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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id c205sm3834922oib.40.2021.03.29.20.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 20:29:06 -0700 (PDT) Date: Mon, 29 Mar 2021 22:29:04 -0500 From: Bjorn Andersson To: Dmitry Baryshkov Cc: Andy Gross , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Manu Gautam , Stephen Boyd , Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v5 4/7] phy: qcom-qmp: rename common registers Message-ID: References: <20210328205257.3348866-1-dmitry.baryshkov@linaro.org> <20210328205257.3348866-5-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210328205257.3348866-5-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Sun 28 Mar 15:52 CDT 2021, Dmitry Baryshkov wrote: > A plenty of DP PHY registers are common between V3 and V4. To simplify > V4 code, rename all common registers. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 50 ++++++++++++++--------------- > drivers/phy/qualcomm/phy-qcom-qmp.h | 37 ++++++++++----------- > 2 files changed, 44 insertions(+), 43 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > index 4150096fd350..097bc005ba43 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > @@ -2435,20 +2435,20 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) > { > writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | > DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, > - qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); > + qphy->pcs + QSERDES_DP_PHY_PD_CTL); > > /* Turn on BIAS current for PHY/PLL */ > writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | > QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, > qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); > > - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); > + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); > > writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | > DP_PHY_PD_CTL_LANE_0_1_PWRDN | > DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | > DP_PHY_PD_CTL_DP_CLAMP_EN, > - qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); > + qphy->pcs + QSERDES_DP_PHY_PD_CTL); > > writel(QSERDES_V3_COM_BIAS_EN | > QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | > @@ -2456,16 +2456,16 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) > QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, > qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); > > - writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0); > - writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); > - writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); > - writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3); > - writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4); > - writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5); > - writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6); > - writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7); > - writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8); > - writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9); > + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); > + writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); > + writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); > + writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); > + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); > + writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); > + writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); > + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); > + writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); > + writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); > qphy->dp_aux_cfg = 0; > > writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | > @@ -2556,9 +2556,9 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) > * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); > */ > val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; > - writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); > + writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); > > - writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); > + writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); > writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); > writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); > > @@ -2588,11 +2588,11 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) > clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); > clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); > > - writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2); > - writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > - writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > - writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > - writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); > + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); > + writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); > + writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); > + writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); > > writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); > > @@ -2603,7 +2603,7 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) > 10000)) > return -ETIMEDOUT; > > - writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); > > if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, > status, > @@ -2612,9 +2612,9 @@ static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) > 10000)) > return -ETIMEDOUT; > > - writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); > udelay(2000); > - writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG); > + writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); > > return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, > status, > @@ -2636,7 +2636,7 @@ static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) > qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); > val = cfg1_settings[qphy->dp_aux_cfg]; > > - writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1); > + writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); > > return 0; > } > @@ -3898,7 +3898,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy) > > if (cfg->type == PHY_TYPE_DP) { > /* Assert DP PHY power down */ > - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL); > + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); > } else { > /* PHY reset */ > if (!cfg->no_pcs_sw_reset) > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h > index 71ce3aa174ae..981d8ee891c0 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h > @@ -349,13 +349,13 @@ > #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c > #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 > > -/* Only for QMP V3 PHY - DP PHY registers */ > -#define QSERDES_V3_DP_PHY_REVISION_ID0 0x000 > -#define QSERDES_V3_DP_PHY_REVISION_ID1 0x004 > -#define QSERDES_V3_DP_PHY_REVISION_ID2 0x008 > -#define QSERDES_V3_DP_PHY_REVISION_ID3 0x00c > -#define QSERDES_V3_DP_PHY_CFG 0x010 > -#define QSERDES_V3_DP_PHY_PD_CTL 0x018 > +/* QMP PHY - DP PHY registers */ > +#define QSERDES_DP_PHY_REVISION_ID0 0x000 > +#define QSERDES_DP_PHY_REVISION_ID1 0x004 > +#define QSERDES_DP_PHY_REVISION_ID2 0x008 > +#define QSERDES_DP_PHY_REVISION_ID3 0x00c > +#define QSERDES_DP_PHY_CFG 0x010 > +#define QSERDES_DP_PHY_PD_CTL 0x018 > # define DP_PHY_PD_CTL_PWRDN 0x001 > # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 > # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 > @@ -363,18 +363,19 @@ > # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 > # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 > # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 > -#define QSERDES_V3_DP_PHY_MODE 0x01c > -#define QSERDES_V3_DP_PHY_AUX_CFG0 0x020 > -#define QSERDES_V3_DP_PHY_AUX_CFG1 0x024 > -#define QSERDES_V3_DP_PHY_AUX_CFG2 0x028 > -#define QSERDES_V3_DP_PHY_AUX_CFG3 0x02c > -#define QSERDES_V3_DP_PHY_AUX_CFG4 0x030 > -#define QSERDES_V3_DP_PHY_AUX_CFG5 0x034 > -#define QSERDES_V3_DP_PHY_AUX_CFG6 0x038 > -#define QSERDES_V3_DP_PHY_AUX_CFG7 0x03c > -#define QSERDES_V3_DP_PHY_AUX_CFG8 0x040 > -#define QSERDES_V3_DP_PHY_AUX_CFG9 0x044 > +#define QSERDES_DP_PHY_MODE 0x01c > +#define QSERDES_DP_PHY_AUX_CFG0 0x020 > +#define QSERDES_DP_PHY_AUX_CFG1 0x024 > +#define QSERDES_DP_PHY_AUX_CFG2 0x028 > +#define QSERDES_DP_PHY_AUX_CFG3 0x02c > +#define QSERDES_DP_PHY_AUX_CFG4 0x030 > +#define QSERDES_DP_PHY_AUX_CFG5 0x034 > +#define QSERDES_DP_PHY_AUX_CFG6 0x038 > +#define QSERDES_DP_PHY_AUX_CFG7 0x03c > +#define QSERDES_DP_PHY_AUX_CFG8 0x040 > +#define QSERDES_DP_PHY_AUX_CFG9 0x044 > > +/* Only for QMP V3 PHY - DP PHY registers */ > #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 > # define PHY_AUX_STOP_ERR_MASK 0x01 > # define PHY_AUX_DEC_ERR_MASK 0x02 > -- > 2.30.2 >