* [PATCH 0/3] Add support for PCIe PHY in SDX55
@ 2021-04-27 6:53 Manivannan Sadhasivam
2021-04-27 6:53 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY Manivannan Sadhasivam
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2021-04-27 6:53 UTC (permalink / raw)
To: vkoul, kishon, robh+dt
Cc: bjorn.andersson, linux-arm-msm, linux-kernel, devicetree,
Manivannan Sadhasivam
Hi,
This series adds support for PCIe PHY found in Qualcomm SDX55 platform.
The PHY version is v4.20 which has different register offsets compared with
previous v4.0x versions. So separate defines are introducted to handle the
differences.
This series has been tested on Telit FN980 EVB with an out of tree PCIe Endpoint
driver.
Thanks,
Mani
Manivannan Sadhasivam (3):
dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY
phy: qcom-qmp: Use phy_status field for the status bit offset
phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 +
drivers/phy/qualcomm/phy-qcom-qmp.c | 160 +++++++++++++++++-
drivers/phy/qualcomm/phy-qcom-qmp.h | 64 ++++++-
3 files changed, 224 insertions(+), 2 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY 2021-04-27 6:53 [PATCH 0/3] Add support for PCIe PHY in SDX55 Manivannan Sadhasivam @ 2021-04-27 6:53 ` Manivannan Sadhasivam 2021-05-03 19:13 ` Rob Herring 2021-05-29 16:25 ` Bjorn Andersson 2021-04-27 6:53 ` [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset Manivannan Sadhasivam ` (2 subsequent siblings) 3 siblings, 2 replies; 9+ messages in thread From: Manivannan Sadhasivam @ 2021-04-27 6:53 UTC (permalink / raw) To: vkoul, kishon, robh+dt Cc: bjorn.andersson, linux-arm-msm, linux-kernel, devicetree, Manivannan Sadhasivam Add devicetree binding for PCIe PHY found in Qcom SDX55 platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 626447fee092..d5162d58a479 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -43,6 +43,7 @@ properties: - qcom,sm8350-qmp-ufs-phy - qcom,sm8350-qmp-usb3-phy - qcom,sm8350-qmp-usb3-uni-phy + - qcom,sdx55-qmp-pcie-phy - qcom,sdx55-qmp-usb3-uni-phy reg: @@ -301,6 +302,7 @@ allOf: enum: - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY 2021-04-27 6:53 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY Manivannan Sadhasivam @ 2021-05-03 19:13 ` Rob Herring 2021-05-29 16:25 ` Bjorn Andersson 1 sibling, 0 replies; 9+ messages in thread From: Rob Herring @ 2021-05-03 19:13 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: linux-kernel, vkoul, kishon, bjorn.andersson, devicetree, robh+dt, linux-arm-msm On Tue, 27 Apr 2021 12:23:58 +0530, Manivannan Sadhasivam wrote: > Add devicetree binding for PCIe PHY found in Qcom SDX55 platform. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY 2021-04-27 6:53 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY Manivannan Sadhasivam 2021-05-03 19:13 ` Rob Herring @ 2021-05-29 16:25 ` Bjorn Andersson 1 sibling, 0 replies; 9+ messages in thread From: Bjorn Andersson @ 2021-05-29 16:25 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: vkoul, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree On Tue 27 Apr 01:53 CDT 2021, Manivannan Sadhasivam wrote: > Add devicetree binding for PCIe PHY found in Qcom SDX55 platform. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml > index 626447fee092..d5162d58a479 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml > @@ -43,6 +43,7 @@ properties: > - qcom,sm8350-qmp-ufs-phy > - qcom,sm8350-qmp-usb3-phy > - qcom,sm8350-qmp-usb3-uni-phy > + - qcom,sdx55-qmp-pcie-phy > - qcom,sdx55-qmp-usb3-uni-phy > > reg: > @@ -301,6 +302,7 @@ allOf: > enum: > - qcom,sdm845-qhp-pcie-phy > - qcom,sdm845-qmp-pcie-phy > + - qcom,sdx55-qmp-pcie-phy > - qcom,sm8250-qmp-gen3x1-pcie-phy > - qcom,sm8250-qmp-gen3x2-pcie-phy > - qcom,sm8250-qmp-modem-pcie-phy > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset 2021-04-27 6:53 [PATCH 0/3] Add support for PCIe PHY in SDX55 Manivannan Sadhasivam 2021-04-27 6:53 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY Manivannan Sadhasivam @ 2021-04-27 6:53 ` Manivannan Sadhasivam 2021-05-29 17:02 ` Bjorn Andersson 2021-04-27 6:54 ` [PATCH 3/3] phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY Manivannan Sadhasivam 2021-05-31 6:08 ` [PATCH 0/3] Add support for PCIe PHY in SDX55 Vinod Koul 3 siblings, 1 reply; 9+ messages in thread From: Manivannan Sadhasivam @ 2021-04-27 6:53 UTC (permalink / raw) To: vkoul, kishon, robh+dt Cc: bjorn.andersson, linux-arm-msm, linux-kernel, devicetree, Manivannan Sadhasivam In preparation of the support for v4.20 PCIe PHY in SDX55, use a separate "phy_status" field for the status bit offset. This is needed because, the v4.20 PHY uses a different offset for the PHY Status. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 9cdebe7f26cb..c9934b2407c4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -2323,6 +2323,8 @@ struct qmp_phy_cfg { unsigned int start_ctrl; unsigned int pwrdn_ctrl; unsigned int mask_com_pcs_ready; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; /* true, if PHY has a separate PHY_COM control block */ bool has_phy_com_ctrl; @@ -2526,6 +2528,7 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, }; static const struct qmp_phy_cfg msm8996_pciephy_cfg = { @@ -2551,6 +2554,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { .start_ctrl = PCS_START | PLL_READY_GATE_EN, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .mask_com_pcs_ready = PCS_READY, + .phy_status = PHYSTATUS, .has_phy_com_ctrl = true, .has_lane_rst = true, @@ -2580,6 +2584,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .no_pcs_sw_reset = true, }; @@ -2606,6 +2611,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, }; static const char * const ipq8074_pciephy_clk_l[] = { @@ -2638,6 +2644,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .has_phy_com_ctrl = false, .has_lane_rst = false, @@ -2670,6 +2677,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { .start_ctrl = PCS_START | SERDES_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ @@ -2698,6 +2706,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { .start_ctrl = PCS_START | SERDES_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ @@ -2736,6 +2745,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { .start_ctrl = PCS_START | SERDES_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ @@ -2774,6 +2784,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { .start_ctrl = PCS_START | SERDES_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, .has_pwrdn_delay = true, @@ -2803,6 +2814,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -2834,6 +2846,7 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -2900,6 +2913,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -2926,6 +2940,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, .no_pcs_sw_reset = true, @@ -2953,6 +2968,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, }; static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { @@ -2977,6 +2993,7 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, }; @@ -3001,6 +3018,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, }; @@ -3027,6 +3045,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, + .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3058,6 +3078,7 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3086,6 +3107,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3117,6 +3139,7 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3145,6 +3168,7 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3171,6 +3195,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .is_dual_lane_phy = true, }; @@ -3197,6 +3222,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3228,6 +3254,7 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, @@ -3843,7 +3870,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) ready = PCS_READY; } else { status = pcs + cfg->regs[QPHY_PCS_STATUS]; - mask = PHYSTATUS; + mask = cfg->phy_status; ready = 0; } -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset 2021-04-27 6:53 ` [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset Manivannan Sadhasivam @ 2021-05-29 17:02 ` Bjorn Andersson 0 siblings, 0 replies; 9+ messages in thread From: Bjorn Andersson @ 2021-05-29 17:02 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: vkoul, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree On Tue 27 Apr 01:53 CDT 2021, Manivannan Sadhasivam wrote: > In preparation of the support for v4.20 PCIe PHY in SDX55, use a > separate "phy_status" field for the status bit offset. This is needed > because, the v4.20 PHY uses a different offset for the PHY Status. Nit. I think "...uses a different bit for..." would be better. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 29 ++++++++++++++++++++++++++++- > 1 file changed, 28 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > index 9cdebe7f26cb..c9934b2407c4 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > @@ -2323,6 +2323,8 @@ struct qmp_phy_cfg { > unsigned int start_ctrl; > unsigned int pwrdn_ctrl; > unsigned int mask_com_pcs_ready; > + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ > + unsigned int phy_status; > > /* true, if PHY has a separate PHY_COM control block */ > bool has_phy_com_ctrl; > @@ -2526,6 +2528,7 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > }; > > static const struct qmp_phy_cfg msm8996_pciephy_cfg = { > @@ -2551,6 +2554,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { > .start_ctrl = PCS_START | PLL_READY_GATE_EN, > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > .mask_com_pcs_ready = PCS_READY, > + .phy_status = PHYSTATUS, > > .has_phy_com_ctrl = true, > .has_lane_rst = true, > @@ -2580,6 +2584,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { > > .start_ctrl = SERDES_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .no_pcs_sw_reset = true, > }; > @@ -2606,6 +2611,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > }; > > static const char * const ipq8074_pciephy_clk_l[] = { > @@ -2638,6 +2644,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > + .phy_status = PHYSTATUS, > > .has_phy_com_ctrl = false, > .has_lane_rst = false, > @@ -2670,6 +2677,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { > > .start_ctrl = PCS_START | SERDES_START, > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = 995, /* us */ > @@ -2698,6 +2706,7 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { > > .start_ctrl = PCS_START | SERDES_START, > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = 995, /* us */ > @@ -2736,6 +2745,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { > > .start_ctrl = PCS_START | SERDES_START, > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = 995, /* us */ > @@ -2774,6 +2784,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { > > .start_ctrl = PCS_START | SERDES_START, > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > + .phy_status = PHYSTATUS, > > .is_dual_lane_phy = true, > .has_pwrdn_delay = true, > @@ -2803,6 +2814,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -2834,6 +2846,7 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -2900,6 +2913,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -2926,6 +2940,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { > > .start_ctrl = SERDES_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .is_dual_lane_phy = true, > .no_pcs_sw_reset = true, > @@ -2953,6 +2968,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, > + .phy_status = PHYSTATUS, > }; > > static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { > @@ -2977,6 +2993,7 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .is_dual_lane_phy = true, > }; > @@ -3001,6 +3018,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { > > .start_ctrl = SERDES_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .is_dual_lane_phy = true, > }; > @@ -3027,6 +3045,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > + > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -3058,6 +3078,7 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -3086,6 +3107,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -3117,6 +3139,7 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -3145,6 +3168,7 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -3171,6 +3195,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { > > .start_ctrl = SERDES_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .is_dual_lane_phy = true, > }; > @@ -3197,6 +3222,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -3228,6 +3254,7 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { > > .start_ctrl = SERDES_START | PCS_START, > .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS, > > .has_pwrdn_delay = true, > .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, > @@ -3843,7 +3870,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) > ready = PCS_READY; > } else { > status = pcs + cfg->regs[QPHY_PCS_STATUS]; > - mask = PHYSTATUS; > + mask = cfg->phy_status; > ready = 0; > } > > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY 2021-04-27 6:53 [PATCH 0/3] Add support for PCIe PHY in SDX55 Manivannan Sadhasivam 2021-04-27 6:53 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY Manivannan Sadhasivam 2021-04-27 6:53 ` [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset Manivannan Sadhasivam @ 2021-04-27 6:54 ` Manivannan Sadhasivam 2021-05-29 17:05 ` Bjorn Andersson 2021-05-31 6:08 ` [PATCH 0/3] Add support for PCIe PHY in SDX55 Vinod Koul 3 siblings, 1 reply; 9+ messages in thread From: Manivannan Sadhasivam @ 2021-04-27 6:54 UTC (permalink / raw) To: vkoul, kishon, robh+dt Cc: bjorn.andersson, linux-arm-msm, linux-kernel, devicetree, Manivannan Sadhasivam The PCIe PHY version used in SDX55 is v4.20 which has different register offsets compared to the v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/phy/qualcomm/phy-qcom-qmp.c | 131 ++++++++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 64 +++++++++++++- 2 files changed, 194 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index c9934b2407c4..bf4d8f22475c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -35,6 +35,7 @@ #define PLL_READY_GATE_EN BIT(3) /* QPHY_PCS_STATUS bit */ #define PHYSTATUS BIT(6) +#define PHYSTATUS_4_20 BIT(7) /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ #define PCS_READY BIT(0) @@ -2030,6 +2031,101 @@ static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), }; +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -3175,6 +3271,38 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, }; +static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 2, + + .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), + .tx_tbl = sdx55_qmp_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), + .rx_tbl = sdx55_qmp_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), + .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), + .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .start_ctrl = PCS_START | SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS_4_20, + + .is_dual_lane_phy = true, + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .type = PHY_TYPE_UFS, .nlanes = 2, @@ -4619,6 +4747,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sm8250-qmp-modem-pcie-phy", .data = &sm8250_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sdx55-qmp-pcie-phy", + .data = &sdx55_qmp_pciephy_cfg, }, { .compatible = "qcom,sdx55-qmp-usb3-uni-phy", .data = &sdx55_usb3_uniphy_cfg, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 71ce3aa174ae..27de9749560a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -396,6 +396,7 @@ #define QSERDES_V3_DP_PHY_STATUS 0x0c0 /* Only for QMP V4 PHY - QSERDES COM registers */ +#define QSERDES_V4_COM_BG_TIMER 0x00c #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 #define QSERDES_V4_COM_SSC_PER1 0x01c #define QSERDES_V4_COM_SSC_PER2 0x020 @@ -403,7 +404,9 @@ #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 #define QSERDES_V4_COM_CLK_ENABLE1 0x048 +#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 #define QSERDES_V4_COM_PLL_IVCO 0x058 #define QSERDES_V4_COM_CMN_IPTRIM 0x060 @@ -415,6 +418,7 @@ #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 +#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 @@ -427,6 +431,10 @@ #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 +#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec +#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 +#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 +#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 @@ -436,13 +444,19 @@ #define QSERDES_V4_COM_CLK_SELECT 0x154 #define QSERDES_V4_COM_HSCLK_SEL 0x158 #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c +#define QSERDES_V4_COM_CMN_CONFIG 0x17c #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 +#define QSERDES_V4_COM_CMN_MISC1 0x19c +#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 +#define QSERDES_V4_COM_CMN_MODE 0x1a4 +#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 -#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 +#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc /* Only for QMP V4 PHY - TX registers */ #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 @@ -459,6 +473,13 @@ #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 +/* Only for QMP V4_20 PHY - TX registers */ +#define QSERDES_V4_20_TX_LANE_MODE_1 0x88 +#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c +#define QSERDES_V4_20_TX_LANE_MODE_3 0x90 +#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 +#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 + /* Only for QMP V4 PHY - RX registers */ #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 @@ -514,6 +535,33 @@ #define QSERDES_V4_RX_DCC_CTRL1 0x1bc #define QSERDES_V4_RX_VTH_CODE 0x1c4 +/* Only for QMP V4_20 PHY - RX registers */ +#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 +#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 +#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac +#define QSERDES_V4_20_RX_DFE_3 0x110 +#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 +#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 +#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 +#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc +#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 +#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c +#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c + /* Only for QMP V4 PHY - UFS PCS registers */ #define QPHY_V4_PCS_UFS_PHY_START 0x000 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 @@ -799,6 +847,12 @@ #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 +/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ +#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 +#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 +#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 + /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 @@ -824,6 +878,14 @@ #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 +#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 +#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 +#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 +#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 + /* Only for QMP V5 PHY - QSERDES COM registers */ #define QSERDES_V5_COM_PLL_IVCO 0x058 #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY 2021-04-27 6:54 ` [PATCH 3/3] phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY Manivannan Sadhasivam @ 2021-05-29 17:05 ` Bjorn Andersson 0 siblings, 0 replies; 9+ messages in thread From: Bjorn Andersson @ 2021-05-29 17:05 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: vkoul, kishon, robh+dt, linux-arm-msm, linux-kernel, devicetree On Tue 27 Apr 01:54 CDT 2021, Manivannan Sadhasivam wrote: > The PCIe PHY version used in SDX55 is v4.20 which has different register > offsets compared to the v4.0x PHYs. So separate register defines are > used for init sequence and PHY status. > I've not reviewed the sequences, but the rest looks good. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 131 ++++++++++++++++++++++++++++ > drivers/phy/qualcomm/phy-qcom-qmp.h | 64 +++++++++++++- > 2 files changed, 194 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > index c9934b2407c4..bf4d8f22475c 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > @@ -35,6 +35,7 @@ > #define PLL_READY_GATE_EN BIT(3) > /* QPHY_PCS_STATUS bit */ > #define PHYSTATUS BIT(6) > +#define PHYSTATUS_4_20 BIT(7) > /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ > #define PCS_READY BIT(0) > > @@ -2030,6 +2031,101 @@ static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { > QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), > }; > > +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), > + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), > +}; > + > +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), > +}; > + > +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), > + QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), > +}; > + > +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), > +}; > + > +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), > + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), > +}; > + > static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { > QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), > QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), > @@ -3175,6 +3271,38 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { > .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, > }; > > +static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { > + .type = PHY_TYPE_PCIE, > + .nlanes = 2, > + > + .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, > + .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), > + .tx_tbl = sdx55_qmp_pcie_tx_tbl, > + .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), > + .rx_tbl = sdx55_qmp_pcie_rx_tbl, > + .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), > + .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, > + .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), > + .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, > + .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), > + .clk_list = sdm845_pciephy_clk_l, > + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), > + .reset_list = sdm845_pciephy_reset_l, > + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), > + .vreg_list = qmp_phy_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > + .regs = sm8250_pcie_regs_layout, > + > + .start_ctrl = PCS_START | SERDES_START, > + .pwrdn_ctrl = SW_PWRDN, > + .phy_status = PHYSTATUS_4_20, > + > + .is_dual_lane_phy = true, > + .has_pwrdn_delay = true, > + .pwrdn_delay_min = 995, /* us */ > + .pwrdn_delay_max = 1005, /* us */ > +}; > + > static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { > .type = PHY_TYPE_UFS, > .nlanes = 2, > @@ -4619,6 +4747,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { > }, { > .compatible = "qcom,sm8250-qmp-modem-pcie-phy", > .data = &sm8250_qmp_gen3x2_pciephy_cfg, > + }, { > + .compatible = "qcom,sdx55-qmp-pcie-phy", > + .data = &sdx55_qmp_pciephy_cfg, > }, { > .compatible = "qcom,sdx55-qmp-usb3-uni-phy", > .data = &sdx55_usb3_uniphy_cfg, > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h > index 71ce3aa174ae..27de9749560a 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h > @@ -396,6 +396,7 @@ > #define QSERDES_V3_DP_PHY_STATUS 0x0c0 > > /* Only for QMP V4 PHY - QSERDES COM registers */ > +#define QSERDES_V4_COM_BG_TIMER 0x00c > #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 > #define QSERDES_V4_COM_SSC_PER1 0x01c > #define QSERDES_V4_COM_SSC_PER2 0x020 > @@ -403,7 +404,9 @@ > #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 > #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 > #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 > +#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 > #define QSERDES_V4_COM_CLK_ENABLE1 0x048 > +#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c > #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 > #define QSERDES_V4_COM_PLL_IVCO 0x058 > #define QSERDES_V4_COM_CMN_IPTRIM 0x060 > @@ -415,6 +418,7 @@ > #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 > #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 > #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 > +#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 > #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac > #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 > #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 > @@ -427,6 +431,10 @@ > #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 > #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc > #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 > +#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec > +#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 > +#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 > +#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 > #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c > #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 > #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 > @@ -436,13 +444,19 @@ > #define QSERDES_V4_COM_CLK_SELECT 0x154 > #define QSERDES_V4_COM_HSCLK_SEL 0x158 > #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c > +#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 > #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c > +#define QSERDES_V4_COM_CMN_CONFIG 0x17c > #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 > +#define QSERDES_V4_COM_CMN_MISC1 0x19c > +#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 > +#define QSERDES_V4_COM_CMN_MODE 0x1a4 > +#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 > #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac > #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 > #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 > -#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc > #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 > +#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc > > /* Only for QMP V4 PHY - TX registers */ > #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 > @@ -459,6 +473,13 @@ > #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 > #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 > > +/* Only for QMP V4_20 PHY - TX registers */ > +#define QSERDES_V4_20_TX_LANE_MODE_1 0x88 > +#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c > +#define QSERDES_V4_20_TX_LANE_MODE_3 0x90 > +#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 > +#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 > + > /* Only for QMP V4 PHY - RX registers */ > #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 > #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 > @@ -514,6 +535,33 @@ > #define QSERDES_V4_RX_DCC_CTRL1 0x1bc > #define QSERDES_V4_RX_VTH_CODE 0x1c4 > > +/* Only for QMP V4_20 PHY - RX registers */ > +#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 > +#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 > +#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac > +#define QSERDES_V4_20_RX_DFE_3 0x110 > +#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 > +#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 > +#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 > +#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 > +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 > +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc > +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 > +#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 > +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 > +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc > +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 > +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 > +#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 > +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec > +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 > +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 > +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 > +#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc > +#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 > +#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c > +#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c > + > /* Only for QMP V4 PHY - UFS PCS registers */ > #define QPHY_V4_PCS_UFS_PHY_START 0x000 > #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 > @@ -799,6 +847,12 @@ > #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 > #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 > > +/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ > +#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 > +#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 > +#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 > +#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 > + > /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ > #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 > #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 > @@ -824,6 +878,14 @@ > #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc > #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 > > +#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 > +#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 > +#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 > +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc > +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 > +#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 > +#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 > + > /* Only for QMP V5 PHY - QSERDES COM registers */ > #define QSERDES_V5_COM_PLL_IVCO 0x058 > #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] Add support for PCIe PHY in SDX55 2021-04-27 6:53 [PATCH 0/3] Add support for PCIe PHY in SDX55 Manivannan Sadhasivam ` (2 preceding siblings ...) 2021-04-27 6:54 ` [PATCH 3/3] phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY Manivannan Sadhasivam @ 2021-05-31 6:08 ` Vinod Koul 3 siblings, 0 replies; 9+ messages in thread From: Vinod Koul @ 2021-05-31 6:08 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: kishon, robh+dt, bjorn.andersson, linux-arm-msm, linux-kernel, devicetree On 27-04-21, 12:23, Manivannan Sadhasivam wrote: > Hi, > > This series adds support for PCIe PHY found in Qualcomm SDX55 platform. > The PHY version is v4.20 which has different register offsets compared with > previous v4.0x versions. So separate defines are introducted to handle the > differences. > > This series has been tested on Telit FN980 EVB with an out of tree PCIe Endpoint > driver. Applied, thanks I got a conflict on last patch as Dimitry has already added some defines in the header.. Pls check everything was applied cleanly Thanks -- ~Vinod ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-05-31 6:09 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-04-27 6:53 [PATCH 0/3] Add support for PCIe PHY in SDX55 Manivannan Sadhasivam 2021-04-27 6:53 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY Manivannan Sadhasivam 2021-05-03 19:13 ` Rob Herring 2021-05-29 16:25 ` Bjorn Andersson 2021-04-27 6:53 ` [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset Manivannan Sadhasivam 2021-05-29 17:02 ` Bjorn Andersson 2021-04-27 6:54 ` [PATCH 3/3] phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY Manivannan Sadhasivam 2021-05-29 17:05 ` Bjorn Andersson 2021-05-31 6:08 ` [PATCH 0/3] Add support for PCIe PHY in SDX55 Vinod Koul
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