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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 94sm1451218otj.33.2021.06.05.19.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jun 2021 19:15:40 -0700 (PDT) Date: Sat, 5 Jun 2021 21:15:38 -0500 From: Bjorn Andersson To: Prasad Malisetty Cc: agross@kernel.org, bhelgaas@google.com, robh+dt@kernel.org, swboyd@chromium.org, lorenzo.pieralisi@arm.com, svarbanov@mm-sol.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, dianders@chromium.org, mka@chromium.org, sanm@codeaurora.org Subject: Re: [PATCH v2 3/4] PCIe: qcom: Add support to control pipe clk mux Message-ID: References: <1622904059-21244-1-git-send-email-pmaliset@codeaurora.org> <1622904059-21244-4-git-send-email-pmaliset@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1622904059-21244-4-git-send-email-pmaliset@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Sat 05 Jun 09:40 CDT 2021, Prasad Malisetty wrote: > In PCIe driver pipe-clk mux needs to switch between pipe_clk > and XO for GDSC enable. This is done by setting pipe_clk mux > as parent of pipe_clk after phy init. But you're not switching between pipe_clk and XO, you're only making sure that the pipe_clk is parented by the PHY's pipe clock. Also, can you please elaborate on how this relates to the GDSC? > > Signed-off-by: Prasad Malisetty > --- > drivers/pci/controller/dwc/pcie-qcom.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 8a7a300..5cbbea4 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -166,6 +166,9 @@ struct qcom_pcie_resources_2_7_0 { > struct regulator_bulk_data supplies[2]; > struct reset_control *pci_reset; > struct clk *pipe_clk; > + struct clk *pipe_clk_mux; > + struct clk *pipe_ext_src; > + struct clk *ref_clk_src; > }; > > union qcom_pcie_resources { > @@ -1167,6 +1170,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > if (ret < 0) > return ret; > > + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280")) { > + res->pipe_clk_mux = devm_clk_get(dev, "pipe_src"); > + if (IS_ERR(res->pipe_clk_mux)) > + return PTR_ERR(res->pipe_clk_mux); > + > + res->pipe_ext_src = devm_clk_get(dev, "pipe_ext"); > + if (IS_ERR(res->pipe_ext_src)) > + return PTR_ERR(res->pipe_ext_src); > + > + res->ref_clk_src = devm_clk_get(dev, "ref"); > + if (IS_ERR(res->ref_clk_src)) > + return PTR_ERR(res->ref_clk_src); > + } > + > res->pipe_clk = devm_clk_get(dev, "pipe"); > return PTR_ERR_OR_ZERO(res->pipe_clk); > } > @@ -1255,6 +1272,11 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) > static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) > { > struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; > + struct dw_pcie *pci = pcie->pci; > + struct device *dev = pci->dev; > + > + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280")) If this is something only found on 7280, you need to document (in the commit message at least) why this does not apply to other platforms with this controller. Thanks, Bjorn > + clk_set_parent(res->pipe_clk_mux, res->pipe_ext_src); > > return clk_prepare_enable(res->pipe_clk); > } > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >