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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id a24sm1466630otr.3.2021.06.05.20.49.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jun 2021 20:49:56 -0700 (PDT) Date: Sat, 5 Jun 2021 22:49:54 -0500 From: Bjorn Andersson To: Roja Rani Yarubandi Cc: agross@kernel.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak , saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com Subject: Re: [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Message-ID: References: <20210604135439.19119-1-rojay@codeaurora.org> <20210604135439.19119-3-rojay@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210604135439.19119-3-rojay@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote: > Add QUPv3 wrapper_0 DT nodes for SC7280 SoC. > > Signed-off-by: Roja Rani Yarubandi > --- > Changes in V3: > - Broken the huge V2 patch into 3 smaller patches. > 1. QSPI DT nodes > 2. QUP wrapper_0 DT nodes > 3. QUP wrapper_1 DT nodes > > Changes in V2: > - As per Doug's comments removed pinmux/pinconf subnodes. > - As per Doug's comments split of SPI, UART nodes has been done. > - Moved QSPI node before aps_smmu as per the order. > > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 97 ++- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 750 +++++++++++++++++++++++- > 2 files changed, 835 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > index d0edffc15736..f57458dbe763 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > @@ -292,6 +292,16 @@ &uart5 { > status = "okay"; > }; > > +&uart7 { > + status = "okay"; > + > + /delete-property/interrupts; > + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, > + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; > + pinctrl-names = "default", "sleep"; > + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; > +}; > + > /* PINCTRL - additions to nodes defined in sc7280.dtsi */ > > &qspi_cs0 { > @@ -307,16 +317,87 @@ &qspi_data01 { > bias-pull-up; > }; > > -&qup_uart5_default { > - tx { > - pins = "gpio46"; Commit message says "add stuff", but somehow uart5 is no longer gpio46/47 and these gpios are no longer specified. Can you roll this in a way where the giant patch actually _only_ adds a whole bunch of stuff? > - drive-strength = <2>; > - bias-disable; > +&qup_uart5_tx { > + drive-strength = <2>; > + bias-disable; > +}; > + Regards, Bjorn