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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id l24sm569847oii.45.2021.06.05.20.53.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jun 2021 20:53:31 -0700 (PDT) Date: Sat, 5 Jun 2021 22:53:30 -0500 From: Bjorn Andersson To: Roja Rani Yarubandi Cc: agross@kernel.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak , saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com Subject: Re: [PATCH V3 3/3] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Message-ID: References: <20210604135439.19119-1-rojay@codeaurora.org> <20210604135439.19119-4-rojay@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210604135439.19119-4-rojay@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote: > Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. > > Signed-off-by: Roja Rani Yarubandi > --- > Changes in V3: > - Broken the huge V2 patch into 3 smaller patches. > 1. QSPI DT nodes > 2. QUP wrapper_0 DT nodes > 3. QUP wrapper_1 DT nodes > > Changes in V2: > - As per Doug's comments removed pinmux/pinconf subnodes. > - As per Doug's comments split of SPI, UART nodes has been done. > - Moved QSPI node before aps_smmu as per the order. > > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 + > arch/arm64/boot/dts/qcom/sc7280.dtsi | 751 ++++++++++++++++++++++++ > 2 files changed, 755 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > index f57458dbe763..bdea9bf4eeca 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > @@ -288,6 +288,10 @@ &qupv3_id_0 { > status = "okay"; > }; > > +&qupv3_id_1 { > + status = "okay"; > +}; > + > &uart5 { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index b783f5622a66..348a34f3448e 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -881,6 +881,437 @@ uart7: serial@99c000 { > }; > }; > > + qupv3_id_1: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0 0x00ac0000 0 0x2000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + iommus = <&apps_smmu 0x43 0x0>; > + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; > + interconnect-names = "qup-core"; We used to have interconnect votes for the wrapper, but I recently merged patches that dropped these for sc7180, so please conclude which way this should be. The rest looks good. Regards, Bjorn