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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id x29sm3534020ooj.10.2021.07.19.13.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 13:08:37 -0700 (PDT) Date: Mon, 19 Jul 2021 15:08:35 -0500 From: Bjorn Andersson To: rojay@codeaurora.org Cc: Stephen Boyd , robh+dt@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak , saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com, rajpat@codeaurora.org Subject: Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node Message-ID: References: <20210604135439.19119-1-rojay@codeaurora.org> <20210604135439.19119-2-rojay@codeaurora.org> <98befc79fc039496b0c12d7983319c92@codeaurora.org> <2ad7a00924b5065bf61c47e8b6d24339@codeaurora.org> <498a2359eec36c6a0b811337ee187df8@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <498a2359eec36c6a0b811337ee187df8@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed 14 Jul 02:47 CDT 2021, rojay@codeaurora.org wrote: > On 2021-07-09 06:26, Stephen Boyd wrote: > > Quoting rojay@codeaurora.org (2021-07-06 02:19:27) > > > On 2021-06-08 13:37, rojay@codeaurora.org wrote: > > > > On 2021-06-06 09:25, Bjorn Andersson wrote: > > > >> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote: > > > >> > > > >>> Add QSPI DT node for SC7280 SoC. > > > >>> > > > >>> Signed-off-by: Roja Rani Yarubandi > > > >>> --- > > > >>> Changes in V3: > > > >>> - Broken the huge V2 patch into 3 smaller patches. > > > >>> 1. QSPI DT nodes > > > >>> 2. QUP wrapper_0 DT nodes > > > >>> 3. QUP wrapper_1 DT nodes > > > >>> > > > >>> Changes in V2: > > > >>> - As per Doug's comments removed pinmux/pinconf subnodes. > > > >>> - As per Doug's comments split of SPI, UART nodes has been done. > > > >>> - Moved QSPI node before aps_smmu as per the order. > > > >>> > > > >>> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++ > > > >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 61 > > > >>> +++++++++++++++++++++++++ > > > >>> 2 files changed, 90 insertions(+) > > > >>> > > > >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > > > >>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > > > >>> index 3900cfc09562..d0edffc15736 100644 > > > >>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > > > >>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > > > >>> @@ -268,6 +268,22 @@ pmr735b_die_temp { > > > >>> }; > > > >>> }; > > > >>> > > > >>> +&qspi { > > > >>> + status = "okay"; > > > >>> + pinctrl-names = "default"; > > > >>> + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; > > > >>> + > > > >>> + flash@0 { > > > >>> + compatible = "jedec,spi-nor"; > > > >>> + reg = <0>; > > > >>> + > > > >>> + /* TODO: Increase frequency after testing */ > > > >>> + spi-max-frequency = <25000000>; > > > >>> + spi-tx-bus-width = <2>; > > > >>> + spi-rx-bus-width = <2>; > > > >>> + }; > > > >>> +}; > > > >>> + > > > >>> &qupv3_id_0 { > > > >>> status = "okay"; > > > >>> }; > > > >>> @@ -278,6 +294,19 @@ &uart5 { > > > >>> > > > >>> /* PINCTRL - additions to nodes defined in sc7280.dtsi */ > > > >>> > > > >>> +&qspi_cs0 { > > > >>> + bias-disable; > > > >>> +}; > > > >>> + > > > >>> +&qspi_clk { > > > >>> + bias-disable; > > > >>> +}; > > > >>> + > > > >>> +&qspi_data01 { > > > >>> + /* High-Z when no transfers; nice to park the lines */ > > > >>> + bias-pull-up; > > > >>> +}; > > > >>> + > > > >>> &qup_uart5_default { > > > >>> tx { > > > >>> pins = "gpio46"; > > > >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > >>> index 6c9d5eb93f93..3047ab802cd2 100644 > > > >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > >>> @@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint { > > > >>> }; > > > >>> }; > > > >>> > > > >>> + qspi_opp_table: qspi-opp-table { > > > >> > > > >> This node doesn't represents anything on the mmio bus, so it shouldn't > > > >> live in in /soc. Can't you move it into &qspi? > > > >> > > > >> Regards, > > > >> Bjorn > > > >> > > > > > > > > Sure, will move it into qspi node. > > > > > > > > Thanks, > > > > Roja > > > > > > > > > > Hi Bjorn, > > > > > > Moving "qspi_opp_table" inside &qspi node causing this warning: > > > arch/arm64/boot/dts/qcom/sc7280.dtsi:1055.35-1072.6: Warning > > > (spi_bus_reg): /soc@0/spi@88dc000/qspi-opp-table: missing or empty reg > > > property > > > > If DT folks are OK I think we should hard-code 'opp-table' as not a > > device for spi to populate on the spi bus and relax the warning in the > > devicetree compiler (see [1] for more details). Technically, nodes that > > are bus controllers assume all child nodes are devices on that bus. In > > this case, we want to stick the opp table as a child of the spi node so > > that it can be called 'opp-table' and not be a node in the root of DT. > > > > > > > > Shall I keep the qspi-opp-table out of &qspi node? > > > > > > > If you do, please move it to / instead of putting it under /soc as it > > doesn't have an address or a reg property. > > > > Hi Bjorn, Rob > > Can we move this "qspi_opp_table" to / from /soc? > If you have made a proper attempt to convince Rob and Mark that a child "opp-table" in a SPI master is not a SPI device - and the conclusion is that this is not a good idea...then yes it should live outside /soc. Thanks, Bjorn