From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0F12C433EF for ; Mon, 20 Sep 2021 00:44:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8238A610CE for ; Mon, 20 Sep 2021 00:44:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231573AbhITAqA (ORCPT ); Sun, 19 Sep 2021 20:46:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229719AbhITAp7 (ORCPT ); Sun, 19 Sep 2021 20:45:59 -0400 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A3CEC061574 for ; Sun, 19 Sep 2021 17:44:33 -0700 (PDT) Received: by mail-ot1-x32a.google.com with SMTP id 97-20020a9d006a000000b00545420bff9eso14418539ota.8 for ; Sun, 19 Sep 2021 17:44:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=lzKqB+hvLZ/JMccnjIuEIhViBFYa45nTJzf1VzPKkQM=; b=geuYnnJgB8GKQG9MHXQWQ9qCeznG/2qiKgr26NIQ2RlTKID2Ai8AQTzC3FHNsffvYm xFN1q2LncnS//Ppt4czKmDJrFUaKFoGGrYNGfSAFV1rHAGpX6VbQHBHZCAeJvMAUukme n+5jxW4GOHoZrPsQ9IJFXuF53SOqYumNaLk00sAzPmCiRFrhvfheG5AcgE4EPYbXrAYc foy2vaQbKs6ykHcdMPF3c0+3ZJNbrKi9sd54wmJ5sCQXx3kAnzmQTew0dDLyuvbdSUMm Mj+Ij/We8jLSmbGR25LHHIYRTEPjqyN7XUufwr59RgN4DDL2OH8bTm7l5BUiZaip99d1 Q3oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=lzKqB+hvLZ/JMccnjIuEIhViBFYa45nTJzf1VzPKkQM=; b=uWSOdC8enHO8nZT+xOLEQiBl4BVMebpJExORd66tny+gEvRSJ7WdQnxgr7NLioMXto 8RXW7lG4vZBbyRDC+ZEQoUrcLnT/e9ayTamcGVlC6o/oYYLbUQ+4pEAdxEwPPz7TBpzR ceEodwgI4z1tBsgJIt9Fh/pNOBLjhtQy/cS4fPezZ0ndGIwPRQ+SWHkxz3tJqWVB5vjG 5j3DGuyFEudYzhzgXuFGhozGQDO6wv8mF+RKaE0wW/pKlrjUppjVgBdgyF8TIrmSqiL6 OApD4SPA1bsKggsK3ZjMcfrcThDkTRRZLiPPIxOjwbqFf2mdYXH4SOuPvD1A0UB6tFJk 3rLw== X-Gm-Message-State: AOAM531rr2lAJX13gOG8tzG0NmMoHyBOERM3Y2XReCkNukTOutSqplRe HLTMYpJeC6UCautlasTTJ0wV6g== X-Google-Smtp-Source: ABdhPJyURgRw9OC2NNBTkmOgiOvyzID7Xviw5xcTBH6RmvJCkZ+rCi5FGlZoYceTmyxZphPwzV4JBw== X-Received: by 2002:a9d:5a9b:: with SMTP id w27mr18814468oth.29.1632098672900; Sun, 19 Sep 2021 17:44:32 -0700 (PDT) Received: from builder.lan (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id f17sm1884382ook.9.2021.09.19.17.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Sep 2021 17:44:32 -0700 (PDT) Date: Sun, 19 Sep 2021 19:44:30 -0500 From: Bjorn Andersson To: Rajendra Nayak Cc: agross@kernel.org, linus.walleij@linaro.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prasad Sodagudi Subject: Re: [PATCH] pinctrl: qcom: Add egpio feature support Message-ID: References: <1631860648-31774-1-git-send-email-rnayak@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1631860648-31774-1-git-send-email-rnayak@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 17 Sep 01:37 CDT 2021, Rajendra Nayak wrote: > From: Prasad Sodagudi > > egpio is a scheme which allows special power Island Domain IOs > (LPASS,SSC) to be reused as regular chip GPIOs by muxing regular > TLMM functions with Island Domain functions. > With this scheme, an IO can be controlled both by the cpu running > linux and the Island processor. This provides great flexibility to > re-purpose the Island IOs for regular TLMM usecases. > > 2 new bits are added to ctl_reg, egpio_present is a read only bit > which shows if egpio feature is available or not on a given gpio. > egpio_enable is the read/write bit and only effective if egpio_present > is 1. Once its set, the Island IO is controlled from Chip TLMM. > egpio_enable when set to 0 means the GPIO is used as Island Domain IO. > > The support exists on most recent qcom SoCs, and we add support > for sm8150/sm8250/sm8350 and sc7280 as part of this patch. > I was under the impression that this feature would allow you to repurpose pins for use either by the remote island or by apps. But if I understand your proposal, you check to see if the pin is "egpio capable" for a pin and if so just sets the bit - muxing it to apps (or the island?). It seems reasonable that this would be another pinmux state for these pins, rather than just flipping them all in one or the other direction. PS. When I spoke with Prasad about this a couple of years ago, I think we talked about representing this as a pinconf property, but it seems to make more sense to me now that it would be a pinmux state. Regards, Bjorn > Signed-off-by: Prasad Sodagudi > [rnayak: rewrite commit log, minor rebase] > Signed-off-by: Rajendra Nayak > --- > drivers/pinctrl/qcom/pinctrl-msm.c | 4 ++++ > drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ > drivers/pinctrl/qcom/pinctrl-sc7280.c | 2 ++ > drivers/pinctrl/qcom/pinctrl-sm8150.c | 2 ++ > drivers/pinctrl/qcom/pinctrl-sm8250.c | 2 ++ > drivers/pinctrl/qcom/pinctrl-sm8350.c | 2 ++ > 6 files changed, 14 insertions(+) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index 8476a8a..f4a2343 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -220,6 +220,10 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, > val = msm_readl_ctl(pctrl, g); > val &= ~mask; > val |= i << g->mux_bit; > + /* Check if egpio present and enable that feature */ > + if (val & BIT(g->egpio_present)) > + val |= BIT(g->egpio_enable); > + > msm_writel_ctl(val, pctrl, g); > > raw_spin_unlock_irqrestore(&pctrl->lock, flags); > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h > index e31a516..3635b31 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.h > +++ b/drivers/pinctrl/qcom/pinctrl-msm.h > @@ -77,6 +77,8 @@ struct msm_pingroup { > unsigned drv_bit:5; > > unsigned od_bit:5; > + unsigned egpio_enable:5; > + unsigned egpio_present:5; > unsigned oe_bit:5; > unsigned in_bit:5; > unsigned out_bit:5; > diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c > index afddf6d..607d459 100644 > --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c > +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c > @@ -43,6 +43,8 @@ > .mux_bit = 2, \ > .pull_bit = 0, \ > .drv_bit = 6, \ > + .egpio_enable = 12, \ > + .egpio_present = 11, \ > .oe_bit = 9, \ > .in_bit = 0, \ > .out_bit = 1, \ > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c > index 7359bae..63a625a 100644 > --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c > +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c > @@ -56,6 +56,8 @@ enum { > .mux_bit = 2, \ > .pull_bit = 0, \ > .drv_bit = 6, \ > + .egpio_enable = 12, \ > + .egpio_present = 11, \ > .oe_bit = 9, \ > .in_bit = 0, \ > .out_bit = 1, \ > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c > index af144e7..ad4fd94 100644 > --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c > +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c > @@ -57,6 +57,8 @@ enum { > .mux_bit = 2, \ > .pull_bit = 0, \ > .drv_bit = 6, \ > + .egpio_enable = 12, \ > + .egpio_present = 11, \ > .oe_bit = 9, \ > .in_bit = 0, \ > .out_bit = 1, \ > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c > index 4d8f863..bb436dc 100644 > --- a/drivers/pinctrl/qcom/pinctrl-sm8350.c > +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c > @@ -46,6 +46,8 @@ > .mux_bit = 2, \ > .pull_bit = 0, \ > .drv_bit = 6, \ > + .egpio_enable = 12, \ > + .egpio_present = 11, \ > .oe_bit = 9, \ > .in_bit = 0, \ > .out_bit = 1, \ > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >