* [PATCH v4 0/2] Add Qualcomm MSM8939 GCC binding and driver
@ 2020-05-12 11:50 Bryan O'Donoghue
2020-05-12 11:50 ` [PATCH v4 1/2] clk: qcom: Add DT bindings for MSM8939 GCC Bryan O'Donoghue
[not found] ` <20200512115023.2856617-3-bryan.odonoghue@linaro.org>
0 siblings, 2 replies; 6+ messages in thread
From: Bryan O'Donoghue @ 2020-05-12 11:50 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, shawn.guo,
p.zabel, vincent.knecht, konradybcio, bryan.odonoghue
V4:
- Moves headers from 1/1 to 0/1 - patch squashing error - Rob
- Identifies licensing as GPL v2.0-only, thanks for pointing this out. - Rob
- Adds Tested-by: Vincent Knecht <vincent.knecht@mailoo.org>, thanks for
testing this. - Vincent
- https://github.com/bryanodonoghue/linux/pull/new/clk-next+msm8939-v2.1
- https://github.com/bryanodonoghue/linux/pull/new/clk-next+msm8939-v4
V3:
This update removes the old clock name arrays which I forgot to prune in
the previous V2.
git diff bod/clk-next+msm8939 bod/clk-next+msm8939-v2.1
V2:
This update does the following
1. Drops code in the probe routine to add xo and sleep_clk. Instead
the DTS for the GCC will need to declare both of those clocks for the
GCC controller.
2. Supplants parent_names for parent_data for all clocks.
3. Squashes down the previous three patches into two.
4. Drops the git log of copying files. The git log makes clear the silicon
is highly similar, so, you can just as easily read the log and do a
diff.
5. Doesn't update the MSM8916 with parent_data.
Happy to do this at a later date but, don't have the time to validate
this properly at the moment. This set focuses on the MSM8939 alone.
6. Dropped comment and boilerplate license text as indicated.
7. Dropped dependency on COMMON_CLK_QCOM seems to not be needed.
8. Easily view the changes here:
git add bod https://github.com/bryanodonoghue/linux.git
git fetch bod
git diff bod/clk-next+msm8939 bod/clk-next+msm8939-v2
V1:
These three patches add support for the MSM8939 Global Clock Controller.
The MSM8939 is a derivation of the MSM8916 sharing the large majority of
its clock settings with MSM8916, however, there are enough changes, in some
cases mutually incompatible changes that necessitate a separate driver.
I thought it was both important and useful to show in the git log the
differences between MSM8916 and MSM8939 so, one patch copies the MSM8916
driver while another patch applies the entire gamut of MSM8939 changes,
squashing down from a git log of approximately 31 separate commits.
For reference that log is here:
https://github.com/bryanodonoghue/linux/pull/new/msm8939-clk-next-reference-log
Generally speaking MSM8939 differes from MSM8916 in two key ways.
- New and higher clock frequencies for existing IP blocks.
- New PLLs to drive those higher frequencies
Bryan O'Donoghue (2):
clk: qcom: Add DT bindings for MSM8939 GCC
clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
.../devicetree/bindings/clock/qcom,gcc.yaml | 3 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-msm8939.c | 3999 +++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8939.h | 206 +
include/dt-bindings/reset/qcom,gcc-msm8939.h | 110 +
6 files changed, 4327 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-msm8939.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8939.h
create mode 100644 include/dt-bindings/reset/qcom,gcc-msm8939.h
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/2] clk: qcom: Add DT bindings for MSM8939 GCC
2020-05-12 11:50 [PATCH v4 0/2] Add Qualcomm MSM8939 GCC binding and driver Bryan O'Donoghue
@ 2020-05-12 11:50 ` Bryan O'Donoghue
2020-05-12 13:58 ` Rob Herring
2020-05-14 21:31 ` Stephen Boyd
[not found] ` <20200512115023.2856617-3-bryan.odonoghue@linaro.org>
1 sibling, 2 replies; 6+ messages in thread
From: Bryan O'Donoghue @ 2020-05-12 11:50 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, shawn.guo,
p.zabel, vincent.knecht, konradybcio, bryan.odonoghue
Add compatible strings and the include files for the MSM8939 GCC.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Vincent Knecht <vincent.knecht@mailoo.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../devicetree/bindings/clock/qcom,gcc.yaml | 3 +
include/dt-bindings/clock/qcom,gcc-msm8939.h | 206 ++++++++++++++++++
include/dt-bindings/reset/qcom,gcc-msm8939.h | 110 ++++++++++
3 files changed, 319 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8939.h
create mode 100644 include/dt-bindings/reset/qcom,gcc-msm8939.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index e533bb0cfd2b..ee0467fb5e31 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -22,6 +22,8 @@ description: |
- dt-bindings/reset/qcom,gcc-ipq6018.h
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+ - dt-bindings/clock/qcom,gcc-msm8939.h
+ - dt-bindings/reset/qcom,gcc-msm8939.h
- dt-bindings/clock/qcom,gcc-msm8660.h
- dt-bindings/reset/qcom,gcc-msm8660.h
- dt-bindings/clock/qcom,gcc-msm8974.h
@@ -41,6 +43,7 @@ properties:
- qcom,gcc-ipq8064
- qcom,gcc-msm8660
- qcom,gcc-msm8916
+ - qcom,gcc-msm8939
- qcom,gcc-msm8960
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8939.h b/include/dt-bindings/clock/qcom,gcc-msm8939.h
new file mode 100644
index 000000000000..0634467c4ce5
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8939.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2020 Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8939_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8939_H
+
+#define GPLL0 0
+#define GPLL0_VOTE 1
+#define BIMC_PLL 2
+#define BIMC_PLL_VOTE 3
+#define GPLL1 4
+#define GPLL1_VOTE 5
+#define GPLL2 6
+#define GPLL2_VOTE 7
+#define PCNOC_BFDCD_CLK_SRC 8
+#define SYSTEM_NOC_BFDCD_CLK_SRC 9
+#define CAMSS_AHB_CLK_SRC 10
+#define APSS_AHB_CLK_SRC 11
+#define CSI0_CLK_SRC 12
+#define CSI1_CLK_SRC 13
+#define GFX3D_CLK_SRC 14
+#define VFE0_CLK_SRC 15
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
+#define BLSP1_UART1_APPS_CLK_SRC 28
+#define BLSP1_UART2_APPS_CLK_SRC 29
+#define CCI_CLK_SRC 30
+#define CAMSS_GP0_CLK_SRC 31
+#define CAMSS_GP1_CLK_SRC 32
+#define JPEG0_CLK_SRC 33
+#define MCLK0_CLK_SRC 34
+#define MCLK1_CLK_SRC 35
+#define CSI0PHYTIMER_CLK_SRC 36
+#define CSI1PHYTIMER_CLK_SRC 37
+#define CPP_CLK_SRC 38
+#define CRYPTO_CLK_SRC 39
+#define GP1_CLK_SRC 40
+#define GP2_CLK_SRC 41
+#define GP3_CLK_SRC 42
+#define BYTE0_CLK_SRC 43
+#define ESC0_CLK_SRC 44
+#define MDP_CLK_SRC 45
+#define PCLK0_CLK_SRC 46
+#define VSYNC_CLK_SRC 47
+#define PDM2_CLK_SRC 48
+#define SDCC1_APPS_CLK_SRC 49
+#define SDCC2_APPS_CLK_SRC 50
+#define APSS_TCU_CLK_SRC 51
+#define USB_HS_SYSTEM_CLK_SRC 52
+#define VCODEC0_CLK_SRC 53
+#define GCC_BLSP1_AHB_CLK 54
+#define GCC_BLSP1_SLEEP_CLK 55
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
+#define GCC_BLSP1_UART1_APPS_CLK 68
+#define GCC_BLSP1_UART2_APPS_CLK 69
+#define GCC_BOOT_ROM_AHB_CLK 70
+#define GCC_CAMSS_CCI_AHB_CLK 71
+#define GCC_CAMSS_CCI_CLK 72
+#define GCC_CAMSS_CSI0_AHB_CLK 73
+#define GCC_CAMSS_CSI0_CLK 74
+#define GCC_CAMSS_CSI0PHY_CLK 75
+#define GCC_CAMSS_CSI0PIX_CLK 76
+#define GCC_CAMSS_CSI0RDI_CLK 77
+#define GCC_CAMSS_CSI1_AHB_CLK 78
+#define GCC_CAMSS_CSI1_CLK 79
+#define GCC_CAMSS_CSI1PHY_CLK 80
+#define GCC_CAMSS_CSI1PIX_CLK 81
+#define GCC_CAMSS_CSI1RDI_CLK 82
+#define GCC_CAMSS_CSI_VFE0_CLK 83
+#define GCC_CAMSS_GP0_CLK 84
+#define GCC_CAMSS_GP1_CLK 85
+#define GCC_CAMSS_ISPIF_AHB_CLK 86
+#define GCC_CAMSS_JPEG0_CLK 87
+#define GCC_CAMSS_JPEG_AHB_CLK 88
+#define GCC_CAMSS_JPEG_AXI_CLK 89
+#define GCC_CAMSS_MCLK0_CLK 90
+#define GCC_CAMSS_MCLK1_CLK 91
+#define GCC_CAMSS_MICRO_AHB_CLK 92
+#define GCC_CAMSS_CSI0PHYTIMER_CLK 93
+#define GCC_CAMSS_CSI1PHYTIMER_CLK 94
+#define GCC_CAMSS_AHB_CLK 95
+#define GCC_CAMSS_TOP_AHB_CLK 96
+#define GCC_CAMSS_CPP_AHB_CLK 97
+#define GCC_CAMSS_CPP_CLK 98
+#define GCC_CAMSS_VFE0_CLK 99
+#define GCC_CAMSS_VFE_AHB_CLK 100
+#define GCC_CAMSS_VFE_AXI_CLK 101
+#define GCC_CRYPTO_AHB_CLK 102
+#define GCC_CRYPTO_AXI_CLK 103
+#define GCC_CRYPTO_CLK 104
+#define GCC_OXILI_GMEM_CLK 105
+#define GCC_GP1_CLK 106
+#define GCC_GP2_CLK 107
+#define GCC_GP3_CLK 108
+#define GCC_MDSS_AHB_CLK 109
+#define GCC_MDSS_AXI_CLK 110
+#define GCC_MDSS_BYTE0_CLK 111
+#define GCC_MDSS_ESC0_CLK 112
+#define GCC_MDSS_MDP_CLK 113
+#define GCC_MDSS_PCLK0_CLK 114
+#define GCC_MDSS_VSYNC_CLK 115
+#define GCC_MSS_CFG_AHB_CLK 116
+#define GCC_OXILI_AHB_CLK 117
+#define GCC_OXILI_GFX3D_CLK 118
+#define GCC_PDM2_CLK 119
+#define GCC_PDM_AHB_CLK 120
+#define GCC_PRNG_AHB_CLK 121
+#define GCC_SDCC1_AHB_CLK 122
+#define GCC_SDCC1_APPS_CLK 123
+#define GCC_SDCC2_AHB_CLK 124
+#define GCC_SDCC2_APPS_CLK 125
+#define GCC_GTCU_AHB_CLK 126
+#define GCC_JPEG_TBU_CLK 127
+#define GCC_MDP_TBU_CLK 128
+#define GCC_SMMU_CFG_CLK 129
+#define GCC_VENUS_TBU_CLK 130
+#define GCC_VFE_TBU_CLK 131
+#define GCC_USB2A_PHY_SLEEP_CLK 132
+#define GCC_USB_HS_AHB_CLK 133
+#define GCC_USB_HS_SYSTEM_CLK 134
+#define GCC_VENUS0_AHB_CLK 135
+#define GCC_VENUS0_AXI_CLK 136
+#define GCC_VENUS0_VCODEC0_CLK 137
+#define BIMC_DDR_CLK_SRC 138
+#define GCC_APSS_TCU_CLK 139
+#define GCC_GFX_TCU_CLK 140
+#define BIMC_GPU_CLK_SRC 141
+#define GCC_BIMC_GFX_CLK 142
+#define GCC_BIMC_GPU_CLK 143
+#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144
+#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145
+#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146
+#define ULTAUDIO_XO_CLK_SRC 147
+#define ULTAUDIO_AHBFABRIC_CLK_SRC 148
+#define CODEC_DIGCODEC_CLK_SRC 149
+#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150
+#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151
+#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152
+#define GCC_ULTAUDIO_STC_XO_CLK 153
+#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154
+#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155
+#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156
+#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157
+#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158
+#define GCC_CODEC_DIGCODEC_CLK 159
+#define GCC_MSS_Q6_BIMC_AXI_CLK 160
+#define GPLL3 161
+#define GPLL3_VOTE 162
+#define GPLL4 163
+#define GPLL4_VOTE 164
+#define GPLL5 165
+#define GPLL5_VOTE 166
+#define GPLL6 167
+#define GPLL6_VOTE 168
+#define BYTE1_CLK_SRC 169
+#define GCC_MDSS_BYTE1_CLK 170
+#define ESC1_CLK_SRC 171
+#define GCC_MDSS_ESC1_CLK 172
+#define PCLK1_CLK_SRC 173
+#define GCC_MDSS_PCLK1_CLK 174
+#define GCC_GFX_TBU_CLK 175
+#define GCC_CPP_TBU_CLK 176
+#define GCC_MDP_RT_TBU_CLK 177
+#define USB_FS_SYSTEM_CLK_SRC 178
+#define USB_FS_IC_CLK_SRC 179
+#define GCC_USB_FS_AHB_CLK 180
+#define GCC_USB_FS_IC_CLK 181
+#define GCC_USB_FS_SYSTEM_CLK 182
+#define GCC_VENUS0_CORE0_VCODEC0_CLK 183
+#define GCC_VENUS0_CORE1_VCODEC0_CLK 184
+#define GCC_OXILI_TIMER_CLK 185
+
+/* Indexes for GDSCs */
+#define BIMC_GDSC 0
+#define VENUS_GDSC 1
+#define MDSS_GDSC 2
+#define JPEG_GDSC 3
+#define VFE_GDSC 4
+#define OXILI_GDSC 5
+#define VENUS_CORE0_GDSC 6
+#define VENUS_CORE1_GDSC 7
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8939.h b/include/dt-bindings/reset/qcom,gcc-msm8939.h
new file mode 100644
index 000000000000..fa41ffeae7a2
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-msm8939.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2020 Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_RESET_MSM_GCC_8939_H
+#define _DT_BINDINGS_RESET_MSM_GCC_8939_H
+
+#define GCC_BLSP1_BCR 0
+#define GCC_BLSP1_QUP1_BCR 1
+#define GCC_BLSP1_UART1_BCR 2
+#define GCC_BLSP1_QUP2_BCR 3
+#define GCC_BLSP1_UART2_BCR 4
+#define GCC_BLSP1_QUP3_BCR 5
+#define GCC_BLSP1_QUP4_BCR 6
+#define GCC_BLSP1_QUP5_BCR 7
+#define GCC_BLSP1_QUP6_BCR 8
+#define GCC_IMEM_BCR 9
+#define GCC_SMMU_BCR 10
+#define GCC_APSS_TCU_BCR 11
+#define GCC_SMMU_XPU_BCR 12
+#define GCC_PCNOC_TBU_BCR 13
+#define GCC_PRNG_BCR 14
+#define GCC_BOOT_ROM_BCR 15
+#define GCC_CRYPTO_BCR 16
+#define GCC_SEC_CTRL_BCR 17
+#define GCC_AUDIO_CORE_BCR 18
+#define GCC_ULT_AUDIO_BCR 19
+#define GCC_DEHR_BCR 20
+#define GCC_SYSTEM_NOC_BCR 21
+#define GCC_PCNOC_BCR 22
+#define GCC_TCSR_BCR 23
+#define GCC_QDSS_BCR 24
+#define GCC_DCD_BCR 25
+#define GCC_MSG_RAM_BCR 26
+#define GCC_MPM_BCR 27
+#define GCC_SPMI_BCR 28
+#define GCC_SPDM_BCR 29
+#define GCC_MM_SPDM_BCR 30
+#define GCC_BIMC_BCR 31
+#define GCC_RBCPR_BCR 32
+#define GCC_TLMM_BCR 33
+#define GCC_USB_HS_BCR 34
+#define GCC_USB2A_PHY_BCR 35
+#define GCC_SDCC1_BCR 36
+#define GCC_SDCC2_BCR 37
+#define GCC_PDM_BCR 38
+#define GCC_SNOC_BUS_TIMEOUT0_BCR 39
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49
+#define GCC_MMSS_BCR 50
+#define GCC_VENUS0_BCR 51
+#define GCC_MDSS_BCR 52
+#define GCC_CAMSS_PHY0_BCR 53
+#define GCC_CAMSS_CSI0_BCR 54
+#define GCC_CAMSS_CSI0PHY_BCR 55
+#define GCC_CAMSS_CSI0RDI_BCR 56
+#define GCC_CAMSS_CSI0PIX_BCR 57
+#define GCC_CAMSS_PHY1_BCR 58
+#define GCC_CAMSS_CSI1_BCR 59
+#define GCC_CAMSS_CSI1PHY_BCR 60
+#define GCC_CAMSS_CSI1RDI_BCR 61
+#define GCC_CAMSS_CSI1PIX_BCR 62
+#define GCC_CAMSS_ISPIF_BCR 63
+#define GCC_CAMSS_CCI_BCR 64
+#define GCC_CAMSS_MCLK0_BCR 65
+#define GCC_CAMSS_MCLK1_BCR 66
+#define GCC_CAMSS_GP0_BCR 67
+#define GCC_CAMSS_GP1_BCR 68
+#define GCC_CAMSS_TOP_BCR 69
+#define GCC_CAMSS_MICRO_BCR 70
+#define GCC_CAMSS_JPEG_BCR 71
+#define GCC_CAMSS_VFE_BCR 72
+#define GCC_CAMSS_CSI_VFE0_BCR 73
+#define GCC_OXILI_BCR 74
+#define GCC_GMEM_BCR 75
+#define GCC_CAMSS_AHB_BCR 76
+#define GCC_MDP_TBU_BCR 77
+#define GCC_GFX_TBU_BCR 78
+#define GCC_GFX_TCU_BCR 79
+#define GCC_MSS_TBU_AXI_BCR 80
+#define GCC_MSS_TBU_GSS_AXI_BCR 81
+#define GCC_MSS_TBU_Q6_AXI_BCR 82
+#define GCC_GTCU_AHB_BCR 83
+#define GCC_SMMU_CFG_BCR 84
+#define GCC_VFE_TBU_BCR 85
+#define GCC_VENUS_TBU_BCR 86
+#define GCC_JPEG_TBU_BCR 87
+#define GCC_PRONTO_TBU_BCR 88
+#define GCC_SMMU_CATS_BCR 89
+#define GCC_BLSP1_UART3_BCR 90
+#define GCC_CAMSS_CSI2_BCR 91
+#define GCC_CAMSS_CSI2PHY_BCR 92
+#define GCC_CAMSS_CSI2RDI_BCR 93
+#define GCC_CAMSS_CSI2PIX_BCR 94
+#define GCC_USB_FS_BCR 95
+#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 96
+#define GCC_CAMSS_MCLK2_BCR 97
+#define GCC_CPP_TBU_BCR 98
+#define GCC_MDP_RT_TBU_BCR 99
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/2] clk: qcom: Add DT bindings for MSM8939 GCC
2020-05-12 11:50 ` [PATCH v4 1/2] clk: qcom: Add DT bindings for MSM8939 GCC Bryan O'Donoghue
@ 2020-05-12 13:58 ` Rob Herring
2020-05-14 21:31 ` Stephen Boyd
1 sibling, 0 replies; 6+ messages in thread
From: Rob Herring @ 2020-05-12 13:58 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: linux-clk, p.zabel, vincent.knecht, devicetree, shawn.guo,
robh+dt, linux-arm-msm, konradybcio, sboyd, mturquette,
linux-kernel, agross, bjorn.andersson
On Tue, 12 May 2020 12:50:22 +0100, Bryan O'Donoghue wrote:
> Add compatible strings and the include files for the MSM8939 GCC.
>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Tested-by: Vincent Knecht <vincent.knecht@mailoo.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> .../devicetree/bindings/clock/qcom,gcc.yaml | 3 +
> include/dt-bindings/clock/qcom,gcc-msm8939.h | 206 ++++++++++++++++++
> include/dt-bindings/reset/qcom,gcc-msm8939.h | 110 ++++++++++
> 3 files changed, 319 insertions(+)
> create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8939.h
> create mode 100644 include/dt-bindings/reset/qcom,gcc-msm8939.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
[not found] ` <20200512115023.2856617-3-bryan.odonoghue@linaro.org>
@ 2020-05-14 21:31 ` Stephen Boyd
2020-05-14 21:42 ` Bryan O'Donoghue
0 siblings, 1 reply; 6+ messages in thread
From: Stephen Boyd @ 2020-05-14 21:31 UTC (permalink / raw)
To: Bryan O'Donoghue, agross, bjorn.andersson, mturquette, robh+dt
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, shawn.guo,
p.zabel, vincent.knecht, konradybcio, bryan.odonoghue
Quoting Bryan O'Donoghue (2020-05-12 04:50:23)
> This patch adds support for the MSM8939 GCC. The MSM8939 is based on the
> MSM8916. MSM8939 is compatible in several ways with MSM8916 but, has
> additional functional blocks added which require additional PLL sources. In
> some cases functional blocks from the MSM8916 have different clock sources
> or different supported frequencies.
>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Is this a co-developed-by tag?
> Tested-by: Vincent Knecht <vincent.knecht@mailoo.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c
> new file mode 100644
> index 000000000000..71081eb23081
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-msm8939.c
> @@ -0,0 +1,3999 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright 2020 Linaro Limited
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/bitops.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +#include <linux/reset-controller.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-msm8939.h>
> +#include <dt-bindings/reset/qcom,gcc-msm8939.h>
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "reset.h"
> +#include "gdsc.h"
> +
> +enum {
> + P_XO,
> + P_GPLL0,
> + P_GPLL0_AUX,
> + P_BIMC,
> + P_GPLL1,
> + P_GPLL1_AUX,
> + P_GPLL2,
> + P_GPLL2_AUX,
> + P_GPLL3,
> + P_GPLL3_AUX,
> + P_GPLL4,
> + P_GPLL5,
> + P_GPLL5_AUX,
> + P_GPLL5_EARLY,
> + P_GPLL6,
> + P_GPLL6_AUX,
> + P_SLEEP_CLK,
> + P_DSI0_PHYPLL_BYTE,
> + P_DSI0_PHYPLL_DSI,
> + P_EXT_PRI_I2S,
> + P_EXT_SEC_I2S,
> + P_EXT_MCLK,
> +};
> +
> +static struct clk_pll gpll0 = {
> + .l_reg = 0x21004,
> + .m_reg = 0x21008,
> + .n_reg = 0x2100c,
> + .config_reg = 0x21010,
> + .mode_reg = 0x21000,
> + .status_reg = 0x2101c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll0",
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xo",
> + .name = "xo",
Please only have .fw_name. The .name field is a fallback, but given that
this is new code there shouldn't be a need for a fallback to the old way
of doing things.
> + },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap gpll0_vote = {
> + .enable_reg = 0x45000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll0_vote",
> + .parent_data = &(const struct clk_parent_data) {
> + .hw = &gpll0.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
> +static struct clk_pll gpll1 = {
> + .l_reg = 0x20004,
> + .m_reg = 0x20008,
> + .n_reg = 0x2000c,
> + .config_reg = 0x20010,
> + .mode_reg = 0x20000,
> + .status_reg = 0x2001c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll1",
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xo",
> + .name = "xo",
> + },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap gpll1_vote = {
> + .enable_reg = 0x45000,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll1_vote",
> + .parent_data = &(const struct clk_parent_data) {
> + .hw = &gpll1.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
> +static struct clk_pll gpll2 = {
> + .l_reg = 0x4a004,
> + .m_reg = 0x4a008,
> + .n_reg = 0x4a00c,
> + .config_reg = 0x4a010,
> + .mode_reg = 0x4a000,
> + .status_reg = 0x4a01c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll2",
[...]
> +
> +static int gcc_msm8939_probe(struct platform_device *pdev)
> +{
> + int ret;
> + struct regmap *regmap;
> +
> + ret = qcom_cc_probe(pdev, &gcc_msm8939_desc);
> + if (ret)
> + return ret;
> +
> + regmap = dev_get_regmap(&pdev->dev, NULL);
> + clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
> + clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
We should probably configure these before registering the clks. Can you
do the usual, map registers, configure stuff, and then
qcom_cc_really_probe()?
> +
> + return 0;
And then this can fail so return an error in case it does.
> +}
> +
> +static struct platform_driver gcc_msm8939_driver = {
> + .probe = gcc_msm8939_probe,
> + .driver = {
> + .name = "gcc-msm8939",
> + .of_match_table = gcc_msm8939_match_table,
> + },
> +};
> +
> +static int __init gcc_msm8939_init(void)
> +{
> + return platform_driver_register(&gcc_msm8939_driver);
> +}
> +core_initcall(gcc_msm8939_init);
> +
> +static void __exit gcc_msm8939_exit(void)
> +{
> + platform_driver_unregister(&gcc_msm8939_driver);
> +}
> +module_exit(gcc_msm8939_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:gcc-msm8939");
The module alias isn't needed right?
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/2] clk: qcom: Add DT bindings for MSM8939 GCC
2020-05-12 11:50 ` [PATCH v4 1/2] clk: qcom: Add DT bindings for MSM8939 GCC Bryan O'Donoghue
2020-05-12 13:58 ` Rob Herring
@ 2020-05-14 21:31 ` Stephen Boyd
1 sibling, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2020-05-14 21:31 UTC (permalink / raw)
To: Bryan O'Donoghue, agross, bjorn.andersson, mturquette, robh+dt
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, shawn.guo,
p.zabel, vincent.knecht, konradybcio, bryan.odonoghue
Quoting Bryan O'Donoghue (2020-05-12 04:50:22)
> Add compatible strings and the include files for the MSM8939 GCC.
>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Tested-by: Vincent Knecht <vincent.knecht@mailoo.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
2020-05-14 21:31 ` [PATCH v4 2/2] clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller Stephen Boyd
@ 2020-05-14 21:42 ` Bryan O'Donoghue
0 siblings, 0 replies; 6+ messages in thread
From: Bryan O'Donoghue @ 2020-05-14 21:42 UTC (permalink / raw)
To: Stephen Boyd, agross, bjorn.andersson, mturquette, robh+dt
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, shawn.guo,
p.zabel, vincent.knecht, konradybcio
On 14/05/2020 22:31, Stephen Boyd wrote:
> Quoting Bryan O'Donoghue (2020-05-12 04:50:23)
>> This patch adds support for the MSM8939 GCC. The MSM8939 is based on the
>> MSM8916. MSM8939 is compatible in several ways with MSM8916 but, has
>> additional functional blocks added which require additional PLL sources. In
>> some cases functional blocks from the MSM8916 have different clock sources
>> or different supported frequencies.
>>
>> Cc: Andy Gross <agross@kernel.org>
>> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Cc: Michael Turquette <mturquette@baylibre.com>
>> Cc: Stephen Boyd <sboyd@kernel.org>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Philipp Zabel <p.zabel@pengutronix.de>
>> Cc: linux-arm-msm@vger.kernel.org
>> Cc: linux-clk@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
>
> Is this a co-developed-by tag?
Yep. I'm squashing down about 30-some internal patches to this one patch
here including one or two from Shawn in this set.
I wasn't quite sure what the etiquette on Co-developed was i.e. it
wasn't something git allowed me to specify with a "git commit -s
--co-developed="xyz"" so I just retained the SOB.
Looking through git logs I see an example
I'll apply a
Co-developed-by: Shawn Guo <shawn.guo@linaro.org>
for v5.
>> +static int gcc_msm8939_probe(struct platform_device *pdev)
>> +{
>> + int ret;
>> + struct regmap *regmap;
>> +
>> + ret = qcom_cc_probe(pdev, &gcc_msm8939_desc);
>> + if (ret)
>> + return ret;
>> +
>> + regmap = dev_get_regmap(&pdev->dev, NULL);
>> + clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
>> + clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
>
> We should probably configure these before registering the clks. Can you
> do the usual, map registers, configure stuff, and then
> qcom_cc_really_probe()?
I think so. If there was a good reason to configure the plls after the
registration, I can't recall what that was, maybe the original flow from
downstream ...
>> +
>> +MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_ALIAS("platform:gcc-msm8939");
>
> The module alias isn't needed right?
Nope g/msm8916/s//msm8939/g - I can zap that.
Thanks for the review.
---
bod
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-05-14 21:42 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-05-12 11:50 [PATCH v4 0/2] Add Qualcomm MSM8939 GCC binding and driver Bryan O'Donoghue
2020-05-12 11:50 ` [PATCH v4 1/2] clk: qcom: Add DT bindings for MSM8939 GCC Bryan O'Donoghue
2020-05-12 13:58 ` Rob Herring
2020-05-14 21:31 ` Stephen Boyd
[not found] ` <20200512115023.2856617-3-bryan.odonoghue@linaro.org>
2020-05-14 21:31 ` [PATCH v4 2/2] clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller Stephen Boyd
2020-05-14 21:42 ` Bryan O'Donoghue
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