From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Gonzalez Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: msm8998: Add ANOC1 SMMU node Date: Thu, 11 Apr 2019 16:49:38 +0200 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Bjorn Andersson , Rob Herring , Mark Rutland Cc: Jeffrey Hugo , MSM , Douglas Anderson , Evan Green , Stanimir Varbanov , Manu Gautam , iommu , Srinivas Kandagatla , Robin Murphy List-Id: linux-arm-msm@vger.kernel.org +robh, +mrutland for DT On 01/04/2019 17:40, Marc Gonzalez wrote: > The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB. > (*) Aggregate Network-on-Chip #1 > > Based on the following DTS downstream: > https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18 > > Signed-off-by: Marc Gonzalez > --- > Changes from v1: > Split off from "PCIe and AR8151 on APQ8098/MSM8998" series > Change compatible string to use qcom,msm8998-smmu-v2 > --- > arch/arm64/boot/dts/qcom/msm8998.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi > index ef71e8f1d102..f807ea3e2c6e 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi > @@ -606,6 +606,21 @@ > #thermal-sensor-cells = <1>; > }; > > + anoc1_smmu: arm,smmu@1680000 { As discussed with Arnd, this should probably be anoc1_smmu: iommu@1680000 > + compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; > + reg = <0x01680000 0x10000>; > + #iommu-cells = <1>; > + > + #global-interrupts = <0>; > + interrupts = > + , > + , > + , > + , > + , > + ; > + }; > + > tcsr_mutex_regs: syscon@1f40000 { > compatible = "syscon"; > reg = <0x1f40000 0x20000>; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A1D9C10F13 for ; Thu, 11 Apr 2019 14:49:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF6FA2077C for ; Thu, 11 Apr 2019 14:49:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726391AbfDKOtk (ORCPT ); Thu, 11 Apr 2019 10:49:40 -0400 Received: from ns.iliad.fr ([212.27.33.1]:57448 "EHLO ns.iliad.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726106AbfDKOtk (ORCPT ); Thu, 11 Apr 2019 10:49:40 -0400 Received: from ns.iliad.fr (localhost [127.0.0.1]) by ns.iliad.fr (Postfix) with ESMTP id EDDBF20D38; Thu, 11 Apr 2019 16:49:38 +0200 (CEST) Received: from [192.168.108.49] (freebox.vlq16.iliad.fr [213.36.7.13]) by ns.iliad.fr (Postfix) with ESMTP id BDB8E20C9E; Thu, 11 Apr 2019 16:49:38 +0200 (CEST) Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: msm8998: Add ANOC1 SMMU node From: Marc Gonzalez To: Bjorn Andersson , Rob Herring , Mark Rutland Cc: Jeffrey Hugo , Vivek Gautam , Manu Gautam , Evan Green , Douglas Anderson , Robin Murphy , Lorenzo Pieralisi , Joerg Roedel , Stanimir Varbanov , Srinivas Kandagatla , MSM , iommu References: Message-ID: Date: Thu, 11 Apr 2019 16:49:38 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Virus-Scanned: ClamAV using ClamSMTP ; ns.iliad.fr ; Thu Apr 11 16:49:39 2019 +0200 (CEST) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Message-ID: <20190411144938.uszGMNd8LP5eHZuIriQA6slXgqCAGO21RSHeut3ayKo@z> +robh, +mrutland for DT On 01/04/2019 17:40, Marc Gonzalez wrote: > The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB. > (*) Aggregate Network-on-Chip #1 > > Based on the following DTS downstream: > https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18 > > Signed-off-by: Marc Gonzalez > --- > Changes from v1: > Split off from "PCIe and AR8151 on APQ8098/MSM8998" series > Change compatible string to use qcom,msm8998-smmu-v2 > --- > arch/arm64/boot/dts/qcom/msm8998.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi > index ef71e8f1d102..f807ea3e2c6e 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi > @@ -606,6 +606,21 @@ > #thermal-sensor-cells = <1>; > }; > > + anoc1_smmu: arm,smmu@1680000 { As discussed with Arnd, this should probably be anoc1_smmu: iommu@1680000 > + compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; > + reg = <0x01680000 0x10000>; > + #iommu-cells = <1>; > + > + #global-interrupts = <0>; > + interrupts = > + , > + , > + , > + , > + , > + ; > + }; > + > tcsr_mutex_regs: syscon@1f40000 { > compatible = "syscon"; > reg = <0x1f40000 0x20000>;