From mboxrd@z Thu Jan 1 00:00:00 1970 From: chandanu@codeaurora.org Subject: Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks Date: Sun, 11 Nov 2018 19:41:56 -0800 Message-ID: References: <1539093467-12123-1-git-send-email-tdas@codeaurora.org> <1539093467-12123-3-git-send-email-tdas@codeaurora.org> <153911726378.119890.5522594539667887860@swboyd.mtv.corp.google.com> <3c4cccca-2c5c-927f-f471-2bbbd71b4155@codeaurora.org> <9c359e26-3708-14b6-f22a-fb529446d325@codeaurora.org> <154083859263.98144.15690571729193618604@swboyd.mtv.corp.google.com> <154091723693.98144.6979314028521443413@swboyd.mtv.corp.google.com> <9c82010f-f3fd-2867-352e-3584ab4ba8f0@codeaurora.org> <154152409835.88331.14046185859724133804@swboyd.mtv.corp.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <154152409835.88331.14046185859724133804@swboyd.mtv.corp.google.com> Sender: linux-kernel-owner@vger.kernel.org To: Stephen Boyd Cc: Michael Turquette , Taniya Das , Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org On 2018-11-06 09:08, Stephen Boyd wrote: > Quoting Taniya Das (2018-10-31 22:02:22) >> + Chandan from Display Port team, >> >> On 10/30/2018 10:03 PM, Stephen Boyd wrote: >> > Also, those >> > numbers look like gigabits per second (Gbit/s) for the DP spec which >> > isn't exactly the same as a clk frequency. What frequency does the PLL >> > run at for these various DP link speeds? >> > >> Could you please help with the above query from Stephen? Hello Stephen, For DP link speed of 5.4Gbit/s, the PLL will be running at 10.8 Ghz. For all the other DP link speeds, the PLL will be running at 8.1 Ghz. > > Can I safely assume that it matches the link rate shown on Wikipedia > for > display port[1]? I.e. > > RBR (Reduced Bit Rate): 1.62 Gbit/s bandwidth per lane (162 MHz link > symbol rate) > HBR (High Bit Rate): 2.70 Gbit/s bandwidth per lane (270 MHz link > symbol rate) > HBR2 (High Bit Rate 2): 5.40 Gbit/s bandwidth per lane (540 MHz link > symbol rate), introduced in DP 1.2 > HBR3 (High Bit Rate 3): 8.10 Gbit/s bandwidth per lane (810 MHz link > symbol rate), introduced in DP 1.3 > > So then they're MHz but the table is written in kHz when it should be > written in Hz. Either way, the table can be removed and then we just > need to fix the DP PHY PLL code to accept Hz instead of kHz. > > [1] https://en.wikipedia.org/wiki/DisplayPort#Main_link