From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71FCBC47082 for ; Mon, 31 May 2021 07:24:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3FDC16100B for ; Mon, 31 May 2021 07:24:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230070AbhEaH0K (ORCPT ); Mon, 31 May 2021 03:26:10 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:25451 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230111AbhEaH0J (ORCPT ); Mon, 31 May 2021 03:26:09 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1622445869; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: Cc: To: Subject: Sender; bh=haTHTuXC1HmWCxguACi3s4xN1NZ67P1q/7nkLTJKnR0=; b=VCh1BFKoCdnmlowj/UDv7vBvEShyAnqK2F5TnXiK1HRmrS7DMlzkAxgti2SxgnCCKO8ITToG enXjmo5KTcybvREZPClNeqNg0bBCCg18aSGU+oeCErd0vFY4xnVcaifOEp5P7MQqNhOOjmdj n/wQ4grfJZ2ul3nCxLhpsHmvYwM= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-east-1.postgun.com with SMTP id 60b48f2c51f29e6baecfdd24 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 31 May 2021 07:24:28 GMT Sender: akhilpo=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 2BD70C4323A; Mon, 31 May 2021 07:24:27 +0000 (UTC) Received: from [192.168.1.105] (unknown [117.210.184.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7541AC433F1; Mon, 31 May 2021 07:24:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7541AC433F1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=akhilpo@codeaurora.org Subject: Re: [PATCH v2 2/8] drm/msm/a6xx: use AOP-initialized PDC for a650 To: Jonathan Marek , freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Eric Anholt , Sharat Masetty , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list References: <20210513171431.18632-1-jonathan@marek.ca> <20210513171431.18632-3-jonathan@marek.ca> From: Akhil P Oommen Message-ID: Date: Mon, 31 May 2021 12:54:20 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: <20210513171431.18632-3-jonathan@marek.ca> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 5/13/2021 10:43 PM, Jonathan Marek wrote: > SM8250 AOP firmware already sets up PDC registers for us, and it only needs > to be enabled. This path will be used for other newer GPUs. > > Signed-off-by: Jonathan Marek > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 3d55e153fa9c..c1ee02d6371d 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -512,19 +512,26 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) > struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; > struct platform_device *pdev = to_platform_device(gmu->dev); > void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); > - void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); > + void __iomem *seqptr; > uint32_t pdc_address_offset; > + bool pdc_in_aop = false; > > - if (!pdcptr || !seqptr) > + if (!pdcptr) > goto err; > > - if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) > + if (adreno_is_a650(adreno_gpu)) > + pdc_in_aop = true; > + else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) > pdc_address_offset = 0x30090; > - else if (adreno_is_a650(adreno_gpu)) > - pdc_address_offset = 0x300a0; > else > pdc_address_offset = 0x30080; > > + if (!pdc_in_aop) { > + seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); > + if (!seqptr) > + goto err; > + } > + > /* Disable SDE clock gating */ > gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); > > @@ -556,6 +563,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) > gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); > } > > + if (pdc_in_aop) > + goto setup_pdc; > + > /* Load PDC sequencer uCode for power up and power down sequence */ > pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); > pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); > @@ -596,6 +606,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) > pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); > > /* Setup GPU PDC */ > +setup_pdc: > pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); > pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); > > We can simply swap the order of PDC and rsc programming here and skip pdc sequence to jump to the rscc programming for a650. This is the order followed in the downstream driver anyway. -Akhil.