From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B26CC433F5 for ; Fri, 13 May 2022 12:40:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377170AbiEMMkE (ORCPT ); Fri, 13 May 2022 08:40:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353953AbiEMMkC (ORCPT ); Fri, 13 May 2022 08:40:02 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 318AE8B097 for ; Fri, 13 May 2022 05:40:01 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id t25so14286782lfg.7 for ; Fri, 13 May 2022 05:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=WZDB7Z12eDc46BTLC2lfW32G/wF1AJbeefP857zfk1I=; b=AXHG4xCifCU8eHr3vEVmEVz7CX1ab+ISwd6QZJXhvTQ077OK2ogJya3YTgriZv8BR4 Fg57x4oH2fk9fM8djQr7SQyu2KJG0ASZ3k4jhDvy2zxlHTecnJZwAmt2V+Y2SlVk5Krl GBsU2ZEtg+BEbEzkcK6KqRgy3NjEYpZf6QRc432NggntsGLNXD7s6zjkhQzL5XrZyKCK 77Pqvf9mQLSahMgUR9MyNPKH1//EPXcrP4tirm/jk4NcAiB7muP9mrT+F/rg5bnIuvdL Nyn+47x3QQuB8vekMTt2+l1CXWQpUFFJUyprxU8jPw0KCIa5o/JRD80rIajD778t1+D+ B1+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=WZDB7Z12eDc46BTLC2lfW32G/wF1AJbeefP857zfk1I=; b=Ei1u6f6sR9buwkGFFqGKJSj+Q5lsgEI+LmFtEdi6HHPPOOvxksntTlFqVzsqx0r3J/ pw0sHQmvqiYFL1PztfEm9lPtM0vWfhYCCTP7CWOtzGK7MOVekqTAD16YexeXvdSN/mKG P3F0iBfI7gCUhBTfdT7dW138dKZ6jGPY2CxgqbwjUiy9DX0xuFDLmWuom66LcdNDq23h Fq6EC+3gQ2m2r+phq3bv1H5miUjYRedkZ8qA39vjyw85HcQFMoORp0ofMfi0ZUEIHK73 gj0rAOdtx6O7QjmmQ6eNSDJIDvBkkfC8hgBzy95O+U3IGRHyAYQXC4ylgVGvrKFiAN7v +m2w== X-Gm-Message-State: AOAM531li+P7A9fDafnD2waBooV/Cx0TZ0hDdTuodn3pE3HRuyPkIX3d ALuyYC2KBQszNxb0HFnVik8F5A== X-Google-Smtp-Source: ABdhPJzzy191PGmD87/Teiyji239CVjb4mjOGOtcjLzQQh2m4VRudIAadvHZQC+uvLNg1xi6n+NDUQ== X-Received: by 2002:a05:6512:1684:b0:448:a0e6:9fa6 with SMTP id bu4-20020a056512168400b00448a0e69fa6mr3309307lfb.592.1652445599514; Fri, 13 May 2022 05:39:59 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h10-20020ac2596a000000b0047255d210fasm367963lfp.41.2022.05.13.05.39.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 May 2022 05:39:59 -0700 (PDT) Message-ID: Date: Fri, 13 May 2022 15:39:58 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH v8 00/10] PCI: qcom: Fix higher MSI vectors handling Content-Language: en-GB To: Johan Hovold Cc: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 13/05/2022 11:58, Johan Hovold wrote: > On Thu, May 12, 2022 at 01:45:35PM +0300, Dmitry Baryshkov wrote: >> I have replied with my Tested-by to the patch at [2], which has landed >> in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: >> Add support for handling MSIs from 8 endpoints"). However lately I >> noticed that during the tests I still had 'pcie_pme=nomsi', so the >> device was not forced to use higher MSI vectors. >> >> After removing this option I noticed that hight MSI vectors are not >> delivered on tested platforms. After additional research I stumbled upon >> a patch in msm-4.14 ([1]), which describes that each group of MSI >> vectors is mapped to the separate interrupt. Implement corresponding >> mapping. >> >> The first patch in the series is a revert of [2] (landed in pci-next). >> Either both patches should be applied or both should be dropped. >> >> Patchseries dependecies: [3] (for the schema change). >> >> Changes since v7: >> - Move code back to the dwc core driver (as required by Rob), >> - Change dt schema to require either a single "msi" interrupt or an >> array of "msi0", "msi1", ... "msi7" IRQs. Disallow specifying a >> part of the array (the DT should specify the exact amount of MSI IRQs >> allowing fallback to a single "msi" IRQ), > > Why this new constraint? > > I've been using your v7 with an sc8280xp which only has four IRQs (and > hence 128 MSIs). > > Looks like this version of the series would not allow that anymore. As a second thought, let's relax parsing needs. > > Johan -- With best wishes Dmitry