From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6EB0C433F5 for ; Fri, 13 May 2022 12:48:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377078AbiEMMsP (ORCPT ); Fri, 13 May 2022 08:48:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347460AbiEMMsO (ORCPT ); Fri, 13 May 2022 08:48:14 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 236163818F for ; Fri, 13 May 2022 05:48:13 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id b18so14305334lfv.9 for ; Fri, 13 May 2022 05:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=Qp6U6LDtAzJAv4pVaRxyFauwAW/SMB8YrlxJPXucXdk=; b=GfxRCdYt4d0NvgjNJJ3/i0YA0koKliMxUUCWYUv88fyDmFhuC3opmOsvihojk5Aufs KCCAoc3rc0BTbFB1r+viroJPZxjsTG35nKFYsSrzI2Iqv8lPmA7SkLNFlg19pACgq/No X58wpmBQGYVA6qRMxRVr538HuJ5ME+eetZvHxS4EdCmJalo7iRBm0yfd2NenM1kmmu0j aPeC1WpN/NecFSM+SImGgeFHLUWbsrVkPq6dNAe+fPXejqZznW2DbM0M2n26MRIUBN/w 5cfonSd9yKaDowhlYUoyJQtQB0xYVRkqDHwXE660Tdd5m6VhmmJVio9/1icWFs8tDhO0 EP1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=Qp6U6LDtAzJAv4pVaRxyFauwAW/SMB8YrlxJPXucXdk=; b=YAuVKT4zdneodwx9hsOljwEzVm6b7Iul7Rl4SzQEeCO8/6IEosbE+SUUCLKkkwpDyA s7CaDlcr4vGOz3hcbQW804zZgmNHTDuxKUUy+4eqmB1ygD49QY8OjoFoNPiDc4tPPfD2 ymNszZ4199xAdyyDATNSBtIdEFaaJcR+zY0s1i0J0/Y1iYYBy8I+6YpAgfwnrW9vCj88 CQCFCM8r9+NCP9vQbcnr4IryGCqbHB2HmcC2yJrqlEeMnYbTHTowjlgaLszS8gCSMXsU jQlvSFzcFGFAouKJB6RboRbtT0XrHzveuZL1fMSxB+5JUFBP7sn5f4HqdwhOLd/JPBBC Brdg== X-Gm-Message-State: AOAM530wNru41UlB5+ZpJQOpnMsaqUbEbU4HiSySYRsjntsgk2JLDa/3 7YlDMhRnBGwTbMvpYcGgviUKzA== X-Google-Smtp-Source: ABdhPJx4lcoptje+cxJATAsXrmMdq66+leY1YvyLqv0s4kCYyV5+Ep2rTJANhSlFa2G1Z/reAPUqLw== X-Received: by 2002:ac2:54a1:0:b0:471:fa39:406d with SMTP id w1-20020ac254a1000000b00471fa39406dmr3410759lfk.640.1652446091461; Fri, 13 May 2022 05:48:11 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id b3-20020ac25e83000000b0047255d210e8sm371273lfq.23.2022.05.13.05.48.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 May 2022 05:48:10 -0700 (PDT) Message-ID: Date: Fri, 13 May 2022 15:48:09 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: Re: [PATCH v8 07/10] PCI: qcom: Handle MSIs routed to multiple GIC interrupts Content-Language: en-GB To: Johan Hovold Cc: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> <20220512104545.2204523-8-dmitry.baryshkov@linaro.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 13/05/2022 15:42, Johan Hovold wrote: > On Thu, May 12, 2022 at 01:45:42PM +0300, Dmitry Baryshkov wrote: >> On some of Qualcomm platforms each group of 32 MSI vectors is routed to the >> separate GIC interrupt. Thus, to receive higher MSI vectors properly, >> declare that the host should use split MSI IRQ handling on these >> platforms. >> >> Signed-off-by: Dmitry Baryshkov >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 2e5464edc36e..f79752d1d680 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -194,6 +194,7 @@ struct qcom_pcie_ops { >> >> struct qcom_pcie_cfg { >> const struct qcom_pcie_ops *ops; >> + unsigned int has_split_msi_irq:1; >> unsigned int pipe_clk_need_muxing:1; >> unsigned int has_tbu_clk:1; >> unsigned int has_ddrss_sf_tbu_clk:1; > >> @@ -1592,6 +1599,11 @@ static int qcom_pcie_probe(struct platform_device *pdev) >> >> pcie->cfg = pcie_cfg; >> >> + if (pcie->cfg->has_split_msi_irq) { >> + pp->num_vectors = MAX_MSI_IRQS; >> + pp->has_split_msi_irq = true; >> + } > > If all qcom platform that can support more than 32 MSI require multiple > IRQs, how about adding num_vectors to the config instead and set > pp->has_split_msi_irq when cfg->num_vectors is set (or unconditionally > if you remove the corresponding warning you just added to the dwc host > code)? > > At least some sc8280xp seem to only support 128 MSI (using 4 IRQs). Nice idea, let's do this. > >> + >> pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); >> if (IS_ERR(pcie->reset)) { >> ret = PTR_ERR(pcie->reset); > > Johan -- With best wishes Dmitry