linux-arm-msm.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Baruch Siach <baruch@tkos.co.il>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Baruch Siach <baruch@tkos.co.il>,
	Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>,
	Kathiravan T <kathirav@codeaurora.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Robert Marko <robert.marko@sartura.hr>,
	devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
	linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-tegra@vger.kernel.org
Subject: [PATCH v2 0/6] arm64: IPQ6018 PCIe support
Date: Wed,  5 May 2021 12:18:28 +0300	[thread overview]
Message-ID: <cover.1620203062.git.baruch@tkos.co.il> (raw)

This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is 
ported from downstream Codeaurora v5.4 kernel. The main difference from 
downstream code is the split of PCIe registers configuration from .init to 
.post_init, since it requires phy_power_on().

Tested on IPQ6010 based hardware.

Changes in v2:

  * Add patch moving GEN3_RELATED macros to a common header

  * Drop ATU configuration from pcie-qcom

  * Remove local definition of common registers

  * Use bulk clk and reset APIs

  * Remove msi-parent from device-tree

Baruch Siach (3):
  PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
  dt-bindings: phy: qcom,qmp: Add IPQ60xx PCIe PHY bindings
  dt-bindings: pci: qcom: Document PCIe bindings for IPQ6018 SoC

Selvam Sathappan Periakaruppan (3):
  PCI: qcom: add support for IPQ60xx PCIe controller
  phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx
  arm64: dts: ipq6018: Add pcie support

 .../devicetree/bindings/pci/qcom,pcie.txt     |  24 +++
 .../devicetree/bindings/phy/qcom,qmp-phy.yaml |  25 +++
 arch/arm64/boot/dts/qcom/ipq6018.dtsi         |  99 ++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h  |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c        | 150 ++++++++++++++++++
 drivers/pci/controller/dwc/pcie-tegra194.c    |   6 -
 drivers/phy/qualcomm/phy-qcom-qmp.c           | 147 +++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h           | 132 +++++++++++++++
 8 files changed, 584 insertions(+), 6 deletions(-)

-- 
2.30.2


             reply	other threads:[~2021-05-05  9:18 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-05  9:18 Baruch Siach [this message]
2021-05-05  9:18 ` [PATCH v2 1/6] PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Baruch Siach
2021-08-06 19:47   ` Rob Herring
2021-05-05  9:18 ` [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller Baruch Siach
2021-08-06 19:59   ` Rob Herring
2021-08-25 11:15     ` Baruch Siach
2021-08-25 13:38       ` Rob Herring
2021-08-25 14:09         ` Baruch Siach
2021-08-25 15:03           ` Rob Herring
2021-08-25 16:05             ` Bjorn Helgaas
2021-08-25 16:37   ` Bjorn Helgaas
2021-05-05  9:18 ` [PATCH v2 3/6] phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx Baruch Siach
2021-05-14 11:43   ` Vinod Koul
2021-05-05  9:18 ` [PATCH v2 4/6] arm64: dts: ipq6018: Add pcie support Baruch Siach
2021-05-05  9:18 ` [PATCH v2 5/6] dt-bindings: phy: qcom,qmp: Add IPQ60xx PCIe PHY bindings Baruch Siach
2021-05-14 11:43   ` Vinod Koul
2021-05-05  9:18 ` [PATCH v2 6/6] dt-bindings: pci: qcom: Document PCIe bindings for IPQ6018 SoC Baruch Siach
2021-05-14 11:43   ` Vinod Koul
2021-08-05  6:58 ` [PATCH v2 0/6] arm64: IPQ6018 PCIe support Baruch Siach
2021-08-05  9:42   ` Lorenzo Pieralisi
2021-08-06 12:48     ` Vinod Koul

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=cover.1620203062.git.baruch@tkos.co.il \
    --to=baruch@tkos.co.il \
    --cc=agross@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=bjorn.andersson@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=gustavo.pimentel@synopsys.com \
    --cc=jingoohan1@gmail.com \
    --cc=jonathanh@nvidia.com \
    --cc=kathirav@codeaurora.org \
    --cc=kishon@ti.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-phy@lists.infradead.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=robert.marko@sartura.hr \
    --cc=robh+dt@kernel.org \
    --cc=speriaka@codeaurora.org \
    --cc=thierry.reding@gmail.com \
    --cc=vkoul@kernel.org \
    --subject='Re: [PATCH v2 0/6] arm64: IPQ6018 PCIe support' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).