Re: [PATCH v2 02/18] arm64: dts: qcom: Add SM6350 device tree

From: Maulik Shah <mkshah@codeaurora.org>
To: Konrad Dybcio <konrad.dybcio@somainline.org>,
	~postmarketos/upstreaming@lists.sr.ht
Cc: martin.botka@somainline.org,
	angelogioacchino.delregno@somainline.org,
	marijn.suijten@somainline.org, jamipkettunen@somainline.org,
	Rob Herring <robh@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Mark Brown <broonie@kernel.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Sebastian Reichel <sre@kernel.org>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Hector Martin <marcan@marcan.st>, Vinod Koul <vkoul@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Kees Cook <keescook@chromium.org>,
	Anton Vorontsov <anton@enomsg.org>,
	Colin Cross <ccross@android.com>, Tony Luck <tony.luck@intel.com>,
	linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH v2 02/18] arm64: dts: qcom: Add SM6350 device tree
Date: Sun, 29 Aug 2021 01:13:48 +0530	[thread overview]
Message-ID: <e483238e-29ac-b1ef-ed80-d5ffdbca83bf@codeaurora.org> (raw)
In-Reply-To: <95c5001a-87dc-2548-97de-538da713b9b6@somainline.org>

Hi,

On 8/28/2021 9:52 PM, Konrad Dybcio wrote:
>>> +
>>> +        tcsr_mutex: hwlock@1f40000 {
>>> +            compatible = "qcom,tcsr-mutex";
>>> +            reg = <0x0 0x01f40000 0x0 0x40000>;
>>> +            #hwlock-cells = <1>;
>>> +        };
>>> +
>>> +        pdc: interrupt-controller@b220000 {
>>> +            compatible = "qcom,sm6350-pdc", "qcom,pdc";
>>> +            reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
>> The second reg  0x17c000f0 is neither documented nor used in PDC irq chip driver. can you please remove it?
>>
>> Thanks,
>> Maulik
>>
> Wouldn't it make more sense to keep it (like in other PDC-enabled SoCs' device trees) so that there's no
>
> need to add it back when the driver gains support for spi_configure_type (I believe that's what it's used for)?
The second reg in some of the PDC enabled SoCs' went in since it may 
have slipped throgh code reviews when using downstream
patch as is on upstream.
Also the bindings document for PDC is still in txt, so yaml check could 
not catch the extra register which is not documented.

An attempt to add support for spi_configure_type [1] & [2] had 
suggestion either to access second reg via mailbox or
add another level of irqchip hierarchy between PDC to GIC to configure 
SPI type. Unless both [1] and [2] patch can go in as
PDC irqchip driver won't gain support to use it. (using mailbox approch 
will have mailbox driver to access this register and PDC node may 
mention which mailbox to use).

[1] 
https://patchwork.kernel.org/project/linux-arm-msm/patch/1568411962-1022-7-git-send-email-ilina@codeaurora.org/

[2] 
https://patchwork.kernel.org/project/linux-arm-msm/patch/1568411962-1022-8-git-send-email-ilina@codeaurora.org/

Thanks,
Maulik

>
>
> Konrad
>
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