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From: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
To: Baruch Siach <baruch@tkos.co.il>, Felipe Balbi <balbi@kernel.org>
Cc: "linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	"linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
	Kathiravan T <kathirav@codeaurora.org>,
	Balaji Prakash J <bjagadee@codeaurora.org>
Subject: Re: [PATCH] usb: dwc3: reference clock configuration
Date: Wed, 31 Mar 2021 01:17:20 +0000	[thread overview]
Message-ID: <f3042097-8569-5882-06db-ae56e05cac59@synopsys.com> (raw)
In-Reply-To: <8fc38cb73afd31269f1ea0c28e73604c53cebb17.1612764006.git.baruch@tkos.co.il>

Baruch Siach wrote:
> From: Balaji Prakash J <bjagadee@codeaurora.org>
> 
> DWC_USB3_GFLADJ and DWC_USB3_GUCTL registers contain options
> to control the behavior of controller with respect to SOF and ITP.
> The reset values of these registers are aligned for 19.2 MHz
> reference clock source. This change will add option to override
> these settings for reference clock other than 19.2 MHz
> 
> Tested on IPQ6018 SoC based CP01 board with 24MHz reference clock.
> 
> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
> [ baruch: mention tested hardware ]
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
>  .../devicetree/bindings/usb/dwc3.txt          |  5 ++
>  drivers/usb/dwc3/core.c                       | 52 +++++++++++++++++++
>  drivers/usb/dwc3/core.h                       | 12 +++++
>  3 files changed, 69 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 1aae2b6160c1..4ffa87b697dc 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -89,6 +89,11 @@ Optional properties:
>   - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
>  	register for post-silicon frame length adjustment when the
>  	fladj_30mhz_sdbnd signal is invalid or incorrect.
> + - snps,quirk-ref-clock-adjustment: Value for GFLADJ_REFCLK_* fields of GFLADJ
> +	register for reference clock other than 19.2 MHz is used.
> + - snps,quirk-ref-clock-period: Value for REFCLKPER filed of GUCTL. This field
> +	indicates in terms of nano seconds the period of ref_clk. To calculate the
> +	ideal value, REFCLKPER = (1/ref_clk in Hz)*10^9.

Why is this a quirk? It's not a quirk. The user can inform the ref_clk
period to the controller here.

The default value from GUCTL.REFCLKPER is a value from coreConsultant
setting. The designer knows what period it should be and should properly
set it if the default is not correctly set.

BR,
Thinh

  parent reply	other threads:[~2021-03-31  1:18 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-08  6:00 [PATCH] usb: dwc3: reference clock configuration Baruch Siach
2021-02-08  6:56 ` Greg KH
2021-02-08 18:26 ` Bjorn Andersson
2021-02-10  6:10   ` Baruch Siach
2021-02-15 16:58     ` Kathiravan T
2021-02-25 16:47       ` Kathiravan T
2021-03-24  8:14         ` Jack Pham
2021-03-31  0:52           ` Thinh Nguyen
2021-03-31  1:17 ` Thinh Nguyen [this message]
2021-04-07 11:56   ` Kathiravan T
2021-04-08  1:53     ` Thinh Nguyen
2021-04-08  2:23       ` Bjorn Andersson
2021-04-08  2:50         ` Thinh Nguyen
2021-04-08  2:54           ` Thinh Nguyen
2021-04-08  3:15           ` Bjorn Andersson
2021-04-08  3:39             ` Thinh Nguyen

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