From: Marc Gonzalez <marc.w.gonzalez@free.fr>
To: Joerg Roedel <joro@8bytes.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>,
Robin Murphy <robin.murphy@arm.com>,
MSM <linux-arm-msm@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
iommu <iommu@lists.linux-foundation.org>,
AngeloGioacchino Del Regno <kholk11@gmail.com>,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
Andy Gross <agross@kernel.org>
Subject: Re: [PATCH v3] iommu/arm-smmu: Avoid constant zero in TLBI writes
Date: Fri, 7 Jun 2019 12:40:05 +0200 [thread overview]
Message-ID: <f7b2e799-e3b1-ad40-c7b7-153f00323636@free.fr> (raw)
In-Reply-To: <20190605121900.GJ15030@fuggles.cambridge.arm.com>
On 05/06/2019 14:19, Will Deacon wrote:
> On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote:
>
>> From: Robin Murphy <robin.murphy@arm.com>
>>
>> Apparently, some Qualcomm arm64 platforms which appear to expose their
>> SMMU global register space are still, in fact, using a hypervisor to
>> mediate it by trapping and emulating register accesses. Sadly, some
>> deployed versions of said trapping code have bugs wherein they go
>> horribly wrong for stores using r31 (i.e. XZR/WZR) as the source
>> register.
>>
>> While this can be mitigated for GCC today by tweaking the constraints
>> for the implementation of writel_relaxed(), to avoid any potential
>> arms race with future compilers more aggressively optimising register
>> allocation, the simple way is to just remove all the problematic
>> constant zeros. For the write-only TLB operations, the actual value is
>> irrelevant anyway and any old nearby variable will provide a suitable
>> GPR to encode. The one point at which we really do need a zero to clear
>> a context bank happens before any of the TLB maintenance where crashes
>> have been reported, so is apparently not a problem... :/
>>
>> Reported-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
>> Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
>
> Acked-by: Will Deacon <will.deacon@arm.com>
>
> Joerg -- Please can you take this as a fix for 5.2, with a Cc stable?
Hello Joerg,
Can you ping this thread once this patch hits linux-next, so I can
ask Bjorn to pick up the 8998 ANOC1 DT node, and the PCIe DT node
that requires ANOC1.
Bjorn: for ANOC1, a small fixup: s/arm,smmu/iommu/
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=99701
https://patchwork.kernel.org/patch/10895341/
Regards.
next prev parent reply other threads:[~2019-06-07 10:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-29 11:55 [PATCH v2] iommu/arm-smmu: Avoid constant zero in TLBI writes Marc Gonzalez
2019-05-29 13:05 ` Will Deacon
2019-05-29 14:31 ` Marc Gonzalez
2019-06-03 12:15 ` [PATCH v3] " Marc Gonzalez
2019-06-05 12:19 ` Will Deacon
2019-06-07 10:40 ` Marc Gonzalez [this message]
2019-06-12 8:10 ` Joerg Roedel
2019-06-14 11:24 ` Marc Gonzalez
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