From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52CD8C07E96 for ; Tue, 6 Jul 2021 17:15:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3301561C5A for ; Tue, 6 Jul 2021 17:15:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230363AbhGFRSg (ORCPT ); Tue, 6 Jul 2021 13:18:36 -0400 Received: from mail-0201.mail-europe.com ([51.77.79.158]:43527 "EHLO mail-0201.mail-europe.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230141AbhGFRSg (ORCPT ); Tue, 6 Jul 2021 13:18:36 -0400 Date: Tue, 06 Jul 2021 17:15:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail; t=1625591754; bh=Zw8oSZeKBxE+Yt+Ye7A3hOc+/l3wSELM0EmZrDF28FU=; h=Date:To:From:Cc:Reply-To:Subject:In-Reply-To:References:From; b=GyGapLyvMm0Pr7fMurOz3iWAouPw517PnDdbDK42xjVLvBTebz0iFpyGfmZjpMnjK vFs3D3VMMEMDE+Wo2ZfFCcIrx2pebPDZEtiBEmr5H+WUw05jMLEaJSBKO+612rcugc LQO0S9O98SCP66AYMtIrgmu5QfyLRwE/gntRl8Kw= To: Arnd Bergmann From: Yassine Oudjana Cc: Marc Zyngier , Will Deacon , Robin Murphy , Catalin Marinas , Ard Biesheuvel , Android Kernel Team , Linux ARM , Mark Rutland , Vincent Whitchurch , linux-arm-msm Reply-To: Yassine Oudjana Subject: Re: [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) Message-ID: In-Reply-To: References: <20210527124356.22367-1-will@kernel.org> <20210706102634.GB24903@arm.com> <59800d6c-364a-f4be-e341-c5b531657ba3@arm.com> <20210706133314.GB20327@willie-the-truck> <87zguz7b6b.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tuesday, July 6th, 2021 at 7:43 PM, Arnd Bergmann wrote: > On Tue, Jul 6, 2021 at 4:46 PM Marc Zyngier maz@kernel.org wrote: > > On Tue, 06 Jul 2021 15:30:34 +0100, Arnd Bergmann arnd@arndb.de wrote: > > > I can only speculate on how much got reused between the two, but > > > as Falkor was released only after they had already given up on > > > the full-custom Kryo core, it's plausible that it incorporates bits f= rom > > > that one. In particular the cache controller is probably easy to reus= e > > > even if the rest of it was a new design. > > > > I guess we'll never find out, and I'm probably one of the few still > > having some access to this HW (not even sure for how long anyway). > > > > I won't cry if we decide to pull the plug on it. > > Sure, but the Snapdragon 820E is one we do need to worry about. > While the internet pretty much agrees on Falkor having 128 bytes > L1 cache line, it might be good to rule out that Kryo just misreports > it before we revert the patch. > > Yassine, could you run the 'line' and 'cache' helper from lmbench > to determine what the cache topology appears to be and if that > matches the CTR_EL0 contents? > > Something like > > numactl -C 0 line -M 1M > numactl -C 3 line -M 1M > numactl -C 0 cache > numactl -C 3 cache > > (the numactl command helps run this both on the 'big' and 'little' > cores without running into migration) > > Arnd Here are the results: $ numactl -C 0 line -M 1M 128 $ numactl -C 3 line -M 1M 128 $ numactl -C 0 cache L1 cache: 512 bytes 1.37 nanoseconds 64 linesize -1.00 parallelism L2 cache: 24576 bytes 2.75 nanoseconds 64 linesize 5.06 parallelism L3 cache: 131072 bytes 7.89 nanoseconds 64 linesize 3.85 parallelism L4 cache: 524288 bytes 15.86 nanoseconds 128 linesize 3.48 parallelism Memory latency: 145.93 nanoseconds 4.88 parallelism $ numactl -C 3 cache L1 cache: 24576 bytes 1.29 nanoseconds 64 linesize 5.00 parallelism L2 cache: 1048576 bytes 8.60 nanoseconds 128 linesize 3.07 parallelism Memory latency: 143.29 nanoseconds 5.37 parallelism