From: Eric Biggers <ebiggers@kernel.org>
To: linux-scsi@vger.kernel.org, linux-arm-msm@vger.kernel.org
Cc: linux-block@vger.kernel.org, linux-fscrypt@vger.kernel.org,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Avri Altman <avri.altman@wdc.com>,
Pedro Sousa <pedrom.sousa@synopsys.com>,
John Stultz <john.stultz@linaro.org>,
Barani Muthukumaran <bmuthuku@qti.qualcomm.com>,
Can Guo <cang@codeaurora.org>,
Satya Tangirala <satyat@google.com>,
Jaegeuk Kim <jaegeuk@kernel.org>,
"Theodore Y . Ts'o" <tytso@mit.edu>
Subject: [RFC PATCH 2/5] arm64: dts: sdm845: add Inline Crypto Engine registers and clock
Date: Thu, 9 Jan 2020 22:16:31 -0800 [thread overview]
Message-ID: <20200110061634.46742-3-ebiggers@kernel.org> (raw)
In-Reply-To: <20200110061634.46742-1-ebiggers@kernel.org>
From: Eric Biggers <ebiggers@google.com>
Add the vendor-specific registers and clock for Qualcomm ICE (Inline
Crypto Engine) to the device tree node for the UFS host controller on
sdm845, so that the ufs-qcom driver will be able to use inline crypto.
Use a separate register range rather than extending the main UFS range
because there's a gap between the two, and the ICE registers are
vendor-specific. (Actually, the hardware claims that the ICE range also
includes the array of standard crypto configuration registers; however,
on this SoC the Linux kernel isn't permitted to access them directly.)
Signed-off-by: Eric Biggers <ebiggers@google.com>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index ddb1f23c936fe..0fecc0791959e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1367,7 +1367,9 @@ cache-controller@1100000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x2500>;
+ reg = <0 0x01d84000 0 0x2500>,
+ <0 0 0 0>,
+ <0 0x01d90000 0 0x8000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
@@ -1385,7 +1387,8 @@ ufs_mem_hc: ufshc@1d84000 {
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
+ "rx_lane1_sync_clk",
+ "ice_core_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -1394,7 +1397,8 @@ ufs_mem_hc: ufshc@1d84000 {
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
@@ -1403,7 +1407,8 @@ ufs_mem_hc: ufshc@1d84000 {
<0 0>,
<0 0>,
<0 0>,
- <0 0>;
+ <0 0>,
+ <0 300000000>;
status = "disabled";
};
--
2.24.1
next prev parent reply other threads:[~2020-01-10 6:18 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-10 6:16 [RFC PATCH 0/5] Inline crypto support on DragonBoard 845c Eric Biggers
2020-01-10 6:16 ` [RFC PATCH 1/5] firmware: qcom_scm: Add support for programming inline crypto keys Eric Biggers
2020-01-10 6:16 ` Eric Biggers [this message]
2020-01-10 6:16 ` [RFC PATCH 3/5] scsi: ufs: add quirk to disable inline crypto support Eric Biggers
2020-01-10 6:16 ` [RFC PATCH 4/5] scsi: ufs: add program_key() variant op Eric Biggers
2020-01-10 6:16 ` [RFC PATCH 5/5] scsi: ufs-qcom: add Inline Crypto Engine support Eric Biggers
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