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[79.139.233.37]) by smtp.googlemail.com with ESMTPSA id 14sm6888501ljj.32.2020.02.24.17.35.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Feb 2020 17:35:23 -0800 (PST) Subject: Re: [PATCH v1 3/3] partitions: Introduce NVIDIA Tegra Partition Table To: Stephen Warren Cc: Jens Axboe , Thierry Reding , Jonathan Hunter , =?UTF-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= , David Heidelberg , Peter Geis , Nicolas Chauvet , Ulf Hansson , Adrian Hunter , Billy Laws , linux-tegra@vger.kernel.org, linux-block@vger.kernel.org, Andrey Danin , Gilles Grandou , Ryan Grachek , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200224231841.26550-1-digetx@gmail.com> <20200224231841.26550-4-digetx@gmail.com> <44c22925-a14e-96d0-1f93-1979c0c60525@wwwdotorg.org> From: Dmitry Osipenko Message-ID: <69a76bbe-e088-6715-fefe-354dd4bc3ef2@gmail.com> Date: Tue, 25 Feb 2020 04:35:21 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <44c22925-a14e-96d0-1f93-1979c0c60525@wwwdotorg.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-block-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-block@vger.kernel.org 25.02.2020 03:20, Stephen Warren пишет: > On 2/24/20 4:18 PM, Dmitry Osipenko wrote: >> All NVIDIA Tegra devices use a special partition table format for the >> internal storage partitioning. Most of Tegra devices have GPT partition >> in addition to TegraPT, but some older Android consumer-grade devices do >> not or GPT is placed in a wrong sector, and thus, the TegraPT is needed >> in order to support these devices properly in the upstream kernel. This >> patch adds support for NVIDIA Tegra Partition Table format that is used >> at least by all NVIDIA Tegra20 and Tegra30 devices. > >> diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c > >> +static void __init tegra_boot_config_table_init(void) >> +{ >> +    void __iomem *bct_base; >> +    u16 pt_addr, pt_size; >> + >> +    bct_base = IO_ADDRESS(TEGRA_IRAM_BASE) + TEGRA_IRAM_BCT_OFFSET; > > This shouldn't be hard-coded. IIRC, the boot ROM writes a BIT (Boot > Information Table) to a fixed location in IRAM, and there's some value > in the BIT that points to where the BCT is in IRAM. In practice, it > might work out that the BCT is always at the same place in IRAM, but > this certainly isn't guaranteed. I think there's code in U-Boot which > extracts the BCT location from the BIT? Yes, see > arch/arm/mach-tegra/ap.c:get_odmdata(). Thank you very much, I didn't know about that. I checked whether Nexus 7 and A500 have a correct pointer in the BIT and they have it. I'll take it into account in v2, thank you again.