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bh=AWWuA/JtQHEoXMKz+XE4VOt7xAtoTKB5e9hojkHO6LI=; b=a/Z7ztQa4yTifCao6VY4J3vAgOie6AhM0rZxjpahZn4PkbQv2U135QwogFXPmpTLFt N28UgF2hJJiVJRfWlG0CSnFfp8BoIFwRPMDkIIeRc0dOPnhfOX/pw+e6ZWpMrGwvroUO DGOksWsi/KV/AQZZkwL3zOCsca+fuggEaKjVNewJOlt/kj3vYCBqq7FGHvs367+/PCDI 8CcNTgwNiU5Up1AvKAId868oJHEWVrwSltc5Y6Zh4gaGH57MRALbZMp4U5kHx7o/QAe0 0e7vg7lBLQPqX10guKbFFw6WC0SryjSWeQv9AmCy2AmUOrVdmsOqHh4YHdBQM9ysfaM2 +0yw== X-Gm-Message-State: APjAAAXzVTL2Vt1c0jlKsSnut1BT8AYDvblnMI3B/pNOXbt7exelBd3/ eqIymFrwy4etFOkziL7ZOtPxY2aQzC/LP7Zek4I0 X-Google-Smtp-Source: APXvYqy6CDJOP3TkhKIRwK/Jy2ldyzs9AHrBBFwOO86437RdJVO4H7Wh9eWo6BybO5H9SQagTXh6cIAk34GC+ElLzQ0= X-Received: by 2002:a05:600c:228f:: with SMTP id 15mr39537254wmf.60.1563454144157; Thu, 18 Jul 2019 05:49:04 -0700 (PDT) MIME-Version: 1.0 References: <20190718020745.8867-1-fred@fredlawl.com> <20190718020745.8867-6-fred@fredlawl.com> In-Reply-To: <20190718020745.8867-6-fred@fredlawl.com> From: Bjorn Helgaas Date: Thu, 18 Jul 2019 07:48:51 -0500 Message-ID: Subject: Re: [PATCH] mtip32xx: Prefer pcie_capability_read_word() To: Frederick Lawler Cc: Jens Axboe , linux-block@vger.kernel.org, Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-block-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-block@vger.kernel.org On Wed, Jul 17, 2019 at 9:09 PM Frederick Lawler wrote: > > Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability") > added accessors for the PCI Express Capability so that drivers didn't > need to be aware of differences between v1 and v2 of the PCI > Express Capability. > > Replace pci_read_config_word() and pci_write_config_word() calls with > pcie_capability_read_word() and pcie_capability_write_word(). > > Signed-off-by: Frederick Lawler > --- > drivers/block/mtip32xx/mtip32xx.c | 28 ++++++++++++---------------- > 1 file changed, 12 insertions(+), 16 deletions(-) > > diff --git a/drivers/block/mtip32xx/mtip32xx.c b/drivers/block/mtip32xx/mtip32xx.c > index f0105d118056..b7b26e33248b 100644 > --- a/drivers/block/mtip32xx/mtip32xx.c > +++ b/drivers/block/mtip32xx/mtip32xx.c > @@ -3952,22 +3952,18 @@ static void mtip_disable_link_opts(struct driver_data *dd, struct pci_dev *pdev) > int pos; > unsigned short pcie_dev_ctrl; > > - pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); > - if (pos) { > - pci_read_config_word(pdev, > - pos + PCI_EXP_DEVCTL, > - &pcie_dev_ctrl); > - if (pcie_dev_ctrl & (1 << 11) || > - pcie_dev_ctrl & (1 << 4)) { > - dev_info(&dd->pdev->dev, > - "Disabling ERO/No-Snoop on bridge device %04x:%04x\n", > - pdev->vendor, pdev->device); > - pcie_dev_ctrl &= ~(PCI_EXP_DEVCTL_NOSNOOP_EN | > - PCI_EXP_DEVCTL_RELAX_EN); > - pci_write_config_word(pdev, > - pos + PCI_EXP_DEVCTL, > - pcie_dev_ctrl); > - } > + if (!pci_is_pcie(pdev)) > + return; > + > + pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &pcie_dev_ctrl); > + if (pcie_dev_ctrl & (1 << 11) || > + pcie_dev_ctrl & (1 << 4)) { Hmm, sort of sloppy that d1e714db8129 ("mtip32xx: Fix ERO and NoSnoop values in PCIe upstream on AMD systems") used PCI_EXP_DEVCTL_NOSNOOP_EN and PCI_EXP_DEVCTL_RELAX_EN below, but not here. Could be fixed with a separate follow-on patch. > + dev_info(&dd->pdev->dev, > + "Disabling ERO/No-Snoop on bridge device %04x:%04x\n", > + pdev->vendor, pdev->device); > + pcie_dev_ctrl &= ~(PCI_EXP_DEVCTL_NOSNOOP_EN | > + PCI_EXP_DEVCTL_RELAX_EN); > + pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, pcie_dev_ctrl); > } > } > > -- > 2.17.1 >