From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.2 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBC0BC433B4 for ; Tue, 6 Apr 2021 14:04:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 927416139C for ; Tue, 6 Apr 2021 14:04:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235371AbhDFOEq (ORCPT ); Tue, 6 Apr 2021 10:04:46 -0400 Received: from mx2.suse.de ([195.135.220.15]:34498 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232842AbhDFOEp (ORCPT ); Tue, 6 Apr 2021 10:04:45 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 28C2CB167; Tue, 6 Apr 2021 14:04:35 +0000 (UTC) Subject: Re: [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support From: Matthias Brugger To: Macpaul Lin , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , mtk01761 , Fabien Parent , Weiyi Lu , Mars Cheng , Sean Wang , Owen Chen , Chunfeng Yun , Evan Green , Yong Wu , Joerg Roedel , Shawn Guo , Marc Zyngier , Ryder Lee , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org Cc: Mediatek WSD Upstream , CC Hwang , Loda Chou References: <1582279929-11535-1-git-send-email-macpaul.lin@mediatek.com> <1582279929-11535-3-git-send-email-macpaul.lin@mediatek.com> Message-ID: <116b6067-fc75-b0cd-2da0-900cfdcacb02@gmail.com> Date: Tue, 6 Apr 2021 16:04:32 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 06/04/2021 16:01, Matthias Brugger wrote: > > > On 21/02/2020 11:12, Macpaul Lin wrote: >> From: Mars Cheng >> >> This adds scpsys support for MT6765 >> Add subdomain support for MT6765: >> isp, mm, connsys, mfg, and cam. >> >> Signed-off-by: Mars Cheng >> Signed-off-by: Owen Chen >> Signed-off-by: Macpaul Lin >> --- >> drivers/soc/mediatek/mtk-scpsys.c | 130 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 130 insertions(+) >> > > Unfortunately scpsys is deprecated in the meantime. Please port you patches to > the new mtk-pm-domains.c driver. The biggest difference is, that the domain and > subdomain structure of the pm domains is describe in device tree instead of > hard-coded in the driver. > I got confused by the email grouping in my mail client. I already gave the same feedback in v10 :) > Regards, > Matthias > >> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c >> index f669d37..9940c6d 100644 >> --- a/drivers/soc/mediatek/mtk-scpsys.c >> +++ b/drivers/soc/mediatek/mtk-scpsys.c >> @@ -15,6 +15,7 @@ >> >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -750,6 +751,120 @@ static void mtk_register_power_domains(struct platform_device *pdev, >> }; >> >> /* >> + * MT6765 power domain support >> + */ >> +#define SPM_PWR_STATUS_MT6765 0x0180 >> +#define SPM_PWR_STATUS_2ND_MT6765 0x0184 >> + >> +static const struct scp_domain_data scp_domain_data_mt6765[] = { >> + [MT6765_POWER_DOMAIN_VCODEC] = { >> + .name = "vcodec", >> + .sta_mask = BIT(26), >> + .ctl_offs = 0x300, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + }, >> + [MT6765_POWER_DOMAIN_ISP] = { >> + .name = "isp", >> + .sta_mask = BIT(5), >> + .ctl_offs = 0x308, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + .subsys_clk_prefix = "isp", >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(20), BIT(20)), >> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, >> + BIT(2), BIT(2)), >> + }, >> + }, >> + [MT6765_POWER_DOMAIN_MM] = { >> + .name = "mm", >> + .sta_mask = BIT(3), >> + .ctl_offs = 0x30C, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + .basic_clk_id = {"mm"}, >> + .subsys_clk_prefix = "mm", >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(16) | BIT(17), BIT(16) | BIT(17)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(10) | BIT(11), BIT(10) | BIT(11)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(1) | BIT(2), BIT(1) | BIT(2)), >> + }, >> + }, >> + [MT6765_POWER_DOMAIN_CONN] = { >> + .name = "conn", >> + .sta_mask = BIT(1), >> + .ctl_offs = 0x32C, >> + .sram_pdn_bits = 0, >> + .sram_pdn_ack_bits = 0, >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(13), BIT(13)), >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(18), BIT(18)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(14) | BIT(16), BIT(14) | BIT(16)), >> + }, >> + }, >> + [MT6765_POWER_DOMAIN_MFG_ASYNC] = { >> + .name = "mfg_async", >> + .sta_mask = BIT(23), >> + .ctl_offs = 0x334, >> + .sram_pdn_bits = 0, >> + .sram_pdn_ack_bits = 0, >> + .basic_clk_id = {"mfg"}, >> + }, >> + [MT6765_POWER_DOMAIN_MFG] = { >> + .name = "mfg", >> + .sta_mask = BIT(4), >> + .ctl_offs = 0x338, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(25), BIT(25)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(21) | BIT(22), BIT(21) | BIT(22)), >> + } >> + }, >> + [MT6765_POWER_DOMAIN_CAM] = { >> + .name = "cam", >> + .sta_mask = BIT(25), >> + .ctl_offs = 0x344, >> + .sram_pdn_bits = GENMASK(8, 9), >> + .sram_pdn_ack_bits = GENMASK(12, 13), >> + .subsys_clk_prefix = "cam", >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(19) | BIT(21), BIT(19) | BIT(21)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(20), BIT(20)), >> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, >> + BIT(3), BIT(3)), >> + } >> + }, >> + [MT6765_POWER_DOMAIN_MFG_CORE0] = { >> + .name = "mfg_core0", >> + .sta_mask = BIT(7), >> + .ctl_offs = 0x34C, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + }, >> +}; >> + >> +static const struct scp_subdomain scp_subdomain_mt6765[] = { >> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM}, >> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP}, >> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC}, >> + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG}, >> + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0}, >> +}; >> + >> +/* >> * MT6797 power domain support >> */ >> >> @@ -1032,6 +1147,18 @@ static void mtk_register_power_domains(struct platform_device *pdev, >> .bus_prot_reg_update = false, >> }; >> >> +static const struct scp_soc_data mt6765_data = { >> + .domains = scp_domain_data_mt6765, >> + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765), >> + .subdomains = scp_subdomain_mt6765, >> + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765), >> + .regs = { >> + .pwr_sta_offs = SPM_PWR_STATUS_MT6765, >> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765, >> + }, >> + .bus_prot_reg_update = true, >> +}; >> + >> static const struct scp_soc_data mt6797_data = { >> .domains = scp_domain_data_mt6797, >> .num_domains = ARRAY_SIZE(scp_domain_data_mt6797), >> @@ -1088,6 +1215,9 @@ static void mtk_register_power_domains(struct platform_device *pdev, >> .compatible = "mediatek,mt2712-scpsys", >> .data = &mt2712_data, >> }, { >> + .compatible = "mediatek,mt6765-scpsys", >> + .data = &mt6765_data, >> + }, { >> .compatible = "mediatek,mt6797-scpsys", >> .data = &mt6797_data, >> }, { >>