[PATCH v2 0/7] Add Amlogic meson8b clock gates

[PATCH v2 0/7] Add Amlogic meson8b clock gates

[Alexander Müller]

This patch series adds support for the Amlogic meson8b clock gates. The Amlogic
U-Boot disables most of them at boot. In order to enable ethernet, USB and other
components it's mandatory to enable the clock gates when loading the corresponding
drivers.

The meson8b clock gate support is based on the previous work done for Amlogic gxbb
currently available in clk-next.

Changes since v1:
  - Fixed GXBB spelling
  - Moved newly introduced CLKID defines to private header
  - Moved CLK_NR_CLKS define from DT binding to private header
  - Rebased to linux-amlogic/v4.7/integ making Kconfig select obsolete

Alexander Müller (7):
  clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention
  meson: clk: Move register definitions to meson8b.h
  meson: clk: Rename register names according to Amlogic datasheet
  clk: meson: Copy meson8b CLKID defines to private header file
  meson: clk: Add CLKIDs for clock gates
  gxbb: clk: Move MESON_GATE macro to gxbb
  meson: clk: Add support for clock gates

 drivers/clk/meson/Makefile               |   2 +-
 drivers/clk/meson/clkc.h                 |  14 -
 drivers/clk/meson/gxbb.c                 | 176 ++++----
 drivers/clk/meson/meson8b-clkc.c         | 458 --------------------
 drivers/clk/meson/meson8b.c              | 705 +++++++++++++++++++++++++++++++
 drivers/clk/meson/meson8b.h              | 148 +++++++
 include/dt-bindings/clock/meson8b-clkc.h |   2 -
 7 files changed, 949 insertions(+), 556 deletions(-)
 delete mode 100644 drivers/clk/meson/meson8b-clkc.c
 create mode 100644 drivers/clk/meson/meson8b.c
 create mode 100644 drivers/clk/meson/meson8b.h

-- 
2.5.0

[PATCH v2 1/7] clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention

[Alexander Müller]

Signed-off-by: Alexander Müller <serveralex@gmail.com>
---
 drivers/clk/meson/Makefile                      | 2 +-
 drivers/clk/meson/{meson8b-clkc.c => meson8b.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename drivers/clk/meson/{meson8b-clkc.c => meson8b.c} (100%)

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 197e401..1a66799 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,5 +3,5 @@
 #
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
-obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o
+obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o
diff --git a/drivers/clk/meson/meson8b-clkc.c b/drivers/clk/meson/meson8b.c
similarity index 100%
rename from drivers/clk/meson/meson8b-clkc.c
rename to drivers/clk/meson/meson8b.c
-- 
2.5.0

[PATCH v2 2/7] meson: clk: Move register definitions to meson8b.h

[Alexander Müller]

Signed-off-by: Alexander Müller <serveralex@gmail.com>
---
 drivers/clk/meson/meson8b.c | 17 +----------------
 drivers/clk/meson/meson8b.h | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 16 deletions(-)
 create mode 100644 drivers/clk/meson/meson8b.h

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index b1902e9..537cc53 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -26,22 +26,7 @@
 #include <linux/module.h>
 
 #include "clkc.h"
-
-/*
- * Clock controller register offsets
- *
- * Register offsets from the HardKernel[0] data sheet are listed in comment
- * blocks below. Those offsets must be multiplied by 4 before adding them to
- * the base address to get the right value
- *
- * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
- */
-#define MESON8B_REG_SYS_CPU_CNTL1	0x015c /* 0x57 offset in data sheet */
-#define MESON8B_REG_HHI_MPEG		0x0174 /* 0x5d offset in data sheet */
-#define MESON8B_REG_MALI		0x01b0 /* 0x6c offset in data sheet */
-#define MESON8B_REG_PLL_FIXED		0x0280
-#define MESON8B_REG_PLL_SYS		0x0300
-#define MESON8B_REG_PLL_VID		0x0320
+#include "meson8b.h"
 
 static DEFINE_SPINLOCK(clk_lock);
 
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
new file mode 100644
index 0000000..5b9cb9f
--- /dev/null
+++ b/drivers/clk/meson/meson8b.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Michael Turquette <mturquette@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MESON8B_H
+#define __MESON8B_H
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the HardKernel[0] data sheet are listed in comment
+ * blocks below. Those offsets must be multiplied by 4 before adding them to
+ * the base address to get the right value
+ *
+ * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
+ */
+#define MESON8B_REG_SYS_CPU_CNTL1	0x015c /* 0x57 offset in data sheet */
+#define MESON8B_REG_HHI_MPEG		0x0174 /* 0x5d offset in data sheet */
+#define MESON8B_REG_MALI		0x01b0 /* 0x6c offset in data sheet */
+#define MESON8B_REG_PLL_FIXED		0x0280
+#define MESON8B_REG_PLL_SYS		0x0300
+#define MESON8B_REG_PLL_VID		0x0320
+
+#endif /* __MESON8B_H */
-- 
2.5.0

[PATCH v2 3/7] meson: clk: Rename register names according to Amlogic datasheet

[Alexander Müller]

Signed-off-by: Alexander Müller <serveralex@gmail.com>
---
 drivers/clk/meson/meson8b.c | 26 +++++++++++++-------------
 drivers/clk/meson/meson8b.h | 11 +++++------
 2 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 537cc53..0c6e26f 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -111,17 +111,17 @@ static struct clk_fixed_rate meson8b_xtal = {
 
 static struct meson_clk_pll meson8b_fixed_pll = {
 	.m = {
-		.reg_off = MESON8B_REG_PLL_FIXED,
+		.reg_off = HHI_MPLL_CNTL,
 		.shift   = 0,
 		.width   = 9,
 	},
 	.n = {
-		.reg_off = MESON8B_REG_PLL_FIXED,
+		.reg_off = HHI_MPLL_CNTL,
 		.shift   = 9,
 		.width   = 5,
 	},
 	.od = {
-		.reg_off = MESON8B_REG_PLL_FIXED,
+		.reg_off = HHI_MPLL_CNTL,
 		.shift   = 16,
 		.width   = 2,
 	},
@@ -137,17 +137,17 @@ static struct meson_clk_pll meson8b_fixed_pll = {
 
 static struct meson_clk_pll meson8b_vid_pll = {
 	.m = {
-		.reg_off = MESON8B_REG_PLL_VID,
+		.reg_off = HHI_VID_PLL_CNTL,
 		.shift   = 0,
 		.width   = 9,
 	},
 	.n = {
-		.reg_off = MESON8B_REG_PLL_VID,
+		.reg_off = HHI_VID_PLL_CNTL,
 		.shift   = 9,
 		.width   = 5,
 	},
 	.od = {
-		.reg_off = MESON8B_REG_PLL_VID,
+		.reg_off = HHI_VID_PLL_CNTL,
 		.shift   = 16,
 		.width   = 2,
 	},
@@ -163,17 +163,17 @@ static struct meson_clk_pll meson8b_vid_pll = {
 
 static struct meson_clk_pll meson8b_sys_pll = {
 	.m = {
-		.reg_off = MESON8B_REG_PLL_SYS,
+		.reg_off = HHI_SYS_PLL_CNTL,
 		.shift   = 0,
 		.width   = 9,
 	},
 	.n = {
-		.reg_off = MESON8B_REG_PLL_SYS,
+		.reg_off = HHI_SYS_PLL_CNTL,
 		.shift   = 9,
 		.width   = 5,
 	},
 	.od = {
-		.reg_off = MESON8B_REG_PLL_SYS,
+		.reg_off = HHI_SYS_PLL_CNTL,
 		.shift   = 16,
 		.width   = 2,
 	},
@@ -250,7 +250,7 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
  * forthcoming coordinated clock rates feature
  */
 static struct meson_clk_cpu meson8b_cpu_clk = {
-	.reg_off = MESON8B_REG_SYS_CPU_CNTL1,
+	.reg_off = HHI_SYS_CPU_CLK_CNTL1,
 	.div_table = cpu_div_table,
 	.clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
 	.hw.init = &(struct clk_init_data){
@@ -264,7 +264,7 @@ static struct meson_clk_cpu meson8b_cpu_clk = {
 static u32 mux_table_clk81[]	= { 6, 5, 7 };
 
 struct clk_mux meson8b_mpeg_clk_sel = {
-	.reg = (void *)MESON8B_REG_HHI_MPEG,
+	.reg = (void *)HHI_MPEG_CLK_CNTL,
 	.mask = 0x7,
 	.shift = 12,
 	.flags = CLK_MUX_READ_ONLY,
@@ -286,7 +286,7 @@ struct clk_mux meson8b_mpeg_clk_sel = {
 };
 
 struct clk_divider meson8b_mpeg_clk_div = {
-	.reg = (void *)MESON8B_REG_HHI_MPEG,
+	.reg = (void *)HHI_MPEG_CLK_CNTL,
 	.shift = 0,
 	.width = 7,
 	.lock = &clk_lock,
@@ -300,7 +300,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
 };
 
 struct clk_gate meson8b_clk81 = {
-	.reg = (void *)MESON8B_REG_HHI_MPEG,
+	.reg = (void *)HHI_MPEG_CLK_CNTL,
 	.bit_idx = 7,
 	.lock = &clk_lock,
 	.hw.init = &(struct clk_init_data){
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 5b9cb9f..b2f29f7 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -30,11 +30,10 @@
  *
  * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
  */
-#define MESON8B_REG_SYS_CPU_CNTL1	0x015c /* 0x57 offset in data sheet */
-#define MESON8B_REG_HHI_MPEG		0x0174 /* 0x5d offset in data sheet */
-#define MESON8B_REG_MALI		0x01b0 /* 0x6c offset in data sheet */
-#define MESON8B_REG_PLL_FIXED		0x0280
-#define MESON8B_REG_PLL_SYS		0x0300
-#define MESON8B_REG_PLL_VID		0x0320
+#define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
+#define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
+#define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
+#define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
+#define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
 
 #endif /* __MESON8B_H */
-- 
2.5.0

[PATCH v2 4/7] clk: meson: Copy meson8b CLKID defines to private header file

[Alexander Müller]

Only expose future CLKID constants if necessary. This patch
removes CLK_NR_CLKS from the DT bindings but leaves all previously
defined CLKIDs there to keep backward compatibility.

Signed-off-by: Alexander Müller <serveralex@gmail.com>
---
 drivers/clk/meson/meson8b.c              |  1 -
 drivers/clk/meson/meson8b.h              | 27 +++++++++++++++++++++++++++
 include/dt-bindings/clock/meson8b-clkc.h |  2 --
 3 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 0c6e26f..9a656d9 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -21,7 +21,6 @@
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/of_address.h>
-#include <dt-bindings/clock/meson8b-clkc.h>
 #include <linux/platform_device.h>
 #include <linux/module.h>
 
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index b2f29f7..f8c6942 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -36,4 +36,31 @@
 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
 #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
 
+/*
+ * CLKID index values
+ *
+ * These indices are entirely contrived and do not map onto the hardware.
+ * Migrate them out of this header and into the DT header file when they need
+ * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
+ */
+
+#define CLKID_UNUSED		0
+#define CLKID_XTAL		1
+#define CLKID_PLL_FIXED		2
+#define CLKID_PLL_VID		3
+#define CLKID_PLL_SYS		4
+#define CLKID_FCLK_DIV2		5
+#define CLKID_FCLK_DIV3		6
+#define CLKID_FCLK_DIV4		7
+#define CLKID_FCLK_DIV5		8
+#define CLKID_FCLK_DIV7		9
+#define CLKID_CLK81		10
+#define CLKID_MALI		11
+#define CLKID_CPUCLK		12
+#define CLKID_ZERO		13
+#define CLKID_MPEG_SEL		14
+#define CLKID_MPEG_DIV		15
+
+#define CLK_NR_CLKS		(CLKID_MPEG_DIV + 1)
+
 #endif /* __MESON8B_H */
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 595a58d..a55ff8c 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -22,6 +22,4 @@
 #define CLKID_MPEG_SEL		14
 #define CLKID_MPEG_DIV		15
 
-#define CLK_NR_CLKS		(CLKID_MPEG_DIV + 1)
-
 #endif /* __MESON8B_CLKC_H */
-- 
2.5.0

[PATCH v2 5/7] meson: clk: Add CLKIDs for clock gates

[Alexander Müller]

Add clock ids for the clock gates to private meson8b header file.

Signed-off-by: Alexander Müller <serveralex@gmail.com>
---
 drivers/clk/meson/meson8b.h | 79 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 78 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index f8c6942..4ba8be5 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -60,7 +60,84 @@
 #define CLKID_ZERO		13
 #define CLKID_MPEG_SEL		14
 #define CLKID_MPEG_DIV		15
+#define CLKID_DDR		16
+#define CLKID_DOS		17
+#define CLKID_ISA		18
+#define CLKID_PL301		19
+#define CLKID_PERIPHS		20
+#define CLKID_SPICC		21
+#define CLKID_I2C		22
+#define CLKID_SAR_ADC		23
+#define CLKID_SMART_CARD	24
+#define CLKID_RNG0		25
+#define CLKID_UART0		26
+#define CLKID_SDHC		27
+#define CLKID_STREAM		28
+#define CLKID_ASYNC_FIFO	29
+#define CLKID_SDIO		30
+#define CLKID_ABUF		31
+#define CLKID_HIU_IFACE		32
+#define CLKID_ASSIST_MISC	33
+#define CLKID_SPI		34
+#define CLKID_I2S_SPDIF		35
+#define CLKID_ETH		36
+#define CLKID_DEMUX		37
+#define CLKID_AIU_GLUE		38
+#define CLKID_IEC958		39
+#define CLKID_I2S_OUT		40
+#define CLKID_AMCLK		41
+#define CLKID_AIFIFO2		42
+#define CLKID_MIXER		43
+#define CLKID_MIXER_IFACE	44
+#define CLKID_ADC		45
+#define CLKID_BLKMV		46
+#define CLKID_AIU		47
+#define CLKID_UART1		48
+#define CLKID_G2D		49
+#define CLKID_USB0		50
+#define CLKID_USB1		51
+#define CLKID_RESET		52
+#define CLKID_NAND		53
+#define CLKID_DOS_PARSER	54
+#define CLKID_USB		55
+#define CLKID_VDIN1		56
+#define CLKID_AHB_ARB0		57
+#define CLKID_EFUSE		58
+#define CLKID_BOOT_ROM		59
+#define CLKID_AHB_DATA_BUS	60
+#define CLKID_AHB_CTRL_BUS	61
+#define CLKID_HDMI_INTR_SYNC	62
+#define CLKID_HDMI_PCLK		63
+#define CLKID_USB1_DDR_BRIDGE	64
+#define CLKID_USB0_DDR_BRIDGE	65
+#define CLKID_MMC_PCLK		66
+#define CLKID_DVIN		67
+#define CLKID_UART2		68
+#define CLKID_SANA		69
+#define CLKID_VPU_INTR		70
+#define CLKID_SEC_AHB_AHB3_BRIDGE	71
+#define CLKID_CLK81_A9		72
+#define CLKID_VCLK2_VENCI0	73
+#define CLKID_VCLK2_VENCI1	74
+#define CLKID_VCLK2_VENCP0	75
+#define CLKID_VCLK2_VENCP1	76
+#define CLKID_GCLK_VENCI_INT	77
+#define CLKID_GCLK_VENCP_INT	78
+#define CLKID_DAC_CLK		79
+#define CLKID_AOCLK_GATE	80
+#define CLKID_IEC958_GATE	81
+#define CLKID_ENC480P		82
+#define CLKID_RNG1		83
+#define CLKID_GCLK_VENCL_INT	84
+#define CLKID_VCLK2_VENCLMCC	85
+#define CLKID_VCLK2_VENCL	86
+#define CLKID_VCLK2_OTHER	87
+#define CLKID_EDP		88
+#define CLKID_AO_MEDIA_CPU	89
+#define CLKID_AO_AHB_SRAM	90
+#define CLKID_AO_AHB_BUS	91
+#define CLKID_AO_IFACE		92
 
-#define CLK_NR_CLKS		(CLKID_MPEG_DIV + 1)
+#define CLK_NR_CLKS		(CLKID_AO_IFACE + 1)
 
 #endif /* __MESON8B_H */
-- 
2.5.0

[PATCH v2 6/7] gxbb: clk: Move MESON_GATE macro to gxbb

[Alexander Müller]

Signed-off-by: Alexander Müller <serveralex@gmail.com>
---
 drivers/clk/meson/clkc.h |  14 ----
 drivers/clk/meson/gxbb.c | 176 +++++++++++++++++++++++++----------------------
 2 files changed, 95 insertions(+), 95 deletions(-)

diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 53326c3..061a01e 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -97,20 +97,6 @@ struct meson_clk_mpll {
 	spinlock_t *lock;
 };
 
-#define MESON_GATE(_name, _reg, _bit)					\
-struct clk_gate gxbb_##_name = { 						\
-	.reg = (void __iomem *) _reg, 					\
-	.bit_idx = (_bit), 						\
-	.lock = &clk_lock,						\
-	.hw.init = &(struct clk_init_data) { 				\
-		.name = #_name,					\
-		.ops = &clk_gate_ops,					\
-		.parent_names = (const char *[]){ "clk81" },		\
-		.num_parents = 1,					\
-		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), 	\
-	},								\
-};
-
 /* clk_ops */
 extern const struct clk_ops meson_clk_pll_ro_ops;
 extern const struct clk_ops meson_clk_pll_ops;
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 007b715..84500e0 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -24,6 +24,20 @@
 #include "clkc.h"
 #include "gxbb.h"
 
+#define GXBB_GATE(_name, _reg, _bit)					\
+struct clk_gate gxbb_##_name = { 					\
+	.reg = (void __iomem *) _reg, 					\
+	.bit_idx = (_bit), 						\
+	.lock = &clk_lock,						\
+	.hw.init = &(struct clk_init_data) { 				\
+		.name = #_name,						\
+		.ops = &clk_gate_ops,					\
+		.parent_names = (const char *[]){ "clk81" },		\
+		.num_parents = 1,					\
+		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), 	\
+	},								\
+};
+
 static DEFINE_SPINLOCK(clk_lock);
 
 static const struct pll_rate_table sys_pll_rate_table[] = {
@@ -563,90 +577,90 @@ static struct clk_gate gxbb_clk81 = {
 };
 
 /* Everything Else (EE) domain gates */
-static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);
-static MESON_GATE(dos, HHI_GCLK_MPEG0, 1);
-static MESON_GATE(isa, HHI_GCLK_MPEG0, 5);
-static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6);
-static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7);
-static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8);
-static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9);
-static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10);
-static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11);
-static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12);
-static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13);
-static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14);
-static MESON_GATE(stream, HHI_GCLK_MPEG0, 15);
-static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16);
-static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);
-static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);
-static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
-static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
-static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);
-
-static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
-static MESON_GATE(eth, HHI_GCLK_MPEG1, 3);
-static MESON_GATE(demux, HHI_GCLK_MPEG1, 4);
-static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6);
-static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7);
-static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8);
-static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9);
-static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10);
-static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11);
-static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12);
-static MESON_GATE(adc, HHI_GCLK_MPEG1, 13);
-static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14);
-static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15);
-static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16);
-static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20);
-static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21);
-static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22);
-static MESON_GATE(reset, HHI_GCLK_MPEG1, 23);
-static MESON_GATE(nand, HHI_GCLK_MPEG1, 24);
-static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25);
-static MESON_GATE(usb, HHI_GCLK_MPEG1, 26);
-static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28);
-static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29);
-static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30);
-static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31);
-
-static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1);
-static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
-static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
-static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4);
-static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
-static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
-static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11);
-static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12);
-static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15);
-static MESON_GATE(sana, HHI_GCLK_MPEG2, 22);
-static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25);
-static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
-static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29);
-
-static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1);
-static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2);
-static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3);
-static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4);
-static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8);
-static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9);
-static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10);
-static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14);
-static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16);
-static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20);
-static MESON_GATE(rng1, HHI_GCLK_OTHER, 21);
-static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22);
-static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24);
-static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25);
-static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26);
-static MESON_GATE(edp, HHI_GCLK_OTHER, 31);
+static GXBB_GATE(ddr, HHI_GCLK_MPEG0, 0);
+static GXBB_GATE(dos, HHI_GCLK_MPEG0, 1);
+static GXBB_GATE(isa, HHI_GCLK_MPEG0, 5);
+static GXBB_GATE(pl301, HHI_GCLK_MPEG0, 6);
+static GXBB_GATE(periphs, HHI_GCLK_MPEG0, 7);
+static GXBB_GATE(spicc, HHI_GCLK_MPEG0, 8);
+static GXBB_GATE(i2c, HHI_GCLK_MPEG0, 9);
+static GXBB_GATE(sar_adc, HHI_GCLK_MPEG0, 10);
+static GXBB_GATE(smart_card, HHI_GCLK_MPEG0, 11);
+static GXBB_GATE(rng0, HHI_GCLK_MPEG0, 12);
+static GXBB_GATE(uart0, HHI_GCLK_MPEG0, 13);
+static GXBB_GATE(sdhc, HHI_GCLK_MPEG0, 14);
+static GXBB_GATE(stream, HHI_GCLK_MPEG0, 15);
+static GXBB_GATE(async_fifo, HHI_GCLK_MPEG0, 16);
+static GXBB_GATE(sdio, HHI_GCLK_MPEG0, 17);
+static GXBB_GATE(abuf, HHI_GCLK_MPEG0, 18);
+static GXBB_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
+static GXBB_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
+static GXBB_GATE(spi, HHI_GCLK_MPEG0, 30);
+
+static GXBB_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
+static GXBB_GATE(eth, HHI_GCLK_MPEG1, 3);
+static GXBB_GATE(demux, HHI_GCLK_MPEG1, 4);
+static GXBB_GATE(aiu_glue, HHI_GCLK_MPEG1, 6);
+static GXBB_GATE(iec958, HHI_GCLK_MPEG1, 7);
+static GXBB_GATE(i2s_out, HHI_GCLK_MPEG1, 8);
+static GXBB_GATE(amclk, HHI_GCLK_MPEG1, 9);
+static GXBB_GATE(aififo2, HHI_GCLK_MPEG1, 10);
+static GXBB_GATE(mixer, HHI_GCLK_MPEG1, 11);
+static GXBB_GATE(mixer_iface, HHI_GCLK_MPEG1, 12);
+static GXBB_GATE(adc, HHI_GCLK_MPEG1, 13);
+static GXBB_GATE(blkmv, HHI_GCLK_MPEG1, 14);
+static GXBB_GATE(aiu, HHI_GCLK_MPEG1, 15);
+static GXBB_GATE(uart1, HHI_GCLK_MPEG1, 16);
+static GXBB_GATE(g2d, HHI_GCLK_MPEG1, 20);
+static GXBB_GATE(usb0, HHI_GCLK_MPEG1, 21);
+static GXBB_GATE(usb1, HHI_GCLK_MPEG1, 22);
+static GXBB_GATE(reset, HHI_GCLK_MPEG1, 23);
+static GXBB_GATE(nand, HHI_GCLK_MPEG1, 24);
+static GXBB_GATE(dos_parser, HHI_GCLK_MPEG1, 25);
+static GXBB_GATE(usb, HHI_GCLK_MPEG1, 26);
+static GXBB_GATE(vdin1, HHI_GCLK_MPEG1, 28);
+static GXBB_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29);
+static GXBB_GATE(efuse, HHI_GCLK_MPEG1, 30);
+static GXBB_GATE(boot_rom, HHI_GCLK_MPEG1, 31);
+
+static GXBB_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1);
+static GXBB_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
+static GXBB_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
+static GXBB_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4);
+static GXBB_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
+static GXBB_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
+static GXBB_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11);
+static GXBB_GATE(dvin, HHI_GCLK_MPEG2, 12);
+static GXBB_GATE(uart2, HHI_GCLK_MPEG2, 15);
+static GXBB_GATE(sana, HHI_GCLK_MPEG2, 22);
+static GXBB_GATE(vpu_intr, HHI_GCLK_MPEG2, 25);
+static GXBB_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
+static GXBB_GATE(clk81_a53, HHI_GCLK_MPEG2, 29);
+
+static GXBB_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1);
+static GXBB_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2);
+static GXBB_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3);
+static GXBB_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4);
+static GXBB_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8);
+static GXBB_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9);
+static GXBB_GATE(dac_clk, HHI_GCLK_OTHER, 10);
+static GXBB_GATE(aoclk_gate, HHI_GCLK_OTHER, 14);
+static GXBB_GATE(iec958_gate, HHI_GCLK_OTHER, 16);
+static GXBB_GATE(enc480p, HHI_GCLK_OTHER, 20);
+static GXBB_GATE(rng1, HHI_GCLK_OTHER, 21);
+static GXBB_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22);
+static GXBB_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24);
+static GXBB_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25);
+static GXBB_GATE(vclk_other, HHI_GCLK_OTHER, 26);
+static GXBB_GATE(edp, HHI_GCLK_OTHER, 31);
 
 /* Always On (AO) domain gates */
 
-static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0);
-static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1);
-static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2);
-static MESON_GATE(ao_iface, HHI_GCLK_AO, 3);
-static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4);
+static GXBB_GATE(ao_media_cpu, HHI_GCLK_AO, 0);
+static GXBB_GATE(ao_ahb_sram, HHI_GCLK_AO, 1);
+static GXBB_GATE(ao_ahb_bus, HHI_GCLK_AO, 2);
+static GXBB_GATE(ao_iface, HHI_GCLK_AO, 3);
+static GXBB_GATE(ao_i2c, HHI_GCLK_AO, 4);
 
 /* Array of all clocks provided by this provider */
 
-- 
2.5.0

[PATCH v2 7/7] meson: clk: Add support for clock gates

[Alexander Müller]

This patch adds support for the meson8b clock gates. Most of
them are disabled by Amlogic U-Boot, but need to be enabled
for ethernet, USB and many other components.

Signed-off-by: Alexander Müller <serveralex@gmail.com>
---
 drivers/clk/meson/meson8b.c | 263 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/meson8b.h |   5 +
 2 files changed, 268 insertions(+)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 9a656d9..0a0e01d 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -27,6 +27,20 @@
 #include "clkc.h"
 #include "meson8b.h"
 
+#define MESON8B_GATE(_name, _reg, _bit)					\
+struct clk_gate meson8b_##_name = { 					\
+	.reg = (void __iomem *) _reg, 					\
+	.bit_idx = (_bit), 						\
+	.lock = &clk_lock,						\
+	.hw.init = &(struct clk_init_data) { 				\
+		.name = #_name,						\
+		.ops = &clk_gate_ops,					\
+		.parent_names = (const char *[]){ "clk81" },		\
+		.num_parents = 1,					\
+		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), 	\
+	},								\
+};
+
 static DEFINE_SPINLOCK(clk_lock);
 
 static const struct pll_rate_table sys_pll_rate_table[] = {
@@ -311,6 +325,92 @@ struct clk_gate meson8b_clk81 = {
 	},
 };
 
+/* Everything Else (EE) domain gates */
+
+static MESON8B_GATE(ddr, HHI_GCLK_MPEG0, 0);
+static MESON8B_GATE(dos, HHI_GCLK_MPEG0, 1);
+static MESON8B_GATE(isa, HHI_GCLK_MPEG0, 5);
+static MESON8B_GATE(pl301, HHI_GCLK_MPEG0, 6);
+static MESON8B_GATE(periphs, HHI_GCLK_MPEG0, 7);
+static MESON8B_GATE(spicc, HHI_GCLK_MPEG0, 8);
+static MESON8B_GATE(i2c, HHI_GCLK_MPEG0, 9);
+static MESON8B_GATE(sar_adc, HHI_GCLK_MPEG0, 10);
+static MESON8B_GATE(smart_card, HHI_GCLK_MPEG0, 11);
+static MESON8B_GATE(rng0, HHI_GCLK_MPEG0, 12);
+static MESON8B_GATE(uart0, HHI_GCLK_MPEG0, 13);
+static MESON8B_GATE(sdhc, HHI_GCLK_MPEG0, 14);
+static MESON8B_GATE(stream, HHI_GCLK_MPEG0, 15);
+static MESON8B_GATE(async_fifo, HHI_GCLK_MPEG0, 16);
+static MESON8B_GATE(sdio, HHI_GCLK_MPEG0, 17);
+static MESON8B_GATE(abuf, HHI_GCLK_MPEG0, 18);
+static MESON8B_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
+static MESON8B_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
+static MESON8B_GATE(spi, HHI_GCLK_MPEG0, 30);
+
+static MESON8B_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
+static MESON8B_GATE(eth, HHI_GCLK_MPEG1, 3);
+static MESON8B_GATE(demux, HHI_GCLK_MPEG1, 4);
+static MESON8B_GATE(aiu_glue, HHI_GCLK_MPEG1, 6);
+static MESON8B_GATE(iec958, HHI_GCLK_MPEG1, 7);
+static MESON8B_GATE(i2s_out, HHI_GCLK_MPEG1, 8);
+static MESON8B_GATE(amclk, HHI_GCLK_MPEG1, 9);
+static MESON8B_GATE(aififo2, HHI_GCLK_MPEG1, 10);
+static MESON8B_GATE(mixer, HHI_GCLK_MPEG1, 11);
+static MESON8B_GATE(mixer_iface, HHI_GCLK_MPEG1, 12);
+static MESON8B_GATE(adc, HHI_GCLK_MPEG1, 13);
+static MESON8B_GATE(blkmv, HHI_GCLK_MPEG1, 14);
+static MESON8B_GATE(aiu, HHI_GCLK_MPEG1, 15);
+static MESON8B_GATE(uart1, HHI_GCLK_MPEG1, 16);
+static MESON8B_GATE(g2d, HHI_GCLK_MPEG1, 20);
+static MESON8B_GATE(usb0, HHI_GCLK_MPEG1, 21);
+static MESON8B_GATE(usb1, HHI_GCLK_MPEG1, 22);
+static MESON8B_GATE(reset, HHI_GCLK_MPEG1, 23);
+static MESON8B_GATE(nand, HHI_GCLK_MPEG1, 24);
+static MESON8B_GATE(dos_parser, HHI_GCLK_MPEG1, 25);
+static MESON8B_GATE(usb, HHI_GCLK_MPEG1, 26);
+static MESON8B_GATE(vdin1, HHI_GCLK_MPEG1, 28);
+static MESON8B_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29);
+static MESON8B_GATE(efuse, HHI_GCLK_MPEG1, 30);
+static MESON8B_GATE(boot_rom, HHI_GCLK_MPEG1, 31);
+
+static MESON8B_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1);
+static MESON8B_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
+static MESON8B_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
+static MESON8B_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4);
+static MESON8B_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
+static MESON8B_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
+static MESON8B_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11);
+static MESON8B_GATE(dvin, HHI_GCLK_MPEG2, 12);
+static MESON8B_GATE(uart2, HHI_GCLK_MPEG2, 15);
+static MESON8B_GATE(sana, HHI_GCLK_MPEG2, 22);
+static MESON8B_GATE(vpu_intr, HHI_GCLK_MPEG2, 25);
+static MESON8B_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
+static MESON8B_GATE(clk81_a9, HHI_GCLK_MPEG2, 29);
+
+static MESON8B_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1);
+static MESON8B_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2);
+static MESON8B_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3);
+static MESON8B_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4);
+static MESON8B_GATE(gclk_venci_int, HHI_GCLK_OTHER, 8);
+static MESON8B_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9);
+static MESON8B_GATE(dac_clk, HHI_GCLK_OTHER, 10);
+static MESON8B_GATE(aoclk_gate, HHI_GCLK_OTHER, 14);
+static MESON8B_GATE(iec958_gate, HHI_GCLK_OTHER, 16);
+static MESON8B_GATE(enc480p, HHI_GCLK_OTHER, 20);
+static MESON8B_GATE(rng1, HHI_GCLK_OTHER, 21);
+static MESON8B_GATE(gclk_vencl_int, HHI_GCLK_OTHER, 22);
+static MESON8B_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24);
+static MESON8B_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25);
+static MESON8B_GATE(vclk2_other, HHI_GCLK_OTHER, 26);
+static MESON8B_GATE(edp, HHI_GCLK_OTHER, 31);
+
+/* Always On (AO) domain gates */
+
+static MESON8B_GATE(ao_media_cpu, HHI_GCLK_AO, 0);
+static MESON8B_GATE(ao_ahb_sram, HHI_GCLK_AO, 1);
+static MESON8B_GATE(ao_ahb_bus, HHI_GCLK_AO, 2);
+static MESON8B_GATE(ao_iface, HHI_GCLK_AO, 3);
+
 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 	.hws = {
 		[CLKID_XTAL] = &meson8b_xtal.hw,
@@ -326,6 +426,83 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 		[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
 		[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
 		[CLKID_CLK81] = &meson8b_clk81.hw,
+		[CLKID_DDR]		    = &meson8b_ddr.hw,
+		[CLKID_DOS]		    = &meson8b_dos.hw,
+		[CLKID_ISA]		    = &meson8b_isa.hw,
+		[CLKID_PL301]		    = &meson8b_pl301.hw,
+		[CLKID_PERIPHS]		    = &meson8b_periphs.hw,
+		[CLKID_SPICC]		    = &meson8b_spicc.hw,
+		[CLKID_I2C]		    = &meson8b_i2c.hw,
+		[CLKID_SAR_ADC]		    = &meson8b_sar_adc.hw,
+		[CLKID_SMART_CARD]	    = &meson8b_smart_card.hw,
+		[CLKID_RNG0]		    = &meson8b_rng0.hw,
+		[CLKID_UART0]		    = &meson8b_uart0.hw,
+		[CLKID_SDHC]		    = &meson8b_sdhc.hw,
+		[CLKID_STREAM]		    = &meson8b_stream.hw,
+		[CLKID_ASYNC_FIFO]	    = &meson8b_async_fifo.hw,
+		[CLKID_SDIO]		    = &meson8b_sdio.hw,
+		[CLKID_ABUF]		    = &meson8b_abuf.hw,
+		[CLKID_HIU_IFACE]	    = &meson8b_hiu_iface.hw,
+		[CLKID_ASSIST_MISC]	    = &meson8b_assist_misc.hw,
+		[CLKID_SPI]		    = &meson8b_spi.hw,
+		[CLKID_I2S_SPDIF]	    = &meson8b_i2s_spdif.hw,
+		[CLKID_ETH]		    = &meson8b_eth.hw,
+		[CLKID_DEMUX]		    = &meson8b_demux.hw,
+		[CLKID_AIU_GLUE]	    = &meson8b_aiu_glue.hw,
+		[CLKID_IEC958]		    = &meson8b_iec958.hw,
+		[CLKID_I2S_OUT]		    = &meson8b_i2s_out.hw,
+		[CLKID_AMCLK]		    = &meson8b_amclk.hw,
+		[CLKID_AIFIFO2]		    = &meson8b_aififo2.hw,
+		[CLKID_MIXER]		    = &meson8b_mixer.hw,
+		[CLKID_MIXER_IFACE]	    = &meson8b_mixer_iface.hw,
+		[CLKID_ADC]		    = &meson8b_adc.hw,
+		[CLKID_BLKMV]		    = &meson8b_blkmv.hw,
+		[CLKID_AIU]		    = &meson8b_aiu.hw,
+		[CLKID_UART1]		    = &meson8b_uart1.hw,
+		[CLKID_G2D]		    = &meson8b_g2d.hw,
+		[CLKID_USB0]		    = &meson8b_usb0.hw,
+		[CLKID_USB1]		    = &meson8b_usb1.hw,
+		[CLKID_RESET]		    = &meson8b_reset.hw,
+		[CLKID_NAND]		    = &meson8b_nand.hw,
+		[CLKID_DOS_PARSER]	    = &meson8b_dos_parser.hw,
+		[CLKID_USB]		    = &meson8b_usb.hw,
+		[CLKID_VDIN1]		    = &meson8b_vdin1.hw,
+		[CLKID_AHB_ARB0]	    = &meson8b_ahb_arb0.hw,
+		[CLKID_EFUSE]		    = &meson8b_efuse.hw,
+		[CLKID_BOOT_ROM]	    = &meson8b_boot_rom.hw,
+		[CLKID_AHB_DATA_BUS]	    = &meson8b_ahb_data_bus.hw,
+		[CLKID_AHB_CTRL_BUS]	    = &meson8b_ahb_ctrl_bus.hw,
+		[CLKID_HDMI_INTR_SYNC]	    = &meson8b_hdmi_intr_sync.hw,
+		[CLKID_HDMI_PCLK]	    = &meson8b_hdmi_pclk.hw,
+		[CLKID_USB1_DDR_BRIDGE]	    = &meson8b_usb1_ddr_bridge.hw,
+		[CLKID_USB0_DDR_BRIDGE]	    = &meson8b_usb0_ddr_bridge.hw,
+		[CLKID_MMC_PCLK]	    = &meson8b_mmc_pclk.hw,
+		[CLKID_DVIN]		    = &meson8b_dvin.hw,
+		[CLKID_UART2]		    = &meson8b_uart2.hw,
+		[CLKID_SANA]		    = &meson8b_sana.hw,
+		[CLKID_VPU_INTR]	    = &meson8b_vpu_intr.hw,
+		[CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
+		[CLKID_CLK81_A9]	    = &meson8b_clk81_a9.hw,
+		[CLKID_VCLK2_VENCI0]	    = &meson8b_vclk2_venci0.hw,
+		[CLKID_VCLK2_VENCI1]	    = &meson8b_vclk2_venci1.hw,
+		[CLKID_VCLK2_VENCP0]	    = &meson8b_vclk2_vencp0.hw,
+		[CLKID_VCLK2_VENCP1]	    = &meson8b_vclk2_vencp1.hw,
+		[CLKID_GCLK_VENCI_INT]	    = &meson8b_gclk_venci_int.hw,
+		[CLKID_GCLK_VENCI_INT]	    = &meson8b_gclk_vencp_int.hw,
+		[CLKID_DAC_CLK]		    = &meson8b_dac_clk.hw,
+		[CLKID_AOCLK_GATE]	    = &meson8b_aoclk_gate.hw,
+		[CLKID_IEC958_GATE]	    = &meson8b_iec958_gate.hw,
+		[CLKID_ENC480P]		    = &meson8b_enc480p.hw,
+		[CLKID_RNG1]		    = &meson8b_rng1.hw,
+		[CLKID_GCLK_VENCL_INT]	    = &meson8b_gclk_vencl_int.hw,
+		[CLKID_VCLK2_VENCLMCC]	    = &meson8b_vclk2_venclmcc.hw,
+		[CLKID_VCLK2_VENCL]	    = &meson8b_vclk2_vencl.hw,
+		[CLKID_VCLK2_OTHER]	    = &meson8b_vclk2_other.hw,
+		[CLKID_EDP]		    = &meson8b_edp.hw,
+		[CLKID_AO_MEDIA_CPU]	    = &meson8b_ao_media_cpu.hw,
+		[CLKID_AO_AHB_SRAM]	    = &meson8b_ao_ahb_sram.hw,
+		[CLKID_AO_AHB_BUS]	    = &meson8b_ao_ahb_bus.hw,
+		[CLKID_AO_IFACE]	    = &meson8b_ao_iface.hw,
 	},
 	.num = CLK_NR_CLKS,
 };
@@ -336,6 +513,87 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = {
 	&meson8b_sys_pll,
 };
 
+static struct clk_gate *meson8b_clk_gates[] = {
+	&meson8b_clk81,
+	&meson8b_ddr,
+	&meson8b_dos,
+	&meson8b_isa,
+	&meson8b_pl301,
+	&meson8b_periphs,
+	&meson8b_spicc,
+	&meson8b_i2c,
+	&meson8b_sar_adc,
+	&meson8b_smart_card,
+	&meson8b_rng0,
+	&meson8b_uart0,
+	&meson8b_sdhc,
+	&meson8b_stream,
+	&meson8b_async_fifo,
+	&meson8b_sdio,
+	&meson8b_abuf,
+	&meson8b_hiu_iface,
+	&meson8b_assist_misc,
+	&meson8b_spi,
+	&meson8b_i2s_spdif,
+	&meson8b_eth,
+	&meson8b_demux,
+	&meson8b_aiu_glue,
+	&meson8b_iec958,
+	&meson8b_i2s_out,
+	&meson8b_amclk,
+	&meson8b_aififo2,
+	&meson8b_mixer,
+	&meson8b_mixer_iface,
+	&meson8b_adc,
+	&meson8b_blkmv,
+	&meson8b_aiu,
+	&meson8b_uart1,
+	&meson8b_g2d,
+	&meson8b_usb0,
+	&meson8b_usb1,
+	&meson8b_reset,
+	&meson8b_nand,
+	&meson8b_dos_parser,
+	&meson8b_usb,
+	&meson8b_vdin1,
+	&meson8b_ahb_arb0,
+	&meson8b_efuse,
+	&meson8b_boot_rom,
+	&meson8b_ahb_data_bus,
+	&meson8b_ahb_ctrl_bus,
+	&meson8b_hdmi_intr_sync,
+	&meson8b_hdmi_pclk,
+	&meson8b_usb1_ddr_bridge,
+	&meson8b_usb0_ddr_bridge,
+	&meson8b_mmc_pclk,
+	&meson8b_dvin,
+	&meson8b_uart2,
+	&meson8b_sana,
+	&meson8b_vpu_intr,
+	&meson8b_sec_ahb_ahb3_bridge,
+	&meson8b_clk81_a9,
+	&meson8b_vclk2_venci0,
+	&meson8b_vclk2_venci1,
+	&meson8b_vclk2_vencp0,
+	&meson8b_vclk2_vencp1,
+	&meson8b_gclk_venci_int,
+	&meson8b_gclk_vencp_int,
+	&meson8b_dac_clk,
+	&meson8b_aoclk_gate,
+	&meson8b_iec958_gate,
+	&meson8b_enc480p,
+	&meson8b_rng1,
+	&meson8b_gclk_vencl_int,
+	&meson8b_vclk2_venclmcc,
+	&meson8b_vclk2_vencl,
+	&meson8b_vclk2_other,
+	&meson8b_edp,
+	&meson8b_ao_media_cpu,
+	&meson8b_ao_ahb_sram,
+	&meson8b_ao_ahb_bus,
+	&meson8b_ao_iface,
+};
+
 static int meson8b_clkc_probe(struct platform_device *pdev)
 {
 	void __iomem *clk_base;
@@ -363,6 +621,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 	meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
 	meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
 
+	/* Populate base address for gates */
+	for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
+		meson8b_clk_gates[i]->reg = clk_base +
+			(u32)meson8b_clk_gates[i]->reg;
+
 	/*
 	 * register all clks
 	 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 4ba8be5..57809d2 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -30,6 +30,11 @@
  *
  * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
  */
+#define HHI_GCLK_MPEG0			0x140 /* 0x50 offset in data sheet */
+#define HHI_GCLK_MPEG1			0x144 /* 0x51 offset in data sheet */
+#define HHI_GCLK_MPEG2			0x148 /* 0x52 offset in data sheet */
+#define HHI_GCLK_OTHER			0x150 /* 0x54 offset in data sheet */
+#define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
 #define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
-- 
2.5.0

Re: [PATCH v2 6/7] gxbb: clk: Move MESON_GATE macro to gxbb

[Michael Turquette]

Hi Alexander,

Quoting Alexander M=C3=BCller (2016-07-13 10:49:40)
> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com>
> ---
>  drivers/clk/meson/clkc.h |  14 ----
>  drivers/clk/meson/gxbb.c | 176 +++++++++++++++++++++++++----------------=
------
>  2 files changed, 95 insertions(+), 95 deletions(-)
> =

> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> index 53326c3..061a01e 100644
> --- a/drivers/clk/meson/clkc.h
> +++ b/drivers/clk/meson/clkc.h
> @@ -97,20 +97,6 @@ struct meson_clk_mpll {
>         spinlock_t *lock;
>  };
>  =

> -#define MESON_GATE(_name, _reg, _bit)                                  \
> -struct clk_gate gxbb_##_name =3D {                                      =
         \

Please leave this macro in clkc.h, but change the above line to:

	#define MESON_GATE(_name, _reg, _bit)	\
	struct clk_gate _name =3D {		\

Note that gxbb_##_name is replaced with _name. I should have done it
like this from the beginning but it's a bit of a brain fart.

>  /* Everything Else (EE) domain gates */
> -static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);

Then reflow the above gxbb gate clock like so:

	static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);

Then you can re-use the same macro in your meson8b driver by prefixing
all of your gate clocks with "meson8b_".

Regards,
Mike

Re: [PATCH v2 2/7] meson: clk: Move register definitions to meson8b.h

[Michael Turquette]

Hi Alexander,

Quoting Alexander M=C3=BCller (2016-07-13 10:49:36)
> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com>

Please explain why you are moving them in the changelog. It's clear
*what* you are doing, but the *why* is missing.

Regards,
Mike

> ---
>  drivers/clk/meson/meson8b.c | 17 +----------------
>  drivers/clk/meson/meson8b.h | 40 ++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 41 insertions(+), 16 deletions(-)
>  create mode 100644 drivers/clk/meson/meson8b.h
> =

> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index b1902e9..537cc53 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -26,22 +26,7 @@
>  #include <linux/module.h>
>  =

>  #include "clkc.h"
> -
> -/*
> - * Clock controller register offsets
> - *
> - * Register offsets from the HardKernel[0] data sheet are listed in comm=
ent
> - * blocks below. Those offsets must be multiplied by 4 before adding the=
m to
> - * the base address to get the right value
> - *
> - * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150=
126.pdf
> - */
> -#define MESON8B_REG_SYS_CPU_CNTL1      0x015c /* 0x57 offset in data she=
et */
> -#define MESON8B_REG_HHI_MPEG           0x0174 /* 0x5d offset in data she=
et */
> -#define MESON8B_REG_MALI               0x01b0 /* 0x6c offset in data she=
et */
> -#define MESON8B_REG_PLL_FIXED          0x0280
> -#define MESON8B_REG_PLL_SYS            0x0300
> -#define MESON8B_REG_PLL_VID            0x0320
> +#include "meson8b.h"
>  =

>  static DEFINE_SPINLOCK(clk_lock);
>  =

> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> new file mode 100644
> index 0000000..5b9cb9f
> --- /dev/null
> +++ b/drivers/clk/meson/meson8b.h
> @@ -0,0 +1,40 @@
> +/*
> + * Copyright (c) 2015 Endless Mobile, Inc.
> + * Author: Carlo Caione <carlo@endlessm.com>
> + *
> + * Copyright (c) 2016 BayLibre, Inc.
> + * Michael Turquette <mturquette@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify =
it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License=
 for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License alo=
ng with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef __MESON8B_H
> +#define __MESON8B_H
> +
> +/*
> + * Clock controller register offsets
> + *
> + * Register offsets from the HardKernel[0] data sheet are listed in comm=
ent
> + * blocks below. Those offsets must be multiplied by 4 before adding the=
m to
> + * the base address to get the right value
> + *
> + * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150=
126.pdf
> + */
> +#define MESON8B_REG_SYS_CPU_CNTL1      0x015c /* 0x57 offset in data she=
et */
> +#define MESON8B_REG_HHI_MPEG           0x0174 /* 0x5d offset in data she=
et */
> +#define MESON8B_REG_MALI               0x01b0 /* 0x6c offset in data she=
et */
> +#define MESON8B_REG_PLL_FIXED          0x0280
> +#define MESON8B_REG_PLL_SYS            0x0300
> +#define MESON8B_REG_PLL_VID            0x0320
> +
> +#endif /* __MESON8B_H */
> -- =

> 2.5.0
>=20

Re: [PATCH v2 5/7] meson: clk: Add CLKIDs for clock gates

[Michael Turquette]

Quoting Alexander M=C3=BCller (2016-07-13 10:49:39)
> Add clock ids for the clock gates to private meson8b header file.
> =

> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com>
> ---
>  drivers/clk/meson/meson8b.h | 79 +++++++++++++++++++++++++++++++++++++++=
+++++-
>  1 file changed, 78 insertions(+), 1 deletion(-)
> =

> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index f8c6942..4ba8be5 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -60,7 +60,84 @@
>  #define CLKID_ZERO             13
>  #define CLKID_MPEG_SEL         14
>  #define CLKID_MPEG_DIV         15
> +#define CLKID_DDR              16
> +#define CLKID_DOS              17
> +#define CLKID_ISA              18
> +#define CLKID_PL301            19
> +#define CLKID_PERIPHS          20
> +#define CLKID_SPICC            21
> +#define CLKID_I2C              22
> +#define CLKID_SAR_ADC          23
> +#define CLKID_SMART_CARD       24
> +#define CLKID_RNG0             25
> +#define CLKID_UART0            26
> +#define CLKID_SDHC             27
> +#define CLKID_STREAM           28
> +#define CLKID_ASYNC_FIFO       29
> +#define CLKID_SDIO             30
> +#define CLKID_ABUF             31
> +#define CLKID_HIU_IFACE                32
> +#define CLKID_ASSIST_MISC      33
> +#define CLKID_SPI              34
> +#define CLKID_I2S_SPDIF                35
> +#define CLKID_ETH              36
> +#define CLKID_DEMUX            37
> +#define CLKID_AIU_GLUE         38
> +#define CLKID_IEC958           39
> +#define CLKID_I2S_OUT          40
> +#define CLKID_AMCLK            41
> +#define CLKID_AIFIFO2          42
> +#define CLKID_MIXER            43
> +#define CLKID_MIXER_IFACE      44
> +#define CLKID_ADC              45
> +#define CLKID_BLKMV            46
> +#define CLKID_AIU              47
> +#define CLKID_UART1            48
> +#define CLKID_G2D              49
> +#define CLKID_USB0             50
> +#define CLKID_USB1             51
> +#define CLKID_RESET            52
> +#define CLKID_NAND             53
> +#define CLKID_DOS_PARSER       54
> +#define CLKID_USB              55
> +#define CLKID_VDIN1            56
> +#define CLKID_AHB_ARB0         57
> +#define CLKID_EFUSE            58
> +#define CLKID_BOOT_ROM         59
> +#define CLKID_AHB_DATA_BUS     60
> +#define CLKID_AHB_CTRL_BUS     61
> +#define CLKID_HDMI_INTR_SYNC   62
> +#define CLKID_HDMI_PCLK                63
> +#define CLKID_USB1_DDR_BRIDGE  64
> +#define CLKID_USB0_DDR_BRIDGE  65
> +#define CLKID_MMC_PCLK         66
> +#define CLKID_DVIN             67
> +#define CLKID_UART2            68
> +#define CLKID_SANA             69
> +#define CLKID_VPU_INTR         70
> +#define CLKID_SEC_AHB_AHB3_BRIDGE      71
> +#define CLKID_CLK81_A9         72
> +#define CLKID_VCLK2_VENCI0     73
> +#define CLKID_VCLK2_VENCI1     74
> +#define CLKID_VCLK2_VENCP0     75
> +#define CLKID_VCLK2_VENCP1     76
> +#define CLKID_GCLK_VENCI_INT   77
> +#define CLKID_GCLK_VENCP_INT   78
> +#define CLKID_DAC_CLK          79
> +#define CLKID_AOCLK_GATE       80
> +#define CLKID_IEC958_GATE      81
> +#define CLKID_ENC480P          82
> +#define CLKID_RNG1             83
> +#define CLKID_GCLK_VENCL_INT   84
> +#define CLKID_VCLK2_VENCLMCC   85
> +#define CLKID_VCLK2_VENCL      86
> +#define CLKID_VCLK2_OTHER      87
> +#define CLKID_EDP              88
> +#define CLKID_AO_MEDIA_CPU     89
> +#define CLKID_AO_AHB_SRAM      90
> +#define CLKID_AO_AHB_BUS       91
> +#define CLKID_AO_IFACE         92
>  =

> -#define CLK_NR_CLKS            (CLKID_MPEG_DIV + 1)
> +#define CLK_NR_CLKS            (CLKID_AO_IFACE + 1)

You can just make this:

	#define NR_CLKS		93

Regards,
Mike

>  =

>  #endif /* __MESON8B_H */
> -- =

> 2.5.0
>=20

Re: [PATCH v2 7/7] meson: clk: Add support for clock gates

[Michael Turquette]

Quoting Alexander M=C3=BCller (2016-07-13 10:49:41)
> This patch adds support for the meson8b clock gates. Most of
> them are disabled by Amlogic U-Boot, but need to be enabled
> for ethernet, USB and many other components.
> =

> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com>
> ---
>  drivers/clk/meson/meson8b.c | 263 ++++++++++++++++++++++++++++++++++++++=
++++++
>  drivers/clk/meson/meson8b.h |   5 +
>  2 files changed, 268 insertions(+)
> =

> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index 9a656d9..0a0e01d 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -27,6 +27,20 @@
>  #include "clkc.h"
>  #include "meson8b.h"
>  =

> +#define MESON8B_GATE(_name, _reg, _bit)                                 =
       \
> +struct clk_gate meson8b_##_name =3D {                                   =
 \
> +       .reg =3D (void __iomem *) _reg,                                  =
 \
> +       .bit_idx =3D (_bit),                                             =
 \
> +       .lock =3D &clk_lock,                                             =
 \
> +       .hw.init =3D &(struct clk_init_data) {                           =
 \
> +               .name =3D #_name,                                        =
 \
> +               .ops =3D &clk_gate_ops,                                  =
 \
> +               .parent_names =3D (const char *[]){ "clk81" },           =
 \
> +               .num_parents =3D 1,                                      =
 \
> +               .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),    =
 \
> +       },                                                              \
> +};

As I mentioned in patch #6, let's keep this shared between meson8b and
gxbb in clkc.h.

> +
>  static DEFINE_SPINLOCK(clk_lock);
>  =

>  static const struct pll_rate_table sys_pll_rate_table[] =3D {
> @@ -311,6 +325,92 @@ struct clk_gate meson8b_clk81 =3D {
>         },
>  };
>  =

> +/* Everything Else (EE) domain gates */
> +
> +static MESON8B_GATE(ddr, HHI_GCLK_MPEG0, 0);

To do the above, "ddr" will need to become "meson8b_ddr", etc.

Regards,
Mike

Re: [PATCH v2 6/7] gxbb: clk: Move MESON_GATE macro to gxbb

[Alexander Müller]

Hi Mike,=20

What about the clk name set by the macro MESON_GATE (#_name)? That would =
change too and I guess that's not desired here.

Regards,=20
Alex

> On 13 Jul 2016, at 23:32, Michael Turquette <mturquette@baylibre.com> =
wrote:
>=20
> Hi Alexander,
>=20
> Quoting Alexander M=C3=BCller (2016-07-13 10:49:40)
>> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com>
>> ---
>> drivers/clk/meson/clkc.h |  14 ----
>> drivers/clk/meson/gxbb.c | 176 =
+++++++++++++++++++++++++----------------------
>> 2 files changed, 95 insertions(+), 95 deletions(-)
>>=20
>> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
>> index 53326c3..061a01e 100644
>> --- a/drivers/clk/meson/clkc.h
>> +++ b/drivers/clk/meson/clkc.h
>> @@ -97,20 +97,6 @@ struct meson_clk_mpll {
>>        spinlock_t *lock;
>> };
>>=20
>> -#define MESON_GATE(_name, _reg, _bit)                                =
  \
>> -struct clk_gate gxbb_##_name =3D {                                   =
            \
>=20
> Please leave this macro in clkc.h, but change the above line to:
>=20
> 	#define MESON_GATE(_name, _reg, _bit)	\
> 	struct clk_gate _name =3D {		\
>=20
> Note that gxbb_##_name is replaced with _name. I should have done it
> like this from the beginning but it's a bit of a brain fart.
>=20
>> /* Everything Else (EE) domain gates */
>> -static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);
>=20
> Then reflow the above gxbb gate clock like so:
>=20
> 	static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
>=20
> Then you can re-use the same macro in your meson8b driver by prefixing
> all of your gate clocks with "meson8b_".
>=20
> Regards,
> Mike

Re: [PATCH v2 6/7] gxbb: clk: Move MESON_GATE macro to gxbb

[Michael Turquette]

Quoting Alexander M=C3=BCller (2016-07-14 10:09:33)
> Hi Mike, =

> =

> What about the clk name set by the macro MESON_GATE (#_name)? That would =
change too and I guess that's not desired here.

Yes it is desired. The names passed into the macro will have to change
for both the meson8b driver and the gxbb driver. That's OK because we
don't want to copy/paste this little macro for every new chip that
AmLogic releases. Better to refactor now while we only have two affected
drivers, and one of them does not yet have gate support merged.

Regards,
Mike

> =

> Regards, =

> Alex
> =

> > On 13 Jul 2016, at 23:32, Michael Turquette <mturquette@baylibre.com> w=
rote:
> > =

> > Hi Alexander,
> > =

> > Quoting Alexander M=C3=BCller (2016-07-13 10:49:40)
> >> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com>
> >> ---
> >> drivers/clk/meson/clkc.h |  14 ----
> >> drivers/clk/meson/gxbb.c | 176 +++++++++++++++++++++++++--------------=
--------
> >> 2 files changed, 95 insertions(+), 95 deletions(-)
> >> =

> >> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> >> index 53326c3..061a01e 100644
> >> --- a/drivers/clk/meson/clkc.h
> >> +++ b/drivers/clk/meson/clkc.h
> >> @@ -97,20 +97,6 @@ struct meson_clk_mpll {
> >>        spinlock_t *lock;
> >> };
> >> =

> >> -#define MESON_GATE(_name, _reg, _bit)                                =
  \
> >> -struct clk_gate gxbb_##_name =3D {                                   =
            \
> > =

> > Please leave this macro in clkc.h, but change the above line to:
> > =

> >       #define MESON_GATE(_name, _reg, _bit)   \
> >       struct clk_gate _name =3D {               \
> > =

> > Note that gxbb_##_name is replaced with _name. I should have done it
> > like this from the beginning but it's a bit of a brain fart.
> > =

> >> /* Everything Else (EE) domain gates */
> >> -static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);
> > =

> > Then reflow the above gxbb gate clock like so:
> > =

> >       static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
> > =

> > Then you can re-use the same macro in your meson8b driver by prefixing
> > all of your gate clocks with "meson8b_".
> > =

> > Regards,
> > Mike
>=20