* [clk:clk-doc 4/5] drivers/clk/nxp/clk-lpc32xx.c:1094:5: error: 'struct clk_fixed_rate' has no member named 'flags'
@ 2018-12-14 9:31 kbuild test robot
2018-12-14 17:20 ` Stephen Boyd
0 siblings, 1 reply; 2+ messages in thread
From: kbuild test robot @ 2018-12-14 9:31 UTC (permalink / raw)
To: Stephen Boyd; +Cc: kbuild-all, linux-clk, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 25679 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-doc
head: 9369ad9e3dd4ec5a5d189825a49c1b76bb733571
commit: 9274efae17dcaf8bb2f8abf802ea254ae8810794 [4/5] clk: Remove 'flags' member of struct clk_fixed_rate
config: arm-lpc32xx_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 9274efae17dcaf8bb2f8abf802ea254ae8810794
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
>> drivers/clk/nxp/clk-lpc32xx.c:1094:5: error: 'struct clk_fixed_rate' has no member named 'flags'
.flags = (_flags), \
^
>> drivers/clk/nxp/clk-lpc32xx.c:1228:2: note: in expansion of macro 'LPC32XX_DEFINE_FIXED'
LPC32XX_DEFINE_FIXED(RTC, 32768, 0),
^~~~~~~~~~~~~~~~~~~~
drivers/clk/nxp/clk-lpc32xx.c: In function 'lpc32xx_clk_register':
drivers/clk/nxp/clk-lpc32xx.c:1471:21: error: 'struct clk_fixed_rate' has no member named 'flags'
parents[0], fixed->flags, fixed->fixed_rate);
^~
vim +1094 drivers/clk/nxp/clk-lpc32xx.c
f7c82a60 Vladimir Zapolskiy 2015-12-06 1087
f7c82a60 Vladimir Zapolskiy 2015-12-06 1088 #define LPC32XX_DEFINE_FIXED(_idx, _rate, _flags) \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1089 [CLK_PREFIX(_idx)] = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1090 .type = CLK_FIXED, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1091 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1092 .f = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1093 .fixed_rate = (_rate), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 @1094 .flags = (_flags), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1095 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1096 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1097 }
f7c82a60 Vladimir Zapolskiy 2015-12-06 1098
f7c82a60 Vladimir Zapolskiy 2015-12-06 1099 #define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1100 [CLK_PREFIX(_idx)] = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1101 .type = CLK_LPC32XX_PLL, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1102 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1103 .hw0 = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1104 .ops = &clk_ ##_name ## _ops, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1105 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1106 .pll = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1107 .reg = LPC32XX_CLKPWR_ ## _reg, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1108 .enable = (_enable), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1109 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1110 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1111 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1112 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1113 }
f7c82a60 Vladimir Zapolskiy 2015-12-06 1114
f7c82a60 Vladimir Zapolskiy 2015-12-06 1115 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1116 [CLK_PREFIX(_idx)] = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1117 .type = CLK_MUX, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1118 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1119 .hw0 = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1120 .ops = (_flags & CLK_MUX_READ_ONLY ? \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1121 &lpc32xx_clk_mux_ro_ops : \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1122 &lpc32xx_clk_mux_ops), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1123 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1124 .mux = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1125 .reg = LPC32XX_CLKPWR_ ## _reg, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1126 .mask = (_mask), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1127 .shift = (_shift), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1128 .table = (_table), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1129 .flags = (_flags), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1130 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1131 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1132 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1133 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1134 }
f7c82a60 Vladimir Zapolskiy 2015-12-06 1135
f7c82a60 Vladimir Zapolskiy 2015-12-06 1136 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1137 [CLK_PREFIX(_idx)] = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1138 .type = CLK_DIV, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1139 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1140 .hw0 = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1141 .ops = &lpc32xx_clk_divider_ops, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1142 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1143 .div = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1144 .reg = LPC32XX_CLKPWR_ ## _reg, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1145 .shift = (_shift), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1146 .width = (_width), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1147 .table = (_table), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1148 .flags = (_flags), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1149 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1150 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1151 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1152 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1153 }
f7c82a60 Vladimir Zapolskiy 2015-12-06 1154
f7c82a60 Vladimir Zapolskiy 2015-12-06 1155 #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1156 [CLK_PREFIX(_idx)] = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1157 .type = CLK_GATE, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1158 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1159 .hw0 = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1160 .ops = &lpc32xx_clk_gate_ops, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1161 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1162 .gate = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1163 .reg = LPC32XX_CLKPWR_ ## _reg, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1164 .bit_idx = (_bit), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1165 .flags = (_flags), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1166 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1167 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1168 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1169 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1170 }
f7c82a60 Vladimir Zapolskiy 2015-12-06 1171
f7c82a60 Vladimir Zapolskiy 2015-12-06 1172 #define LPC32XX_DEFINE_CLK(_idx, _reg, _e, _em, _d, _dm, _b, _bm, _ops) \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1173 [CLK_PREFIX(_idx)] = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1174 .type = CLK_LPC32XX, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1175 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1176 .hw0 = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1177 .ops = &(_ops), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1178 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1179 .clk = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1180 .reg = LPC32XX_CLKPWR_ ## _reg, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1181 .enable = (_e), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1182 .enable_mask = (_em), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1183 .disable = (_d), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1184 .disable_mask = (_dm), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1185 .busy = (_b), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1186 .busy_mask = (_bm), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1187 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1188 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1189 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1190 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1191 }
f7c82a60 Vladimir Zapolskiy 2015-12-06 1192
f7c82a60 Vladimir Zapolskiy 2015-12-06 1193 #define LPC32XX_DEFINE_USB(_idx, _ce, _cd, _cm, _e, _b, _ops) \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1194 [CLK_PREFIX(_idx)] = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1195 .type = CLK_LPC32XX_USB, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1196 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1197 .hw0 = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1198 .ops = &(_ops), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1199 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1200 .usb_clk = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1201 .ctrl_enable = (_ce), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1202 .ctrl_disable = (_cd), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1203 .ctrl_mask = (_cm), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1204 .enable = (_e), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1205 .busy = (_b), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1206 } \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1207 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1208 } \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1209 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1210 }
f7c82a60 Vladimir Zapolskiy 2015-12-06 1211
f7c82a60 Vladimir Zapolskiy 2015-12-06 1212 #define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1213 [CLK_PREFIX(_idx)] = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1214 .type = CLK_COMPOSITE, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1215 { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1216 .hw1 = { \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1217 .mux = (CLK_PREFIX(_mux) == LPC32XX_CLK__NULL ? NULL : \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1218 &clk_hw_proto[CLK_PREFIX(_mux)].hw0), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1219 .div = (CLK_PREFIX(_div) == LPC32XX_CLK__NULL ? NULL : \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1220 &clk_hw_proto[CLK_PREFIX(_div)].hw0), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1221 .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\
f7c82a60 Vladimir Zapolskiy 2015-12-06 1222 &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1223 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1224 }, \
f7c82a60 Vladimir Zapolskiy 2015-12-06 1225 }
f7c82a60 Vladimir Zapolskiy 2015-12-06 1226
f7c82a60 Vladimir Zapolskiy 2015-12-06 1227 static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = {
f7c82a60 Vladimir Zapolskiy 2015-12-06 @1228 LPC32XX_DEFINE_FIXED(RTC, 32768, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1229 LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1230 LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1231 LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1232 LPC32XX_DEFINE_GATE(OSC, OSC_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1233 LPC32XX_DEFINE_GATE(USB, USB_CTRL, 18, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1234
f7c82a60 Vladimir Zapolskiy 2015-12-06 1235 LPC32XX_DEFINE_DIV(HCLK_DIV_PERIPH, HCLKDIV_CTRL, 2, 5, NULL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1236 CLK_DIVIDER_READ_ONLY),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1237 LPC32XX_DEFINE_DIV(HCLK_DIV, HCLKDIV_CTRL, 0, 2, clk_hclk_div_table,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1238 CLK_DIVIDER_READ_ONLY),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1239
f7c82a60 Vladimir Zapolskiy 2015-12-06 1240 /* Register 3 read-only muxes with a single control PWR_CTRL[2] */
f7c82a60 Vladimir Zapolskiy 2015-12-06 1241 LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1242 CLK_MUX_READ_ONLY),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1243 LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1244 CLK_MUX_READ_ONLY),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1245 LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1246 CLK_MUX_READ_ONLY),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1247 /* Register 2 read-only muxes with a single control PWR_CTRL[10] */
f7c82a60 Vladimir Zapolskiy 2015-12-06 1248 LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1249 CLK_MUX_READ_ONLY),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1250 LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1251 CLK_MUX_READ_ONLY),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1252
f7c82a60 Vladimir Zapolskiy 2015-12-06 1253 /* 3 always on gates with a single control PWR_CTRL[0] same as OSC */
f7c82a60 Vladimir Zapolskiy 2015-12-06 1254 LPC32XX_DEFINE_GATE(PERIPH, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1255 LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1256 LPC32XX_DEFINE_GATE(ARM, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1257
f7c82a60 Vladimir Zapolskiy 2015-12-06 1258 LPC32XX_DEFINE_GATE(ARM_VFP, DEBUG_CTRL, 4, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1259 LPC32XX_DEFINE_GATE(DMA, DMA_CLK_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1260 LPC32XX_DEFINE_CLK(DDRAM, HCLKDIV_CTRL, 0x0, BIT(8) | BIT(7),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1261 0x0, BIT(8) | BIT(7), 0x0, BIT(1) | BIT(0), clk_ddram_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1262
f7c82a60 Vladimir Zapolskiy 2015-12-06 1263 LPC32XX_DEFINE_GATE(TIMER0, TIMCLK_CTRL1, 2, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1264 LPC32XX_DEFINE_GATE(TIMER1, TIMCLK_CTRL1, 3, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1265 LPC32XX_DEFINE_GATE(TIMER2, TIMCLK_CTRL1, 4, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1266 LPC32XX_DEFINE_GATE(TIMER3, TIMCLK_CTRL1, 5, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1267 LPC32XX_DEFINE_GATE(TIMER4, TIMCLK_CTRL1, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1268 LPC32XX_DEFINE_GATE(TIMER5, TIMCLK_CTRL1, 1, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1269
f7c82a60 Vladimir Zapolskiy 2015-12-06 1270 LPC32XX_DEFINE_GATE(SSP0, SSP_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1271 LPC32XX_DEFINE_GATE(SSP1, SSP_CTRL, 1, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1272 LPC32XX_DEFINE_GATE(SPI1, SPI_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1273 LPC32XX_DEFINE_GATE(SPI2, SPI_CTRL, 4, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1274 LPC32XX_DEFINE_GATE(I2S0, I2S_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1275 LPC32XX_DEFINE_GATE(I2S1, I2S_CTRL, 1, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1276 LPC32XX_DEFINE_GATE(I2C1, I2CCLK_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1277 LPC32XX_DEFINE_GATE(I2C2, I2CCLK_CTRL, 1, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1278 LPC32XX_DEFINE_GATE(WDOG, TIMCLK_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1279 LPC32XX_DEFINE_GATE(HSTIMER, TIMCLK_CTRL, 1, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1280
f7c82a60 Vladimir Zapolskiy 2015-12-06 1281 LPC32XX_DEFINE_GATE(KEY, KEYCLK_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1282 LPC32XX_DEFINE_GATE(MCPWM, TIMCLK_CTRL1, 6, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1283
f7c82a60 Vladimir Zapolskiy 2015-12-06 1284 LPC32XX_DEFINE_MUX(PWM1_MUX, PWMCLK_CTRL, 1, 0x1, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1285 LPC32XX_DEFINE_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL,
f84d42a9 Vladimir Zapolskiy 2016-10-07 1286 CLK_DIVIDER_ONE_BASED),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1287 LPC32XX_DEFINE_GATE(PWM1_GATE, PWMCLK_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1288 LPC32XX_DEFINE_COMPOSITE(PWM1, PWM1_MUX, PWM1_DIV, PWM1_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1289
f7c82a60 Vladimir Zapolskiy 2015-12-06 1290 LPC32XX_DEFINE_MUX(PWM2_MUX, PWMCLK_CTRL, 3, 0x1, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1291 LPC32XX_DEFINE_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL,
f84d42a9 Vladimir Zapolskiy 2016-10-07 1292 CLK_DIVIDER_ONE_BASED),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1293 LPC32XX_DEFINE_GATE(PWM2_GATE, PWMCLK_CTRL, 2, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1294 LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1295
f7c82a60 Vladimir Zapolskiy 2015-12-06 1296 LPC32XX_DEFINE_MUX(UART3_MUX, UART3_CLK_CTRL, 16, 0x1, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1297 LPC32XX_DEFINE_CLK(UART3_DIV, UART3_CLK_CTRL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1298 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1299 LPC32XX_DEFINE_GATE(UART3_GATE, UART_CLK_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1300 LPC32XX_DEFINE_COMPOSITE(UART3, UART3_MUX, UART3_DIV, UART3_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1301
f7c82a60 Vladimir Zapolskiy 2015-12-06 1302 LPC32XX_DEFINE_MUX(UART4_MUX, UART4_CLK_CTRL, 16, 0x1, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1303 LPC32XX_DEFINE_CLK(UART4_DIV, UART4_CLK_CTRL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1304 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1305 LPC32XX_DEFINE_GATE(UART4_GATE, UART_CLK_CTRL, 1, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1306 LPC32XX_DEFINE_COMPOSITE(UART4, UART4_MUX, UART4_DIV, UART4_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1307
f7c82a60 Vladimir Zapolskiy 2015-12-06 1308 LPC32XX_DEFINE_MUX(UART5_MUX, UART5_CLK_CTRL, 16, 0x1, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1309 LPC32XX_DEFINE_CLK(UART5_DIV, UART5_CLK_CTRL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1310 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1311 LPC32XX_DEFINE_GATE(UART5_GATE, UART_CLK_CTRL, 2, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1312 LPC32XX_DEFINE_COMPOSITE(UART5, UART5_MUX, UART5_DIV, UART5_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1313
f7c82a60 Vladimir Zapolskiy 2015-12-06 1314 LPC32XX_DEFINE_MUX(UART6_MUX, UART6_CLK_CTRL, 16, 0x1, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1315 LPC32XX_DEFINE_CLK(UART6_DIV, UART6_CLK_CTRL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1316 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1317 LPC32XX_DEFINE_GATE(UART6_GATE, UART_CLK_CTRL, 3, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1318 LPC32XX_DEFINE_COMPOSITE(UART6, UART6_MUX, UART6_DIV, UART6_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1319
f7c82a60 Vladimir Zapolskiy 2015-12-06 1320 LPC32XX_DEFINE_CLK(IRDA, IRDA_CLK_CTRL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1321 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1322
f7c82a60 Vladimir Zapolskiy 2015-12-06 1323 LPC32XX_DEFINE_MUX(TEST1_MUX, TEST_CLK_CTRL, 5, 0x3,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1324 test1_mux_table, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1325 LPC32XX_DEFINE_GATE(TEST1_GATE, TEST_CLK_CTRL, 4, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1326 LPC32XX_DEFINE_COMPOSITE(TEST1, TEST1_MUX, _NULL, TEST1_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1327
f7c82a60 Vladimir Zapolskiy 2015-12-06 1328 LPC32XX_DEFINE_MUX(TEST2_MUX, TEST_CLK_CTRL, 1, 0x7,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1329 test2_mux_table, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1330 LPC32XX_DEFINE_GATE(TEST2_GATE, TEST_CLK_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1331 LPC32XX_DEFINE_COMPOSITE(TEST2, TEST2_MUX, _NULL, TEST2_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1332
f7c82a60 Vladimir Zapolskiy 2015-12-06 1333 LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1334
f7c82a60 Vladimir Zapolskiy 2015-12-06 1335 LPC32XX_DEFINE_DIV(USB_DIV_DIV, USB_DIV, 0, 4, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1336 LPC32XX_DEFINE_GATE(USB_DIV_GATE, USB_CTRL, 17, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1337 LPC32XX_DEFINE_COMPOSITE(USB_DIV, _NULL, USB_DIV_DIV, USB_DIV_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1338
f84d42a9 Vladimir Zapolskiy 2016-10-07 1339 LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1340 LPC32XX_DEFINE_CLK(SD_GATE, MS_CTRL, BIT(5) | BIT(9), BIT(5) | BIT(9),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1341 0x0, BIT(5) | BIT(9), 0x0, 0x0, clk_mask_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1342 LPC32XX_DEFINE_COMPOSITE(SD, _NULL, SD_DIV, SD_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1343
f7c82a60 Vladimir Zapolskiy 2015-12-06 1344 LPC32XX_DEFINE_DIV(LCD_DIV, LCDCLK_CTRL, 0, 5, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1345 LPC32XX_DEFINE_GATE(LCD_GATE, LCDCLK_CTRL, 5, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1346 LPC32XX_DEFINE_COMPOSITE(LCD, _NULL, LCD_DIV, LCD_GATE),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1347
f7c82a60 Vladimir Zapolskiy 2015-12-06 1348 LPC32XX_DEFINE_CLK(MAC, MACCLK_CTRL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1349 BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1350 BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1351 0x0, 0x0, clk_mask_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1352 LPC32XX_DEFINE_CLK(SLC, FLASHCLK_CTRL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1353 BIT(2) | BIT(0), BIT(2) | BIT(0), 0x0,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1354 BIT(0), BIT(1), BIT(2) | BIT(1), clk_mask_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1355 LPC32XX_DEFINE_CLK(MLC, FLASHCLK_CTRL,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1356 BIT(1), BIT(2) | BIT(1), 0x0, BIT(1),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1357 BIT(2) | BIT(0), BIT(2) | BIT(0), clk_mask_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1358 /*
f7c82a60 Vladimir Zapolskiy 2015-12-06 1359 * ADC/TS clock unfortunately cannot be registered as a composite one
f7c82a60 Vladimir Zapolskiy 2015-12-06 1360 * due to a different connection of gate, div and mux, e.g. gating it
f7c82a60 Vladimir Zapolskiy 2015-12-06 1361 * won't mean that the clock is off, if peripheral clock is its parent:
f7c82a60 Vladimir Zapolskiy 2015-12-06 1362 *
f7c82a60 Vladimir Zapolskiy 2015-12-06 1363 * rtc-->[gate]-->| |
f7c82a60 Vladimir Zapolskiy 2015-12-06 1364 * | mux |--> adc/ts
f7c82a60 Vladimir Zapolskiy 2015-12-06 1365 * pclk-->[div]-->| |
f7c82a60 Vladimir Zapolskiy 2015-12-06 1366 *
f7c82a60 Vladimir Zapolskiy 2015-12-06 1367 * Constraints:
f7c82a60 Vladimir Zapolskiy 2015-12-06 1368 * ADC --- resulting clock must be <= 4.5 MHz
f7c82a60 Vladimir Zapolskiy 2015-12-06 1369 * TS --- resulting clock must be <= 400 KHz
f7c82a60 Vladimir Zapolskiy 2015-12-06 1370 */
f7c82a60 Vladimir Zapolskiy 2015-12-06 1371 LPC32XX_DEFINE_DIV(ADC_DIV, ADCCLK_CTRL1, 0, 8, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1372 LPC32XX_DEFINE_GATE(ADC_RTC, ADCCLK_CTRL, 0, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1373 LPC32XX_DEFINE_MUX(ADC, ADCCLK_CTRL1, 8, 0x1, NULL, 0),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1374
f7c82a60 Vladimir Zapolskiy 2015-12-06 1375 /* USB controller clocks */
f7c82a60 Vladimir Zapolskiy 2015-12-06 1376 LPC32XX_DEFINE_USB(USB_AHB,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1377 BIT(24), 0x0, BIT(24), BIT(4), 0, clk_usb_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1378 LPC32XX_DEFINE_USB(USB_OTG,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1379 0x0, 0x0, 0x0, BIT(3), 0, clk_usb_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1380 LPC32XX_DEFINE_USB(USB_I2C,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1381 0x0, BIT(23), BIT(23), BIT(2), 0, clk_usb_i2c_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1382 LPC32XX_DEFINE_USB(USB_DEV,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1383 BIT(22), 0x0, BIT(22), BIT(1), BIT(0), clk_usb_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1384 LPC32XX_DEFINE_USB(USB_HOST,
f7c82a60 Vladimir Zapolskiy 2015-12-06 1385 BIT(21), 0x0, BIT(21), BIT(0), BIT(1), clk_usb_ops),
f7c82a60 Vladimir Zapolskiy 2015-12-06 1386 };
f7c82a60 Vladimir Zapolskiy 2015-12-06 1387
:::::: The code at line 1094 was first introduced by commit
:::::: f7c82a60ba26c2f003662bcb2cff131021c1e828 clk: lpc32xx: add common clock framework driver
:::::: TO: Vladimir Zapolskiy <vz@mleia.com>
:::::: CC: Michael Turquette <mturquette@baylibre.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [clk:clk-doc 4/5] drivers/clk/nxp/clk-lpc32xx.c:1094:5: error: 'struct clk_fixed_rate' has no member named 'flags'
2018-12-14 9:31 [clk:clk-doc 4/5] drivers/clk/nxp/clk-lpc32xx.c:1094:5: error: 'struct clk_fixed_rate' has no member named 'flags' kbuild test robot
@ 2018-12-14 17:20 ` Stephen Boyd
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2018-12-14 17:20 UTC (permalink / raw)
To: kbuild test robot; +Cc: kbuild-all, linux-clk, linux-arm-kernel
Quoting kbuild test robot (2018-12-14 01:31:14)
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-doc
> head: 9369ad9e3dd4ec5a5d189825a49c1b76bb733571
> commit: 9274efae17dcaf8bb2f8abf802ea254ae8810794 [4/5] clk: Remove 'flags' member of struct clk_fixed_rate
> config: arm-lpc32xx_defconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
> reproduce:
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> git checkout 9274efae17dcaf8bb2f8abf802ea254ae8810794
> # save the attached .config to linux build tree
> GCC_VERSION=7.2.0 make.cross ARCH=arm
>
> All error/warnings (new ones prefixed by >>):
>
> >> drivers/clk/nxp/clk-lpc32xx.c:1094:5: error: 'struct clk_fixed_rate' has no member named 'flags'
> .flags = (_flags), \
> ^
> >> drivers/clk/nxp/clk-lpc32xx.c:1228:2: note: in expansion of macro 'LPC32XX_DEFINE_FIXED'
> LPC32XX_DEFINE_FIXED(RTC, 32768, 0),
> ^~~~~~~~~~~~~~~~~~~~
> drivers/clk/nxp/clk-lpc32xx.c: In function 'lpc32xx_clk_register':
> drivers/clk/nxp/clk-lpc32xx.c:1471:21: error: 'struct clk_fixed_rate' has no member named 'flags'
> parents[0], fixed->flags, fixed->fixed_rate);
> ^~
Ah thanks. Good news is that it's an easy fix.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2018-12-14 9:31 [clk:clk-doc 4/5] drivers/clk/nxp/clk-lpc32xx.c:1094:5: error: 'struct clk_fixed_rate' has no member named 'flags' kbuild test robot
2018-12-14 17:20 ` Stephen Boyd
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