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From: Stephen Boyd <sboyd@kernel.org>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Nicolas Boichat <drinkcat@chromium.org>,
	Rob Herring <robh@kernel.org>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Weiyi Lu <weiyi.lu@mediatek.com>
Cc: James Liao <jamesjj.liao@mediatek.com>,
	Fan Chen <fan.chen@mediatek.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-clk@vger.kernel.org, srv_heupstream@mediatek.com,
	stable@vger.kernel.org, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: Re: [PATCH v3 12/12] clk: mediatek: Allow changing PLL rate when it is off
Date: Fri, 14 Dec 2018 14:01:23 -0800
Message-ID: <154482488309.19322.1300826887966936368@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20181210073240.32278-14-weiyi.lu@mediatek.com>

Quoting Weiyi Lu (2018-12-09 23:32:40)
> From: James Liao <jamesjj.liao@mediatek.com>
> 
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are off.
> 
> On MT8173 for example, ARMPLL's enable bit can be controlled by
> other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> set ARMPLL's enable bit as 0. In this case, SW may want and can
> still change ARMPLL's rate by changing its pcw and postdiv settings.
> But without this patch, new pcw setting will not be applied because
> its enable bit is 0.
> 
> (am from https://patchwork.kernel.org/patch/9411983/)

Remove this.

> 
> Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
> Acked-by: Michael Turquette <mturuqette@baylibre.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>

  reply index

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-10  7:32 [PATCH v3 00/11] Mediatek MT8183 clock and scpsys support Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 00/12] " Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 01/12] clk: mediatek: fixup: Disable tuner_en before change PLL rate Weiyi Lu
2018-12-14 21:57   ` Stephen Boyd
2019-02-01  8:21     ` Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 02/12] clk: mediatek: add new clkmux register API Weiyi Lu
2018-12-10 12:30   ` Nicolas Boichat
2019-02-01  8:22     ` Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu
2018-12-14 22:02   ` Stephen Boyd
2019-02-01  8:22     ` Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 04/12] soc: mediatek: add new flow for mtcmos power Weiyi Lu
2018-12-10 12:52   ` Nicolas Boichat
2018-12-10  7:32 ` [PATCH v3 05/12] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu
2018-12-14 21:57   ` Stephen Boyd
2018-12-10  7:32 ` [PATCH v3 06/12] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 07/12] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support Weiyi Lu
2018-12-11  1:00   ` Nicolas Boichat
2019-02-01  8:22     ` Weiyi Lu
2018-12-14 21:59   ` Stephen Boyd
2019-02-01  8:22     ` Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 09/12] dt-bindings: soc: fix typo of MT8173 power dt-bindings Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 10/12] dt-bindings: soc: Add MT8183 " Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 11/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 12/12] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu
2018-12-14 22:01   ` Stephen Boyd [this message]
2019-02-01  8:22     ` Weiyi Lu

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