From: Chunhui Dai <chunhui.dai@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: --to=Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, CK Hu <ck.hu@mediatek.com>,
<wangyan.wang@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
Sean Wang <sean.wang@mediatek.com>,
Ryder Lee <ryder.lee@mediatek.com>,
Colin Ian King <colin.king@canonical.com>,
<linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<dri-devel@lists.freedesktop.org>, <srv_heupstream@mediatek.com>,
<bibby.hsieh@mediatek.com>, <jamesjj.liao@mediatek.com>,
<jitao.shi@mediatek.com>
Subject: Re: [PATCH 4/9] drm/mediatek: fix the rate and divder of hdmi phy for MT2701
Date: Thu, 17 Jan 2019 16:34:35 +0800 [thread overview]
Message-ID: <1547714075.4664.1.camel@mszsdaap41> (raw)
In-Reply-To: <a3e37dde-2bab-be02-27ec-d15784bd560b@gmail.com>
On Wed, 2019-01-09 at 17:54 +0100, Matthias Brugger wrote:
>
> On 04/01/2019 08:03, chunhui dai wrote:
> > fix the rate and divder of hdmi phy for MT2701.
>
> This is a bug? Then we would need a fixes tag.
yes, we would add the tag in V2.
> Otherwise you should explain in the commit, that you need to change the
> calculation due to previous commits.
>
> Regards,
> Matthias
>
> >
> > Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > index a28a32d..10b6235 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > @@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> >
> > if (rate <= 64000000)
> > pos_div = 3;
> > - else if (rate <= 12800000)
> > - pos_div = 1;
> > + else if (rate <= 128000000)
> > + pos_div = 2;
> > else
> > pos_div = 1;
> >
> >
next prev parent reply other threads:[~2019-01-17 8:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1546585439-30455-1-git-send-email-chunhui.dai@mediatek.com>
[not found] ` <1546585439-30455-5-git-send-email-chunhui.dai@mediatek.com>
2019-01-09 16:54 ` [PATCH 4/9] drm/mediatek: fix the rate and divder of hdmi phy for MT2701 Matthias Brugger
2019-01-17 8:34 ` Chunhui Dai [this message]
[not found] ` <1546585439-30455-2-git-send-email-chunhui.dai@mediatek.com>
2019-01-09 16:55 ` [PATCH 1/9] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware Matthias Brugger
2019-01-10 1:47 ` CK Hu
[not found] ` <1546585439-30455-10-git-send-email-chunhui.dai@mediatek.com>
2019-01-09 16:58 ` [PATCH 9/9] drm/mediatek: add dpi dual edge support Matthias Brugger
2019-01-22 7:03 ` Jitao Shi
[not found] ` <6021c8950c3146bb941ed1355391106d@mtkmbs01n1.mediatek.inc>
2019-01-22 6:41 ` Jitao Shi
[not found] ` <1546585439-30455-3-git-send-email-chunhui.dai@mediatek.com>
2019-01-10 8:28 ` [PATCH 2/9] drm/mediatek: move the setting of fixed divider CK Hu
2019-01-17 8:49 ` Chunhui Dai
[not found] ` <1546585439-30455-4-git-send-email-chunhui.dai@mediatek.com>
2019-01-16 6:37 ` [PATCH 3/9] drm/mediatek: using different flags of clk for HDMI phy CK Hu
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