From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D026C282C8 for ; Mon, 28 Jan 2019 08:52:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1960520880 for ; Mon, 28 Jan 2019 08:52:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726415AbfA1Iwd (ORCPT ); Mon, 28 Jan 2019 03:52:33 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:50568 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726556AbfA1Iwd (ORCPT ); Mon, 28 Jan 2019 03:52:33 -0500 X-UUID: 5856478060624a52b168cce05c68252f-20190128 X-UUID: 5856478060624a52b168cce05c68252f-20190128 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1259753091; Mon, 28 Jan 2019 16:52:21 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 28 Jan 2019 16:52:20 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 28 Jan 2019 16:52:20 +0800 Message-ID: <1548665540.10401.0.camel@mtksdaap41> Subject: Re: [PATCH V3,4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701 From: CK Hu To: Wangyan Wang CC: Michael Turquette , Matthias Brugger , Stephen Boyd , Philipp Zabel , David Airlie , Sean Wang , Ryder Lee , "Colin Ian King" , , , , , , , , , chunhui dai Date: Mon, 28 Jan 2019 16:52:20 +0800 In-Reply-To: <20190125040205.5451-5-wangyan.wang@mediatek.com> References: <20190125040205.5451-1-wangyan.wang@mediatek.com> <20190125040205.5451-5-wangyan.wang@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Fri, 2019-01-25 at 12:02 +0800, Wangyan Wang wrote: > From: chunhui dai > > Due to a clerical error,there is one zero less for 12800000. > Fix it for 128000000. > Reviewed-by: CK Hu > Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623") > Signed-off-by: chunhui dai > Signed-off-by: wangyan wang > --- > drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > index 43bc058d5528..88dd9e812ca0 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > @@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > > if (rate <= 64000000) > pos_div = 3; > - else if (rate <= 12800000) > - pos_div = 1; > + else if (rate <= 128000000) > + pos_div = 2; > else > pos_div = 1; >