From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1CAEC282C8 for ; Mon, 28 Jan 2019 09:28:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB23720880 for ; Mon, 28 Jan 2019 09:28:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726590AbfA1J2G (ORCPT ); Mon, 28 Jan 2019 04:28:06 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:42538 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726369AbfA1J2G (ORCPT ); Mon, 28 Jan 2019 04:28:06 -0500 X-UUID: 863d28cdc2af469cb5d87e6ffaa7e7bc-20190128 X-UUID: 863d28cdc2af469cb5d87e6ffaa7e7bc-20190128 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1465889627; Mon, 28 Jan 2019 17:27:58 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 28 Jan 2019 17:27:55 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 28 Jan 2019 17:27:56 +0800 Message-ID: <1548667676.10401.17.camel@mtksdaap41> Subject: Re: [PATCH V3,0/8] make mt7623 clock of HDMI stable From: CK Hu To: Wangyan Wang CC: Michael Turquette , Matthias Brugger , Stephen Boyd , Philipp Zabel , David Airlie , Sean Wang , Ryder Lee , "Colin Ian King" , , , , , , , , Date: Mon, 28 Jan 2019 17:27:56 +0800 In-Reply-To: <20190125040205.5451-1-wangyan.wang@mediatek.com> References: <20190125040205.5451-1-wangyan.wang@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 13C157F7FD1C1FE845342FFC67C91DCB7AFB3126B8FEBB6A239CD4F9D45860B62000:8 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi, Wangyan: How do you prove that this series would make mt7623 HDMI clock more stable? By experience result? I would like to prove it by the source code. Does 'stable' means that hardware could generate the frequency most close to the target frequency? If it does, I think you could compare the frequency generated by original code and applying this series for all the usually-used frequency. I also need you to show the clock tree and all setting of each divider so we could review that is this series good enough. Also, describe these in cover latter. You have mail to dri-devel [1] and linux-mediatek [2], but these patches does not show in web site. Maybe your mail is not plain text, please fix this and resend patches. [1] https://lists.freedesktop.org/archives/dri-devel/ [2] http://lists.infradead.org/pipermail/linux-mediatek/ Regards, CK On Fri, 2019-01-25 at 12:01 +0800, Wangyan Wang wrote: > V3 adopt maintainer's suggestion. > Here is the change list between V2 & V3: > 1. add "Signed-off-by: wangyan wang " > in commit message > > 2. add modify description in patch > "drm/mediatek: fix the rate and divder ..." > > chunhui dai (8): > drm/mediatek: recalculate hdmi phy clock of MT2701 by querying > hardware > drm/mediatek: move the setting of fixed divider > drm/mediatek: using different flags of clk for HDMI phy > drm/mediatek: fix the rate and divder of hdmi phy for MT2701 > clk: mediatek: add MUX_GATE_FLAGS_2 > clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel > drm/mediatek: using new factor for tvdpll in MT2701 > drm/mediatek: fix the rate of parent for hdmi phy in MT2701 > > drivers/clk/mediatek/clk-mt2701.c | 4 +- > drivers/clk/mediatek/clk-mtk.c | 2 +- > drivers/clk/mediatek/clk-mtk.h | 20 +++++-- > drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +-- > drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 34 +++-------- > drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 7 +-- > .../gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 56 +++++++++++++++++-- > .../gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 ++++++++ > 8 files changed, 102 insertions(+), 52 deletions(-) >