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Subject: Re: [PATCH] clk: ingenic: jz4740: Fix gating of UDC clock
References: <20190125153436.13517-1-paul@crapouillou.net> <154844250661.136743.15303302299846585853@swboyd.mtv.corp.google.com> <1548444298.1804.2@crapouillou.net>
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Cc:     Michael Turquette <mturquette@baylibre.com>,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
From:   Stephen Boyd <sboyd@kernel.org>
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Message-ID: <154878559039.136743.10189442694979275708@swboyd.mtv.corp.google.com>
To:     Paul Cercueil <paul@crapouillou.net>
Date:   Tue, 29 Jan 2019 10:13:10 -0800
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Quoting Paul Cercueil (2019-01-25 11:24:58)
> Hi,
>=20
>=20
> On Fri, Jan 25, 2019 at 3:55 PM, Stephen Boyd <sboyd@kernel.org> wrote:
> > Quoting Paul Cercueil (2019-01-25 07:34:36)
> >>  The UDC clock is gated when the bit is cleared, not when it is set.
> >>=20
> >>  Signed-off-by: Paul Cercueil <paul@crapouillou.net=20
> >> <mailto:paul@crapouillou.net>>
> >>  Tested-by: Artur Rojek <contact@artur-rojek.eu=20
> >> <mailto:contact@artur-rojek.eu>>
> >>  ---
> >=20
> > Any Fixes tag for this?
> >=20
>=20
> Fixes: 2b555a4b9cae
>=20
> Should I resend?
>=20

No need to resend. Is this fixing something that's broken in the v5.0-rc
series? I'm trying to understand if this is a critical fix or a
non-critical fix that can bake until the next release cycle.