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Wed, 13 Feb 2019 20:54:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hHkYAJ4t/SYAqFMpMYi9fxYycrMV51Pn/LP5JnRobNs=; b=rJwFqxdB81iPZ2hhBT0EwrgGJX8k8yY3BfqdqHRyjRRoPAM5KMG3MW+ISDwAgUov98v6pJo+8hBjpU8s6wGdBylesmakNwiBmq0BM59nTyVAv8+0EUXvJdAb1B8BkbNbOwg/PLD8jgct4I84wANt7wj+KDjKVnsQCn4xAxYgF2w= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3850.eurprd04.prod.outlook.com (52.134.65.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1601.22; Thu, 14 Feb 2019 01:54:08 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::14e8:6d2e:fe21:4fd5]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::14e8:6d2e:fe21:4fd5%3]) with mapi id 15.20.1601.023; Thu, 14 Feb 2019 01:54:08 +0000 From: Anson Huang To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , Aisheng Dong , Daniel Baluta , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "viresh.kumar@linaro.org" CC: dl-linux-imx Subject: [PATCH V4 2/2] clk: imx: scu: add cpu frequency scaling support Thread-Topic: [PATCH V4 2/2] clk: imx: scu: add cpu frequency scaling support Thread-Index: AQHUxAgs8uuWj5mH40eZScOWTh4APw== Date: Thu, 14 Feb 2019 01:54:08 +0000 Message-ID: <1550108915-574-2-git-send-email-Anson.Huang@nxp.com> References: <1550108915-574-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1550108915-574-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0163.apcprd02.prod.outlook.com (2603:1096:201:1f::23) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: w0AT72hred62x86/+U4KGgkNJwQD530hOMlYCiZkbz57GhR6G6FfUjWjanvwyV8yY1zosNka5YhGOan3XjpGilBxoi6Bbq70s9VD2LOyGjGijKT8961TDpjCRbe1RcRWf/n8YGc1zFrwekI0lM1UoxoBVRwPzvFs9LN5aWFg6wRfOF6xKImWtJYWGIfIUxFNgjzCRxXlFpmWoFQd00lW0trpbnGaYWLhoNvb1uq9MCe5gK7V0tNL/cmNcENmEah+vYQV2Jd4GzUPvLPG/HzVIH1nEQ6iy4f5IoMF44rjVd45BEa5TP3idEe3zvaMCUmDlfnrru1BwaUjqeuF2M4/8i/zX8WkMitWLoL6rZxqANekCMF6R2BSZsn6BRX5YLiFCkIn0LlN57rsXF1JQbHn4uHv0QQKVg3wmy+Tyw7XtJg= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e606a76c-6eae-401f-ef0c-08d6921f4ed8 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Feb 2019 01:54:01.7308 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3850 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On NXP's i.MX SoCs with system controller inside, CPU frequency scaling can ONLY be done by system controller firmware, and it can ONLY be requested from secure mode, so Linux kernel has to call ARM SMC to trap to ARM-Trusted-Firmware to request system controller firmware to do CPU frequency scaling. This patch adds i.MX system controller CPU frequency scaling support, it reuses cpufreq-dt driver and implement the CPU frequency scaling inside SCU clock driver. Signed-off-by: Anson Huang --- Changes since V3: - use different clk ops for CPU clock to avoid runtime check in clk= _set_rate; - use rsrc_id to determine whether it is CPU frequency change and a= lso to get cluster ID for SMC call. --- drivers/clk/imx/clk-scu.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 7ccf7ed..c234a6e 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -4,12 +4,17 @@ * Dong Aisheng */ =20 +#include +#include #include #include #include =20 #include "clk-scu.h" =20 +#define IMX_SIP_CPUFREQ 0xC2000001 +#define IMX_SIP_SET_CPUFREQ 0x00 + static struct imx_sc_ipc *ccm_ipc_handle; =20 /* @@ -145,6 +150,23 @@ static long clk_scu_round_rate(struct clk_hw *hw, unsi= gned long rate, return rate; } =20 +static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_scu *clk =3D to_clk_scu(hw); + struct arm_smccc_res res; + unsigned long cluster_id; + + if (clk->rsrc_id =3D=3D IMX_SC_R_A35) + cluster_id =3D 0; + + /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */ + arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ, + cluster_id, rate, 0, 0, 0, 0, &res); + + return 0; +} + /* * clk_scu_set_rate - Set rate for a SCU clock * @hw: clock to change rate for @@ -232,6 +254,14 @@ static const struct clk_ops clk_scu_ops =3D { .unprepare =3D clk_scu_unprepare, }; =20 +static const struct clk_ops clk_scu_cpu_ops =3D { + .recalc_rate =3D clk_scu_recalc_rate, + .round_rate =3D clk_scu_round_rate, + .set_rate =3D clk_scu_atf_set_cpu_rate, + .prepare =3D clk_scu_prepare, + .unprepare =3D clk_scu_unprepare, +}; + struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type) { struct clk_init_data init; @@ -247,7 +277,10 @@ struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_= id, u8 clk_type) clk->clk_type =3D clk_type; =20 init.name =3D name; - init.ops =3D &clk_scu_ops; + if (rsrc_id =3D=3D IMX_SC_R_A35) + init.ops =3D &clk_scu_cpu_ops; + else + init.ops =3D &clk_scu_ops; init.num_parents =3D 0; /* * Note on MX8, the clocks are tightly coupled with power domain --=20 2.7.4