From: Stephen Boyd <sboyd@kernel.org>
To: Abel Vesa <abel.vesa@nxp.com>,
Aisheng Dong <aisheng.dong@nxp.com>,
Anson Huang <anson.huang@nxp.com>,
Fabio Estevam <fabio.estevam@nxp.com>,
Fabio Estevam <festevam@gmail.com>, Jacky Bai <ping.bai@nxp.com>,
Lucas Stach <l.stach@pengutronix.de>,
Sascha Hauer <kernel@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>
Cc: dl-linux-imx <linux-imx@nxp.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Abel Vesa <abel.vesa@nxp.com>
Subject: Re: [PATCH v2] clk: imx: Refactor entire sccg pll clk
Date: Tue, 26 Feb 2019 10:09:22 -0800 [thread overview]
Message-ID: <155120456259.260864.486515032059106989@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1550855235-31528-1-git-send-email-abel.vesa@nxp.com>
Quoting Abel Vesa (2019-02-22 09:07:32)
> Make the entire combination of plls to be one single clock. The parents used
> for bypasses are specified each as an index in the parents list.
> The determine_rate does a lookup throughout all the possible combinations
> for all the divs and returns the best possible 'setup' which in turn is used
> by set_rate later to set up all the divs and bypasses.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Tested-by: Lucas Stach <l.stach@pengutronix.de>
> Acked-by: Lucas Stach <l.stach@pengutronix.de>
> ---
Applied to clk-next
prev parent reply other threads:[~2019-02-26 18:09 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-22 17:07 [PATCH v2] clk: imx: Refactor entire sccg pll clk Abel Vesa
2019-02-22 17:46 ` Stephen Boyd
2019-02-23 10:58 ` Abel Vesa
2019-02-25 17:23 ` Stephen Boyd
2019-02-26 11:18 ` Aisheng Dong
2019-02-26 11:23 ` Abel Vesa
2019-02-26 11:45 ` Aisheng Dong
2019-02-26 12:03 ` Abel Vesa
2019-02-26 18:09 ` Stephen Boyd [this message]
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