From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77289C43381 for ; Wed, 6 Mar 2019 10:07:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 518F620657 for ; Wed, 6 Mar 2019 10:07:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729884AbfCFKHr (ORCPT ); Wed, 6 Mar 2019 05:07:47 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:32495 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729848AbfCFKHq (ORCPT ); Wed, 6 Mar 2019 05:07:46 -0500 X-UUID: c025d4ebebe940c79edfb26b25ee24bb-20190306 X-UUID: c025d4ebebe940c79edfb26b25ee24bb-20190306 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1761748286; Wed, 06 Mar 2019 18:07:36 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 6 Mar 2019 18:07:34 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 6 Mar 2019 18:07:34 +0800 Message-ID: <1551866854.1001.6.camel@mtksdaap41> Subject: Re: [PATCH v6 1/8] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware From: CK Hu To: wangyan wang CC: Michael Turquette , Stephen Boyd , Matthias Brugger , "Philipp Zabel" , David Airlie , "Daniel Vetter" , chunhui dai , "Colin Ian King" , Sean Wang , "Ryder Lee" , , , , , , Date: Wed, 6 Mar 2019 18:07:34 +0800 In-Reply-To: <20190225020912.29120-2-wangyan.wang@mediatek.com> References: <20190225020912.29120-1-wangyan.wang@mediatek.com> <20190225020912.29120-2-wangyan.wang@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi, Wangyan: On Mon, 2019-02-25 at 10:09 +0800, wangyan wang wrote: > From: chunhui dai > > Recalculate the rate of this clock, by querying hardware. > > Signed-off-by: chunhui dai > Signed-off-by: wangyan wang > --- > drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 7 ++---- > drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 3 +-- > drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 35 ++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 8 ++++++ > 4 files changed, 46 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c > index 4ef9c57ffd44..13c5e65b9ead 100644 > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c > @@ -29,12 +29,9 @@ long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, > return rate; > } > > -unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, > - unsigned long parent_rate) > +u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset) > { > - struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); > - > - return hdmi_phy->pll_rate; > + return readl(hdmi_phy->regs + offset); > } > > void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h > index f39b1fc66612..fdad8b17a915 100644 > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h > @@ -41,6 +41,7 @@ struct mtk_hdmi_phy { > unsigned int ibias_up; > }; > > +u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset); > void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, > u32 bits); > void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset, > @@ -50,8 +51,6 @@ void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset, > struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw); > long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, > unsigned long *parent_rate); > -unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, > - unsigned long parent_rate); > > extern struct platform_driver mtk_hdmi_phy_driver; > extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf; > diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > index fcc42dc6ea7f..b25c9dfc432a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c > @@ -153,6 +153,41 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > RG_HDMITX_DRV_IBIAS_MASK); > return 0; > } > +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); > + unsigned long out_rate, val; > + > + val = (mtk_hdmi_phy_read(hdmi_phy, HDMI_CON6) > + & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV; > + switch (val) { > + case 0x00: > + out_rate = parent_rate; > + break; > + case 0x01: > + out_rate = parent_rate / 2; > + break; > + default: > + out_rate = parent_rate / 4; > + break; > + } > + > + val = (mtk_hdmi_phy_read(hdmi_phy, HDMI_CON6) > + & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV; > + out_rate *= (val + 1) * 2; > + val = (mtk_hdmi_phy_read(hdmi_phy, HDMI_CON2) > + & RG_HDMITX_TX_POSDIV_MASK); > + > + out_rate >>= (val >> RG_HDMITX_TX_POSDIV); > + > + if (mtk_hdmi_phy_read(hdmi_phy, HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV) > + out_rate = out_rate / 5; > + All the register you read here is set in mtk_hdmi_pll_set_rate(), so I think you could determine the out_rate in mtk_hdmi_pll_set_rate(). Regards, CK > + hdmi_phy->pll_rate = out_rate; > + > + return hdmi_phy->pll_rate; > +} > > static const struct clk_ops mtk_hdmi_phy_pll_ops = { > .prepare = mtk_hdmi_pll_prepare, > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > index ed5916b27658..cb23c1e4692a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c > @@ -285,6 +285,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, > return 0; > } > > +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); > + > + return hdmi_phy->pll_rate; > +} > + > static const struct clk_ops mtk_hdmi_phy_pll_ops = { > .prepare = mtk_hdmi_pll_prepare, > .unprepare = mtk_hdmi_pll_unprepare,