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References: <20190417112420.3034-1-paul@crapouillou.net> <155562472561.15276.17918796624287416345@swboyd.mtv.corp.google.com> <1556571191.1721.0@crapouillou.net>
From:   Stephen Boyd <sboyd@kernel.org>
Subject: Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
To:     Paul Cercueil <paul@crapouillou.net>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        stable@vger.kernel.org
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Date:   Mon, 29 Apr 2019 15:59:19 -0700
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Quoting Paul Cercueil (2019-04-29 13:53:11)
> Hi Stephen,
>=20
> Le jeu. 18 avril 2019 =C3=A0 23:58, Stephen Boyd <sboyd@kernel.org> a=20
> =C3=A9crit :
> > Quoting Paul Cercueil (2019-04-17 04:24:20)
> >>  The pixel clock is directly connected to the output of the PLL, and=20
> >> not
> >>  to the /2 divider.
> >>=20
> >>  Cc: stable@vger.kernel.org
> >>  Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
> >>  Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> >>  ---
> >=20
> > Applied to clk-next
>=20
> Could you drop this patch?
>=20
> It turns out it is wrong and the pixel clock is really connected to the=20
> "pll half"
> clock. The real bug was elsewhere: the "pll half" clock does not report=20
> the correct
> rate. I will send a patch for this one later.
>=20

Ok. No problem.