From: Stefan Wahren <wahrenst@gmx.net>
To: Eric Anholt <eric@anholt.net>,
Florian Fainelli <f.fainelli@gmail.com>,
Ray Jui <rjui@broadcom.com>,
Scott Branden <sbranden@broadcom.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org, Stefan Wahren <wahrenst@gmx.net>
Subject: [PATCH 3/4] clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support
Date: Sun, 18 Aug 2019 18:23:43 +0200 [thread overview]
Message-ID: <1566145424-3186-4-git-send-email-wahrenst@gmx.net> (raw)
In-Reply-To: <1566145424-3186-1-git-send-email-wahrenst@gmx.net>
The new BCM2711 supports an additional clock for the emmc2 block.
So add a new compatible and register this clock only for BCM2711.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
---
drivers/clk/bcm/clk-bcm2835.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 21cd952..fdf672a 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -114,6 +114,8 @@
#define CM_AVEODIV 0x1bc
#define CM_EMMCCTL 0x1c0
#define CM_EMMCDIV 0x1c4
+#define CM_EMMC2CTL 0x1d0
+#define CM_EMMC2DIV 0x1d4
/* General bits for the CM_*CTL regs */
# define CM_ENABLE BIT(4)
@@ -290,7 +292,8 @@
#define BCM2835_MAX_FB_RATE 1750000000u
#define SOC_BCM2835 BIT(0)
-#define SOC_ALL (SOC_BCM2835)
+#define SOC_BCM2711 BIT(1)
+#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
/*
* Names of clocks used within the driver that need to be replaced
@@ -2003,6 +2006,16 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.frac_bits = 8,
.tcnt_mux = 39),
+ /* EMMC2 clock (only available for BCM2711) */
+ [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
+ SOC_BCM2711,
+ .name = "emmc2",
+ .ctl_reg = CM_EMMC2CTL,
+ .div_reg = CM_EMMC2DIV,
+ .int_bits = 4,
+ .frac_bits = 8,
+ .tcnt_mux = 42),
+
/* General purpose (GPIO) clocks */
[BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
SOC_ALL,
@@ -2238,8 +2251,13 @@ static const struct cprman_plat_data cprman_bcm2835_plat_data = {
.soc = SOC_BCM2835,
};
+static const struct cprman_plat_data cprman_bcm2711_plat_data = {
+ .soc = SOC_BCM2711,
+};
+
static const struct of_device_id bcm2835_clk_of_match[] = {
{ .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
+ { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
{}
};
MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
--
2.7.4
next prev parent reply other threads:[~2019-08-18 16:24 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-18 16:23 [PATCH 0/4] clk: bcm2835: Add bcm2711 support Stefan Wahren
2019-08-18 16:23 ` [PATCH 1/4] dt-bindings: bcm2835-cprman: " Stefan Wahren
2019-09-17 17:16 ` Stephen Boyd
2019-08-18 16:23 ` [PATCH 2/4] clk: bcm2835: Introduce SoC specific clock registration Stefan Wahren
2019-09-17 17:16 ` Stephen Boyd
2019-08-18 16:23 ` Stefan Wahren [this message]
2019-09-17 17:16 ` [PATCH 3/4] clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support Stephen Boyd
2019-08-18 16:23 ` [PATCH 4/4] clk: bcm2835: Mark PLLD_PER as CRITICAL Stefan Wahren
2019-09-17 17:16 ` Stephen Boyd
2019-08-26 18:16 ` [PATCH 0/4] clk: bcm2835: Add bcm2711 support Stefan Wahren
2019-09-04 18:17 ` Stefan Wahren
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