From: Mars Cheng <mars.cheng@mediatek.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Sean Wang <sean.wang@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
<devicetree@vger.kernel.org>, CC Hwang <cc.hwang@mediatek.com>,
<wsd_upstream@mediatek.com>, Loda Chou <loda.chou@mediatek.com>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
mtk01761 <wendell.lin@mediatek.com>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v2 11/11] arm64: dts: add dts nodes for MT6779
Date: Thu, 22 Aug 2019 08:46:04 +0800 [thread overview]
Message-ID: <1566434764.14794.2.camel@mtkswgap22> (raw)
In-Reply-To: <c533371d-efcd-59dc-0172-3f5775221302@kernel.org>
Hi Marc
> >>> + soc {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + compatible = "simple-bus";
> >>> + ranges;
> >>> +
> >>> + gic: interrupt-controller@0c000000 {
> >>> + compatible = "arm,gic-v3";
> >>> + #interrupt-cells = <3>;
> >>
> >> You also haven't described the CPU PMUs. Depending on how they are wired
> >> (SPIs or PPIs), you may have to change the interrupt-cells property to
> >> include a cell for the PPI partitioning.
> >>
> >
> > pmu nodes would be:
> >
> > pmu {
> > compatible = "arm,armv8-pmuv3";
> > interrupt-parent = <&gic>;
> > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> > };
> >
> > dsu-pmu-0 {
> > compatible = "arm,dsu-pmu";
> > interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
> > <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> > };
> >
> > so I think interrupt-cells could be <3>, will add pmu nodes in v3.
>
> No, that's wrong, at least for the CPU pmu node.
>
> First, you need two of them (one for the A55s, one for the A75s).
> Then you need to partition the corresponding PPI so that they can be
> described as separate affinity sets.
> Finally, this implies that #interrupt-cells goes up to 4, and all the
> interrupts directly routed to the GIC must be updated.
>
> You should have something like this:
>
> &gic {
> ppi-partitions {
> cluster0: interrupt-partition-0 {
> affinity = <&cpu0 &cpu1 &cpu2
> &cpu3 &cpu4 &cpu5>;
> };
>
> cluster1: interrupt-partition-1 {
> affinity = <&cpu6 &cpu7>;
> };
> };
>
> pmu_a55 {
> compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &cluster0>;
> };
>
> pmu_a75 {
> compatible = "arm,cortex-a75-pmu", "arm,armv8-pmuv3";
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &cluster1>;
> };
>
> Please see the rk3399 usage of the binding, as it is the canonical example.
>
> >
Got the idea. Will check rk3399 and fix our part. Thanks for reviewing.
next prev parent reply other threads:[~2019-08-22 0:46 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-19 9:21 [PATCHv2 00/11] Add basic SoC Support for Mediatek MT6779 SoC Mars Cheng
2019-08-19 9:21 ` [PATCH v2 01/11] dt-bindings: mediatek: add support for mt6779 reference board Mars Cheng
2019-08-23 15:50 ` Matthias Brugger
2019-08-19 9:21 ` [PATCH v2 02/11] dt-bindings: mtk-uart: add mt6779 uart bindings Mars Cheng
2019-08-23 15:47 ` Matthias Brugger
2019-08-19 9:21 ` [PATCH v2 03/11] dt-bindings: irq: mtk,sysirq: add support for mt6779 Mars Cheng
2019-08-23 8:51 ` Linus Walleij
2019-08-23 15:51 ` Matthias Brugger
2019-08-23 15:44 ` Matthias Brugger
2019-08-27 16:50 ` Rob Herring
2019-08-19 9:21 ` [PATCH v2 04/11] pinctrl: mediatek: update pinmux definitions " Mars Cheng
2019-08-23 15:53 ` Matthias Brugger
2020-01-02 4:04 ` Hanks Chen
2019-08-19 9:21 ` [PATCH v2 05/11] pinctrl: mediatek: avoid virtual gpio trying to set reg Mars Cheng
2019-08-23 8:57 ` Linus Walleij
2019-12-22 13:52 ` Hanks Chen
2020-01-07 10:20 ` Linus Walleij
2020-01-08 11:27 ` Hanks Chen
2019-08-19 9:21 ` [PATCH v2 06/11] pinctrl: mediatek: add pinctrl support for MT6779 SoC Mars Cheng
[not found] ` <CAGp9LzoVwNxY8Q3G4hxpa7=orsEox+J0mNamag70wyjrGvDiZw@mail.gmail.com>
2019-08-23 8:59 ` Linus Walleij
2019-08-19 9:21 ` [PATCH v2 07/11] pinctrl: mediatek: add mt6779 eint support Mars Cheng
2019-08-22 18:13 ` Sean Wang
2019-08-19 9:21 ` [PATCH v2 08/11] dt-bindings: mediatek: bindings for MT6779 clk Mars Cheng
2019-08-27 16:52 ` Rob Herring
2019-09-10 14:53 ` Stephen Boyd
2019-08-19 9:21 ` [PATCH v2 09/11] clk: mediatek: Add dt-bindings for MT6779 clocks Mars Cheng
2019-08-27 16:53 ` Rob Herring
2019-09-10 14:53 ` Stephen Boyd
2019-08-19 9:21 ` [PATCH v2 10/11] clk: mediatek: Add MT6779 clock support Mars Cheng
2019-09-10 14:53 ` Stephen Boyd
2019-08-19 9:21 ` [PATCH v2 11/11] arm64: dts: add dts nodes for MT6779 Mars Cheng
2019-08-19 9:40 ` Marc Zyngier
2019-08-19 11:42 ` Mars Cheng
2019-08-19 12:07 ` Marc Zyngier
2019-08-22 0:46 ` Mars Cheng [this message]
2019-08-23 16:13 ` Matthias Brugger
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1566434764.14794.2.camel@mtkswgap22 \
--to=mars.cheng@mediatek.com \
--cc=cc.hwang@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=linus.walleij@linaro.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=loda.chou@mediatek.com \
--cc=matthias.bgg@gmail.com \
--cc=maz@kernel.org \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=sean.wang@kernel.org \
--cc=wendell.lin@mediatek.com \
--cc=wsd_upstream@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).