From: Peng Fan <peng.fan@nxp.com>
To: "mturquette@baylibre.com" <mturquette@baylibre.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>
Cc: "kernel@pengutronix.de" <kernel@pengutronix.de>,
dl-linux-imx <linux-imx@nxp.com>,
Anson Huang <anson.huang@nxp.com>, Jacky Bai <ping.bai@nxp.com>,
Abel Vesa <abel.vesa@nxp.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Leonard Crestez <leonard.crestez@nxp.com>,
Peng Fan <peng.fan@nxp.com>
Subject: [PATCH V2 2/4] clk: imx: clk-pll14xx: unbypass PLL by default
Date: Mon, 26 Aug 2019 09:42:19 +0000 [thread overview]
Message-ID: <1566855676-11510-2-git-send-email-peng.fan@nxp.com> (raw)
In-Reply-To: <1566855676-11510-1-git-send-email-peng.fan@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
When registering the PLL, unbypass the PLL.
The PLL has two bypass control bit, BYPASS and EXT_BYPASS.
we will expose EXT_BYPASS to clk driver for mux usage, and keep
BYPASS inside pll14xx usage. The PLL has a restriction that
when M/P change, need to RESET/BYPASS pll to avoid glitch, so
we could not expose BYPASS.
To make it easy for clk driver usage, unbypass PLL which does
not hurt current function.
Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
V2:
New patch
drivers/clk/imx/clk-pll14xx.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index 656f48b002dd..7a815ec76aa5 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -368,6 +368,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
struct clk_pll14xx *pll;
struct clk *clk;
struct clk_init_data init;
+ u32 val;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
@@ -399,6 +400,10 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
pll->rate_table = pll_clk->rate_table;
pll->rate_count = pll_clk->rate_count;
+ val = readl_relaxed(pll->base + GNRL_CTL);
+ val &= ~BYPASS_MASK;
+ writel_relaxed(val, pll->base + GNRL_CTL);
+
clk = clk_register(NULL, &pll->hw);
if (IS_ERR(clk)) {
pr_err("%s: failed to register pll %s %lu\n",
--
2.16.4
next prev parent reply other threads:[~2019-08-26 9:43 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-26 9:42 [PATCH V2 1/4] clk: imx: pll14xx: avoid glitch when set rate Peng Fan
2019-08-26 9:42 ` Peng Fan [this message]
2019-08-26 9:42 ` [PATCH V2 3/4] clk: imx: imx8mm: fix pll mux bit Peng Fan
2019-08-26 9:42 ` [PATCH V2 4/4] clk: imx: imx8mn: " Peng Fan
2019-09-06 17:21 ` [PATCH V2 1/4] clk: imx: pll14xx: avoid glitch when set rate Stephen Boyd
2019-09-09 3:40 ` Peng Fan
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