IPQ8074 needs support for secure pil as well. Also, currently only unified firmware is supported. IPQ8074 supports split firmware for q6 and m3, so adding support for that. Also, this series is based on Govind’s, “[v4] Add non PAS wcss Q6 support for QCS404” https://www.spinics.net/lists/linux-remoteproc/msg03612.html [V2] Fixed all comments Gokul Sriram Palanisamy (12): remoteproc: qcom: Add PRNG proxy clock remoteproc: qcom: Add secure PIL support remoteproc: qcom: Add support for split q6 + m3 wlan firmware remoteproc: qcom: Add ssr subdevice identifier remoteproc: qcom: Update regmap offsets for halt register dt-bindings: clock: qcom: Add reset for WCSSAON clk: qcom: Add WCSSAON reset dt-bindings: mailbox: qom: Add ipq8074 APPS compatible mailbox: qcom: Add support for IPQ8074 APCS dt-bindings: firmware: qcom: Add compatible for IPQ8074 SoC arm64: dts: Add support for scm on IPQ8074 SoCs arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC .../devicetree/bindings/firmware/qcom,scm.txt | 1 + .../bindings/mailbox/qcom,apcs-kpss-global.txt | 1 + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 132 +++++++++++++++++ drivers/clk/qcom/gcc-ipq8074.c | 1 + drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + drivers/remoteproc/qcom_q6v5_wcss.c | 158 +++++++++++++++++---- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 7 files changed, 265 insertions(+), 30 deletions(-) -- 1.9.1
PRNG clock is needed by the secure PIL, support for the same is added in subsequent patches. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org> --- drivers/remoteproc/qcom_q6v5_wcss.c | 63 +++++++++++++++++++++++++++---------- 1 file changed, 46 insertions(+), 17 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c index 0821c94..dc2bae4 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -88,18 +88,6 @@ enum { WCSS_QCS404, }; -struct wcss_data { - const char *firmware_name; - int crash_reason_smem; - u8 version; - bool aon_reset_required; - const char *ssr_name; - const char *sysmon_name; - int ssctl_id; - const struct rproc_ops *ops; - bool requires_force_stop; -}; - struct q6v5_wcss { struct device *dev; @@ -124,6 +112,7 @@ struct q6v5_wcss { struct clk *qdsp6ss_xo_cbcr; struct clk *qdsp6ss_core_gfmux; struct clk *wcss_bcr_cbcr; + struct clk *prng_clk; struct regulator *cx_supply; struct qcom_rproc_glink glink_subdev; @@ -146,6 +135,20 @@ struct q6v5_wcss { bool requires_force_stop; }; +struct wcss_data { + int (*init_clock)(struct q6v5_wcss *wcss); + int (*init_regulator)(struct q6v5_wcss *wcss); + const char *firmware_name; + int crash_reason_smem; + u8 version; + bool aon_reset_required; + const char *ssr_name; + const char *sysmon_name; + int ssctl_id; + const struct rproc_ops *ops; + bool requires_force_stop; +}; + static int q6v5_wcss_reset(struct q6v5_wcss *wcss) { int ret; @@ -235,6 +238,12 @@ static int q6v5_wcss_start(struct rproc *rproc) struct q6v5_wcss *wcss = rproc->priv; int ret; + ret = clk_prepare_enable(wcss->prng_clk); + if (ret) { + dev_err(wcss->dev, "prng clock enable failed\n"); + return ret; + } + qcom_q6v5_prepare(&wcss->q6v5); /* Release Q6 and WCSS reset */ @@ -703,6 +712,7 @@ static int q6v5_wcss_stop(struct rproc *rproc) return ret; } + clk_disable_unprepare(wcss->prng_clk); qcom_q6v5_unprepare(&wcss->q6v5); return 0; @@ -858,7 +868,21 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) return 0; } -static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) +static int ipq8074_init_clock(struct q6v5_wcss *wcss) +{ + int ret; + + wcss->prng_clk = devm_clk_get(wcss->dev, "prng"); + if (IS_ERR(wcss->prng_clk)) { + ret = PTR_ERR(wcss->prng_clk); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "Failed to get prng clock\n"); + return ret; + } + return 0; +} + +static int qcs404_init_clock(struct q6v5_wcss *wcss) { int ret; @@ -973,7 +997,7 @@ static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) return 0; } -static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss) +static int qcs404_init_regulator(struct q6v5_wcss *wcss) { wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); if (IS_ERR(wcss->cx_supply)) @@ -1017,12 +1041,14 @@ static int q6v5_wcss_probe(struct platform_device *pdev) if (ret) goto free_rproc; - if (wcss->version == WCSS_QCS404) { - ret = q6v5_wcss_init_clock(wcss); + if (desc->init_clock) { + ret = desc->init_clock(wcss); if (ret) goto free_rproc; + } - ret = q6v5_wcss_init_regulator(wcss); + if (desc->init_regulator) { + ret = desc->init_regulator(wcss); if (ret) goto free_rproc; } @@ -1067,6 +1093,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev) } static const struct wcss_data wcss_ipq8074_res_init = { + .init_clock = ipq8074_init_clock, .firmware_name = "IPQ8074/q6_fw.mdt", .crash_reason_smem = 421, .aon_reset_required = true, @@ -1075,6 +1102,8 @@ static int q6v5_wcss_remove(struct platform_device *pdev) }; static const struct wcss_data wcss_qcs404_res_init = { + .init_clock = qcs404_init_clock, + .init_regulator = qcs404_init_regulator, .crash_reason_smem = 421, .firmware_name = "wcnss.mdt", .version = WCSS_QCS404, -- 1.9.1
IPQ8074 uses secure PIL. Hence, adding the support for the same. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org> --- drivers/remoteproc/qcom_q6v5_wcss.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c index dc2bae4..8418f57 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -19,6 +19,7 @@ #include <linux/regulator/consumer.h> #include <linux/reset.h> #include <linux/soc/qcom/mdt_loader.h> +#include <linux/qcom_scm.h> #include "qcom_common.h" #include "qcom_q6v5.h" @@ -83,6 +84,9 @@ #define TCSR_WCSS_CLK_ENABLE 0x14 #define MAX_HALT_REG 3 + +#define WCNSS_PAS_ID 6 + enum { WCSS_IPQ8074, WCSS_QCS404, @@ -133,6 +137,7 @@ struct q6v5_wcss { int crash_reason_smem; u8 version; bool requires_force_stop; + bool need_mem_protection; }; struct wcss_data { @@ -147,6 +152,7 @@ struct wcss_data { int ssctl_id; const struct rproc_ops *ops; bool requires_force_stop; + bool need_mem_protection; }; static int q6v5_wcss_reset(struct q6v5_wcss *wcss) @@ -246,6 +252,15 @@ static int q6v5_wcss_start(struct rproc *rproc) qcom_q6v5_prepare(&wcss->q6v5); + if (wcss->need_mem_protection) { + ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID); + if (ret) { + dev_err(wcss->dev, "wcss_reset failed\n"); + return ret; + } + goto wait_for_reset; + } + /* Release Q6 and WCSS reset */ ret = reset_control_deassert(wcss->wcss_reset); if (ret) { @@ -280,6 +295,7 @@ static int q6v5_wcss_start(struct rproc *rproc) if (ret) goto wcss_q6_reset; +wait_for_reset: ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); if (ret == -ETIMEDOUT) dev_err(wcss->dev, "start timed out\n"); @@ -688,6 +704,15 @@ static int q6v5_wcss_stop(struct rproc *rproc) struct q6v5_wcss *wcss = rproc->priv; int ret; + if (wcss->need_mem_protection) { + ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID); + if (ret) { + dev_err(wcss->dev, "not able to shutdown\n"); + return ret; + } + goto pas_done; + } + /* WCSS powerdown */ if (wcss->requires_force_stop) { ret = qcom_q6v5_request_stop(&wcss->q6v5); @@ -712,6 +737,7 @@ static int q6v5_wcss_stop(struct rproc *rproc) return ret; } +pas_done: clk_disable_unprepare(wcss->prng_clk); qcom_q6v5_unprepare(&wcss->q6v5); @@ -734,6 +760,12 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) { struct q6v5_wcss *wcss = rproc->priv; + if (wcss->need_mem_protection) + return qcom_mdt_load(wcss->dev, fw, rproc->firmware, + WCNSS_PAS_ID, wcss->mem_region, + wcss->mem_phys, wcss->mem_size, + &wcss->mem_reloc); + return qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, 0, wcss->mem_region, wcss->mem_phys, wcss->mem_size, &wcss->mem_reloc); @@ -1019,6 +1051,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev) if (!desc) return -EINVAL; + if (desc->need_mem_protection && !qcom_scm_is_available()) + return -EPROBE_DEFER; + rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, desc->firmware_name, sizeof(*wcss)); if (!rproc) { @@ -1032,6 +1067,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss->version = desc->version; wcss->requires_force_stop = desc->requires_force_stop; + wcss->need_mem_protection = desc->need_mem_protection; ret = q6v5_wcss_init_mmio(wcss, pdev); if (ret) @@ -1099,6 +1135,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev) .aon_reset_required = true, .ops = &q6v5_wcss_ipq8074_ops, .requires_force_stop = true, + .need_mem_protection = true, }; static const struct wcss_data wcss_qcs404_res_init = { -- 1.9.1
IPQ8074 supports split firmware for q6 and m3 as well. So add support for loading the m3 firmware before q6. Now the drivers works fine for both split and unified firmwares. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org> --- drivers/remoteproc/qcom_q6v5_wcss.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c index 8418f57..5957114 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -138,12 +138,14 @@ struct q6v5_wcss { u8 version; bool requires_force_stop; bool need_mem_protection; + const char *m3_firmware_name; }; struct wcss_data { int (*init_clock)(struct q6v5_wcss *wcss); int (*init_regulator)(struct q6v5_wcss *wcss); - const char *firmware_name; + const char *q6_firmware_name; + const char *m3_firmware_name; int crash_reason_smem; u8 version; bool aon_reset_required; @@ -759,7 +761,26 @@ static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, int len) static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) { struct q6v5_wcss *wcss = rproc->priv; + const struct firmware *m3_fw; + int ret; + + if (wcss->m3_firmware_name) { + ret = request_firmware(&m3_fw, wcss->m3_firmware_name, + wcss->dev); + if (ret) + goto skip_m3; + + ret = qcom_mdt_load_no_init(wcss->dev, m3_fw, + wcss->m3_firmware_name, 0, + wcss->mem_region, wcss->mem_phys, + wcss->mem_size, &wcss->mem_reloc); + if (ret) { + dev_err(wcss->dev, "can't load m3_fw.bXX\n"); + return ret; + } + } +skip_m3: if (wcss->need_mem_protection) return qcom_mdt_load(wcss->dev, fw, rproc->firmware, WCNSS_PAS_ID, wcss->mem_region, @@ -1055,7 +1076,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) return -EPROBE_DEFER; rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, - desc->firmware_name, sizeof(*wcss)); + desc->q6_firmware_name, sizeof(*wcss)); if (!rproc) { dev_err(&pdev->dev, "failed to allocate rproc\n"); return -ENOMEM; @@ -1068,6 +1089,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss->version = desc->version; wcss->requires_force_stop = desc->requires_force_stop; wcss->need_mem_protection = desc->need_mem_protection; + wcss->m3_firmware_name = desc->m3_firmware_name; ret = q6v5_wcss_init_mmio(wcss, pdev); if (ret) @@ -1130,7 +1152,8 @@ static int q6v5_wcss_remove(struct platform_device *pdev) static const struct wcss_data wcss_ipq8074_res_init = { .init_clock = ipq8074_init_clock, - .firmware_name = "IPQ8074/q6_fw.mdt", + .q6_firmware_name = "IPQ8074/q6_fw.mdt", + .m3_firmware_name = "IPQ8074/m3_fw.mdt", .crash_reason_smem = 421, .aon_reset_required = true, .ops = &q6v5_wcss_ipq8074_ops, @@ -1142,7 +1165,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev) .init_clock = qcs404_init_clock, .init_regulator = qcs404_init_regulator, .crash_reason_smem = 421, - .firmware_name = "wcnss.mdt", + .q6_firmware_name = "wcnss.mdt", .version = WCSS_QCS404, .aon_reset_required = false, .ssr_name = "mpss", -- 1.9.1
Add name for ssr subdevice on IPQ8074 SoC. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org> --- drivers/remoteproc/qcom_q6v5_wcss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c index 5957114..6d3ef06 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -1156,6 +1156,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev) .m3_firmware_name = "IPQ8074/m3_fw.mdt", .crash_reason_smem = 421, .aon_reset_required = true, + .ssr_name = "q6wcss", .ops = &q6v5_wcss_ipq8074_ops, .requires_force_stop = true, .need_mem_protection = true, -- 1.9.1
Fixed issue in reading halt-regs parameter from device-tree. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> --- drivers/remoteproc/qcom_q6v5_wcss.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c index 6d3ef06..b4ef5d3 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -83,7 +83,7 @@ #define TCSR_WCSS_CLK_MASK 0x1F #define TCSR_WCSS_CLK_ENABLE 0x14 -#define MAX_HALT_REG 3 +#define MAX_HALT_REG 4 #define WCNSS_PAS_ID 6 @@ -149,6 +149,7 @@ struct wcss_data { int crash_reason_smem; u8 version; bool aon_reset_required; + bool bcr_reset_required; const char *ssr_name; const char *sysmon_name; int ssctl_id; @@ -810,7 +811,8 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) }; static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss, - bool aon_reset_required) + bool aon_reset_required, + bool bcr_reset_required) { struct device *dev = wcss->dev; @@ -834,10 +836,13 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss, return PTR_ERR(wcss->wcss_q6_reset); } - wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset"); - if (IS_ERR(wcss->wcss_q6_bcr_reset)) { - dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); - return PTR_ERR(wcss->wcss_q6_reset); + if (bcr_reset_required) { + wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, + "wcss_q6_bcr_reset"); + if (IS_ERR(wcss->wcss_q6_bcr_reset)) { + dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); + return PTR_ERR(wcss->wcss_q6_reset); + } } return 0; @@ -885,9 +890,9 @@ static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, return -EINVAL; } - wcss->halt_q6 = halt_reg[0]; - wcss->halt_wcss = halt_reg[1]; - wcss->halt_nc = halt_reg[2]; + wcss->halt_q6 = halt_reg[1]; + wcss->halt_wcss = halt_reg[2]; + wcss->halt_nc = halt_reg[3]; return 0; } @@ -1111,7 +1116,8 @@ static int q6v5_wcss_probe(struct platform_device *pdev) goto free_rproc; } - ret = q6v5_wcss_init_reset(wcss, desc->aon_reset_required); + ret = q6v5_wcss_init_reset(wcss, desc->aon_reset_required, + desc->bcr_reset_required); if (ret) goto free_rproc; @@ -1156,6 +1162,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev) .m3_firmware_name = "IPQ8074/m3_fw.mdt", .crash_reason_smem = 421, .aon_reset_required = true, + .bcr_reset_required = false, .ssr_name = "q6wcss", .ops = &q6v5_wcss_ipq8074_ops, .requires_force_stop = true, @@ -1169,6 +1176,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev) .q6_firmware_name = "wcnss.mdt", .version = WCSS_QCS404, .aon_reset_required = false, + .bcr_reset_required = true, .ssr_name = "mpss", .sysmon_name = "wcnss", .ssctl_id = 0x12, -- 1.9.1
Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org> --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 4de4811..04e1f57 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -362,5 +362,6 @@ #define GCC_PCIE1_AXI_SLAVE_ARES 128 #define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 +#define GCC_WCSSAON_RESET 131 #endif -- 1.9.1
Add WCSSAON reset required for Q6v5 on IPQ8074 SoC. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org> --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 39ade58..06092f8 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4685,6 +4685,7 @@ enum { [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, + [GCC_WCSSAON_RESET] = { 0x59010, 0 }, }; static const struct of_device_id gcc_ipq8074_match_table[] = { -- 1.9.1
Add mailbox support required in IPQ8074 SoCs. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> --- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index 1232fc9..389c6ce 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -13,6 +13,7 @@ platforms. "qcom,msm8998-apcs-hmss-global" "qcom,qcs404-apcs-apps-global" "qcom,sdm845-apss-shared" + "qcom,ipq8074-apcs-apps-global" - reg: Usage: required -- 1.9.1
Add support of IPQ8074 with IPC register offset as 8. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 705e17a..52185eb 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -119,6 +119,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev) { .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 }, { .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 }, { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 }, + { .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 }, {} }; MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); -- 1.9.1
Add compatible for IPQ8074 support. This does not need clocks for scm calls. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 41f133a..3b153c1 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -17,6 +17,7 @@ Required properties: * "qcom,scm-msm8998" * "qcom,scm-ipq4019" * "qcom,scm-sdm845" + * "qcom,scm-ipq8074" and: * "qcom,scm" - clocks: Specifies clocks needed by the SCM interface, if any: -- 1.9.1
Enables scm support, clock is not needed for enabling scm interface. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 67ee5f5..6a61a63 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -10,6 +10,12 @@ model = "Qualcomm Technologies, Inc. IPQ8074"; compatible = "qcom,ipq8074"; + firmware { + scm { + compatible = "qcom,scm-ipq8074", "qcom,scm"; + }; + }; + soc: soc { #address-cells = <0x1>; #size-cells = <0x1>; -- 1.9.1
Enable remoteproc WCSS PIL driver with glink and ssr subdevices. Also configures shared memory and enables smp2p and mailboxes required for IPC. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org> --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 126 ++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 6a61a63..0ea026e 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -10,12 +10,66 @@ model = "Qualcomm Technologies, Inc. IPQ8074"; compatible = "qcom,ipq8074"; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smem_region: memory@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x00100000>; + }; + + q6_region: memory@4b000000 { + no-map; + reg = <0x0 0x4b000000 0x0 0x05f00000>; + }; + }; + firmware { scm { compatible = "qcom,scm-ipq8074", "qcom,scm"; }; }; + tcsr_mutex: hwlock@193d000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x80>; + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 0>; + }; + + wcss: smp2p-wcss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = <0 322 1>; + + qcom,ipc = <&apcs 8 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + qcom,smp2p-feature-ssr-ack; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { #address-cells = <0x1>; #size-cells = <0x1>; @@ -431,6 +485,78 @@ "axi_m_sticky"; status = "disabled"; }; + + apcs: syscon@b111000 { + compatible = "syscon"; + reg = <0x0b111000 0x1000>; + }; + + tcsr_q6: syscon@1945000 { + compatible = "syscon"; + reg = <0x01945000 0xe000>; + }; + + tcsr_mutex_regs: syscon@193d000 { + compatible = "syscon"; + reg = <0x01905000 0x8000>; + }; + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + + #mbox-cells = <1>; + }; + + q6v5_wcss: q6v5_wcss@cd00000 { + compatible = "qcom,ipq8074-wcss-pil"; + reg = <0x0cd00000 0x4040>, + <0x004ab000 0x20>; + reg-names = "qdsp6", + "rmb"; + qca,auto-restart; + qca,extended-intc; + interrupts-extended = <&intc 0 325 1>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 2 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + resets = <&gcc GCC_WCSSAON_RESET>, + <&gcc GCC_WCSS_BCR>, + <&gcc GCC_WCSS_Q6_BCR>; + + reset-names = "wcss_aon_reset", + "wcss_reset", + "wcss_q6_reset"; + + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "prng"; + + qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + + rpm_requests { + qcom,glink-channels = "IPCRTR"; + }; + }; + }; }; cpus { -- 1.9.1
On Fri, 13 Sep 2019 17:26:05 +0530, Gokul Sriram Palanisamy wrote:
> Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
>
> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
> ---
> include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
> 1 file changed, 1 insertion(+)
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
On Fri, 13 Sep 2019 17:26:07 +0530, Gokul Sriram Palanisamy wrote:
> Add mailbox support required in IPQ8074 SoCs.
>
> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> ---
> Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
On Fri, 13 Sep 2019 17:26:09 +0530, Gokul Sriram Palanisamy wrote:
> Add compatible for IPQ8074 support.
> This does not need clocks for scm calls.
>
> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> ---
> Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
Hi Rob,
On 2019-09-14 03:18, Rob Herring wrote:
> On Fri, 13 Sep 2019 17:26:05 +0530, Gokul Sriram Palanisamy wrote:
>> Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
>>
>> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
>> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
>> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
>> ---
>> include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
>> 1 file changed, 1 insertion(+)
>>
>
> Please add Acked-by/Reviewed-by tags when posting new versions.
> However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
Sorry, missed it. Will add it.
Regards,
Gokul
Hi Rob,
On 2019-09-14 03:18, Rob Herring wrote:
> On Fri, 13 Sep 2019 17:26:07 +0530, Gokul Sriram Palanisamy wrote:
>> Add mailbox support required in IPQ8074 SoCs.
>>
>> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
>> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
>> ---
>> Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt |
>> 1 +
>> 1 file changed, 1 insertion(+)
>>
>
> Please add Acked-by/Reviewed-by tags when posting new versions.
> However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
Sorry, missed it. Will add it.
Regards,
Gokul
Hi Rob,
On 2019-09-14 03:18, Rob Herring wrote:
> On Fri, 13 Sep 2019 17:26:09 +0530, Gokul Sriram Palanisamy wrote:
>> Add compatible for IPQ8074 support.
>> This does not need clocks for scm calls.
>>
>> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
>> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
>> ---
>> Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>
> Please add Acked-by/Reviewed-by tags when posting new versions.
> However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
Sorry, missed it. Will add it.
Regards,
Gokul
Quoting Gokul Sriram Palanisamy (2019-09-13 04:56:11) > diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > index 6a61a63..0ea026e 100644 > --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi > @@ -431,6 +485,78 @@ > "axi_m_sticky"; > status = "disabled"; > }; > + > + apcs: syscon@b111000 { > + compatible = "syscon"; > + reg = <0x0b111000 0x1000>; > + }; > + > + tcsr_q6: syscon@1945000 { > + compatible = "syscon"; > + reg = <0x01945000 0xe000>; > + }; > + > + tcsr_mutex_regs: syscon@193d000 { > + compatible = "syscon"; > + reg = <0x01905000 0x8000>; > + }; > + > + apcs_glb: mailbox@b111000 { This is the same as the syscon above. What's going on? > + compatible = "qcom,ipq8074-apcs-apps-global"; > + reg = <0x0b111000 0x1000>; > + > + #mbox-cells = <1>; > + };
Quoting Gokul Sriram Palanisamy (2019-09-13 04:56:05)
> Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
>
> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
Quoting Gokul Sriram Palanisamy (2019-09-13 04:56:06)
> Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
>
> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
On 2019-09-17 21:45, Stephen Boyd wrote:
> Quoting Gokul Sriram Palanisamy (2019-09-13 04:56:11)
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 6a61a63..0ea026e 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -431,6 +485,78 @@
>> "axi_m_sticky";
>> status = "disabled";
>> };
>> +
>> + apcs: syscon@b111000 {
>> + compatible = "syscon";
>> + reg = <0x0b111000 0x1000>;
>> + };
>> +
>> + tcsr_q6: syscon@1945000 {
>> + compatible = "syscon";
>> + reg = <0x01945000 0xe000>;
>> + };
>> +
>> + tcsr_mutex_regs: syscon@193d000 {
>> + compatible = "syscon";
>> + reg = <0x01905000 0x8000>;
>> + };
>> +
>> + apcs_glb: mailbox@b111000 {
>
> This is the same as the syscon above. What's going on?
>
>> + compatible = "qcom,ipq8074-apcs-apps-global";
>> + reg = <0x0b111000 0x1000>;
>> +
>> + #mbox-cells = <1>;
>> + };
Sorry for the delayed response. Will have this addressed and post a v3.
Regards,
Gokul