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From: Taniya Das <tdas@codeaurora.org>
To: "Stephen Boyd" <sboyd@kernel.org>,
	"Michael Turquette  " <mturquette@baylibre.com>
Cc: David Brown <david.brown@linaro.org>,
	Rajendra Nayak <rnayak@codeaurora.org>,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Andy Gross <agross@kernel.org>,
	devicetree@vger.kernel.org, robh@kernel.org, robh+dt@kernel.org,
	Taniya Das <tdas@codeaurora.org>
Subject: [PATCH v1 2/7] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
Date: Thu, 31 Oct 2019 17:51:08 +0530
Message-ID: <1572524473-19344-3-git-send-email-tdas@codeaurora.org> (raw)
In-Reply-To: <1572524473-19344-1-git-send-email-tdas@codeaurora.org>

The GPUCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 .../devicetree/bindings/clock/qcom,gpucc.txt       | 24 --------
 .../devicetree/bindings/clock/qcom,gpucc.yaml      | 69 ++++++++++++++++++++++
 2 files changed, 69 insertions(+), 24 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.txt
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.yaml

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
deleted file mode 100644
index 269afe8a..0000000
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Qualcomm Graphics Clock & Reset Controller Binding
---------------------------------------------------
-
-Required properties :
-- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
-- reg : shall contain base register location and length
-- #clock-cells : from common clock binding, shall contain 1
-- #reset-cells : from common reset binding, shall contain 1
-- #power-domain-cells : from generic power domain binding, shall contain 1
-- clocks : shall contain the XO clock
-	   shall contain the gpll0 out main clock (msm8998)
-- clock-names : shall be "xo"
-		shall be "gpll0" (msm8998)
-
-Example:
-	gpucc: clock-controller@5090000 {
-		compatible = "qcom,sdm845-gpucc";
-		reg = <0x5090000 0x9000>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-		#power-domain-cells = <1>;
-		clocks = <&rpmhcc RPMH_CXO_CLK>;
-		clock-names = "xo";
-	};
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
new file mode 100644
index 0000000..96aaf36
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller Binding
+
+maintainers:
+  - Taniya Das <tdas@codeaurora.org>
+
+description: |
+  Qualcomm grpahics clock control module which supports the clocks, resets and
+  power domains.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sdm845-gpucc
+      - qcom,msm8998-gpucc
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: Board XO source
+      - description: GPLL0 source from GCC
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+    items:
+      - const: xo
+      - const: gpll0
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+examples:
+  # Example of GPUCC with clock node properties for SDM845:
+  - |
+    clock-controller@5090000 {
+      compatible = "qcom,sdm845-gpucc";
+      reg = <0x5090000 0x9000>;
+      clocks = <&rpmhcc 0>, <&gcc 32>;
+      clock-names = "xo", "gpll0";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+     };
+...
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.


  parent reply index

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-31 12:21 [PATCH v1 0/7] Add GPU & Video Clock controller driver for SC7180 Taniya Das
2019-10-31 12:21 ` [PATCH v1 1/7] clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration Taniya Das
2019-11-06  0:36   ` Stephen Boyd
2019-11-15  8:11     ` Taniya Das
2019-11-07  4:24   ` Doug Anderson
2019-11-15  8:11     ` Taniya Das
2019-10-31 12:21 ` Taniya Das [this message]
2019-11-06  0:26   ` [PATCH v1 2/7] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings Stephen Boyd
2019-11-06  3:18     ` Rob Herring
2019-10-31 12:21 ` [PATCH v1 3/7] dt-bindings: clock: Introduce QCOM Graphics " Taniya Das
2019-11-06  3:59   ` Rob Herring
2019-10-31 12:21 ` [PATCH v1 4/7] clk: qcom: Add graphics clock controller driver for SC7180 Taniya Das
2019-11-06  0:30   ` Stephen Boyd
2019-11-15  8:11     ` Taniya Das
2019-11-16  5:50       ` Stephen Boyd
2019-10-31 12:21 ` [PATCH v1 5/7] dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings Taniya Das
2019-11-06  4:00   ` Rob Herring
2019-10-31 12:21 ` [PATCH v1 6/7] dt-bindings: clock: Introduce QCOM Video " Taniya Das
2019-11-06  0:37   ` Stephen Boyd
2019-10-31 12:21 ` [PATCH v1 7/7] clk: qcom: Add video clock controller driver for SC7180 Taniya Das
2019-11-06  0:39   ` Stephen Boyd
2019-11-15  8:11     ` Taniya Das
2019-11-16  5:51       ` Stephen Boyd

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