From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 952CBC432C0 for ; Wed, 27 Nov 2019 04:59:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 67A9E20835 for ; Wed, 27 Nov 2019 04:59:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="R6F/juMB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726634AbfK0E7i (ORCPT ); Tue, 26 Nov 2019 23:59:38 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17820 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726546AbfK0E7h (ORCPT ); Tue, 26 Nov 2019 23:59:37 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Nov 2019 20:59:40 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Nov 2019 20:59:37 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Nov 2019 20:59:37 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Nov 2019 04:59:36 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Nov 2019 04:59:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.169.149]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Nov 2019 20:59:36 -0800 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v2 01/11] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock ids Date: Tue, 26 Nov 2019 20:59:23 -0800 Message-ID: <1574830773-14892-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574830773-14892-1-git-send-email-skomatineni@nvidia.com> References: <1574830773-14892-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1574830780; bh=nBZ2jL8Xbzw6bstXTbwfBSRgB9PAmA4jf6nyPDEPCRc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=R6F/juMBDC5JvDEQMfAH+uKMwWRutAxkRwb8YDJSR0vOaS9LYczxm0AnMISORdbNf lRW7FdnIMuDG2pDCFBWI3qvd1Y/Bra3F4TqxZJ5jjAA/mT3pqYNAMVw1chOny/yJb7 i6+ofLF+6TkPIuKKMfselmR8PQq5uxGYqaI98uKAq29BmHA/7pZUV4fkSOF2BJAvTT yoheccWEKfKVD3Pncs5fQBl6KZRr7vSnFnvbrNkGQbFslregFhi30MD/LB16P3pskI LdK+Uzezxj5mQcAFfZJHcdLte+pkjpR9qm7vdy6bTEPE433J5g2XkSuESYILW3sO1V ITIkievKrV+2Q== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra PMC has clk_out_1, clk_out_2, clk_out_3 clocks and each of these clocks has mux and a gate as a part of PMC controller. This patch adds ids for each of these PMC clock mux and gates to use with the devicetree. Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/soc/tegra-pmc.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/soc/tegra-pmc.h diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h new file mode 100644 index 000000000000..705ee8083070 --- /dev/null +++ b/include/dt-bindings/soc/tegra-pmc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H +#define _DT_BINDINGS_SOC_TEGRA_PMC_H + +#define TEGRA_PMC_CLK_OUT_1_MUX 0 +#define TEGRA_PMC_CLK_OUT_1 1 +#define TEGRA_PMC_CLK_OUT_2_MUX 2 +#define TEGRA_PMC_CLK_OUT_2 3 +#define TEGRA_PMC_CLK_OUT_3_MUX 4 +#define TEGRA_PMC_CLK_OUT_3 5 + +#define TEGRA_PMC_CLK_MAX 6 + +#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */ -- 2.7.4