From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10369C43603 for ; Tue, 17 Dec 2019 20:05:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D72592176D for ; Tue, 17 Dec 2019 20:05:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="McYZRMPT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728371AbfLQUFC (ORCPT ); Tue, 17 Dec 2019 15:05:02 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:15604 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727975AbfLQUEU (ORCPT ); Tue, 17 Dec 2019 15:04:20 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 17 Dec 2019 12:04:10 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 17 Dec 2019 12:04:19 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 17 Dec 2019 12:04:19 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 17 Dec 2019 20:04:19 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 17 Dec 2019 20:04:19 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.174.101]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 17 Dec 2019 12:04:19 -0800 From: Sowjanya Komatineni To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v4 12/19] ASoC: tegra: Add initial parent configuration for audio mclk Date: Tue, 17 Dec 2019 12:03:59 -0800 Message-ID: <1576613046-17159-13-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576613046-17159-1-git-send-email-skomatineni@nvidia.com> References: <1576613046-17159-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1576613051; bh=mQEVupMkbU/jyL3p5x47nSTUlJ7UZJQiCwUhp/sDlfw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=McYZRMPTgKHAg5JrQmLMSRQNEawCe4VohH6KgRgDmA2VfjDBptbabD2LlzK4smf+b SDPs35tIlpSkYrlsaCjOEXgWO+26PlIucIm2aafY2sWqc2aqH85OhmW2xqMKy07QzL UMfkhicvqwJSkDLOr1MVelJBdeVKBfMef+v0QX9hKphpXSb2rpPqxjpt3BTzRETjqk OAsVZa9/12L/cIOeqf2rI2Y5BrZ32L/7UI/GtT219BamGlR4f+tcoUW0171H0ag8tG wlzjBJNNM3UNHXU5GRngNcwxu1+DH64uN6bs/VeUg0Kq2FtRWtndjnXXRLSDDWC7br a7DvF71ECtOYA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 through Tegra210 and currently Tegra clock driver does initial parent configuration for audio mclk "clk_out_1" and enables them by default. With the move of Tera PMC clocks from clock driver to Tegra PMC driver, initial parent configuration for audio clocks are through the device tree using assigned-clock-parents property. Default clock parents can be specified in device tree using assigned-clocks and assigned-clock-parents and there is no need to have clock driver do parent configuration and enable audio related clocks. This patch has implementation of doing initial parent confgiuration in audio driver when default parent configuration is not specified in the device tree using assigned-clock properties. This patch configures PLLA_OUT0 as parent to extern1 and extern1 as parent to clk_out_1 and uses clk_out_1 as cdev1 clock to allow mclk control from this driver. Signed-off-by: Sowjanya Komatineni --- sound/soc/tegra/tegra_asoc_utils.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c index 38535962029c..fe9ca8acd0fb 100644 --- a/sound/soc/tegra/tegra_asoc_utils.c +++ b/sound/soc/tegra/tegra_asoc_utils.c @@ -158,6 +158,7 @@ EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate); int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, struct device *dev) { + struct clk *clk_out_1, *clk_extern1; int ret; data->dev = dev; @@ -193,6 +194,41 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, return PTR_ERR(data->clk_cdev1); } + /* + * If clock parents are not set in DT, configure here to use clk_out_1 + * as mclk and extern1 as parent for Tegra30 and higher. + */ + if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) && + data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) { + clk_extern1 = devm_clk_get(dev, "extern1"); + if (IS_ERR(clk_extern1)) { + dev_err(data->dev, "Can't retrieve clk extern1\n"); + return PTR_ERR(clk_extern1); + } + + ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0); + if (ret < 0) { + dev_err(data->dev, + "Set parent failed for clk extern1\n"); + return ret; + } + + clk_out_1 = devm_clk_get(dev, "clk_out_1"); + if (IS_ERR(clk_out_1)) { + dev_err(data->dev, "Can't retrieve clk clk_out_1\n"); + return PTR_ERR(clk_out_1); + } + + ret = clk_set_parent(clk_out_1, clk_extern1); + if (ret < 0) { + dev_err(data->dev, + "Set parent failed for clk_out_1\n"); + return ret; + } + + data->clk_cdev1 = clk_out_1; + } + ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100); return ret; -- 2.7.4