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* [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver
@ 2019-12-17 20:03 Sowjanya Komatineni
  2019-12-17 20:03 ` [PATCH v4 01/19] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks Sowjanya Komatineni
                   ` (18 more replies)
  0 siblings, 19 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

This patch series moves Tegra PMC clocks from clock driver to pmc driver
along with the device trees changes and audio driver which uses one of
the pmc clock for audio mclk.

Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
are currently registered by Tegra clock driver using clk_regiser_mux and
clk_register_gate which performs direct Tegra PMC register access.

When Tegra PMC is in secure mode, any access from non-secure world will
not go through.

This patch series adds these Tegra PMC clocks and blink controls to Tegra
PMC driver with PMC as clock provider and removes them from Tegra clock
driver.

PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 thru Tegra210
and clock driver does inital parent configuration for it and enables them.
But this clock should be taken care by audio driver as there is no need
to have this clock pre enabled.

So, this series also includes patch that updates ASoC driver to take
care of parent configuration for mclk if device tree don't specify
initial parent configuration using assigned-clock-parents.

DTs are also updated to use clk_out_1 as audio mclk rather than extern1.

This series also includes a patch for mclk fallback to extern1 when
retrieving mclk fails to have this backward compatible of new DT with
old kernels.

[v4]:	Changes between v3 and v4 are
	- v3 Feedback
	- Updated clocks clk_m_div2 and clk_m_div4 as osc_div2 and osc_div4.
	  Tegra don't have clk_m_div2, clk_m_div4 and they should actually
	  be osc_div2 and osc_div4 clocks from osc pads.
	- Fixed PMC clock parents to use osc, osc_div2, osc_div4.
	- Register each PMC clock as single clock rather than separate
	  mux and gate clocks.
	- Update ASoC utils to use resource managed APIs rather than
	  using clk_get and clk_put.
	- Updated device tree and ASoC driver to use clk_out_1 instead of
	  clk_out_1_mux as PMC clocks are registered as single clock.
	- Update clock driver init_table to not enable audio related clocks
	  as ASoC utils will do audio clock enables.

[v3]:	Changes between v2 and v3 are
	- Removes set parent of clk_out_1_mux to extern1 and enabling
	  extern1 from the clock driver.
	- Doesn't enable clk_out_1 and blink by default in pmc driver
	- Updates ASoC driver to take care of audio mclk parent
	  configuration incase if device tree don't specify assigned
	  clock parent properties and enables mclk using both clk_out_1
	  and extern1.
	- updates all device trees using extern1 as mclk in sound node
	  to use clk_out_1 from pmc.
	- patch for YAML format pmc dt-binding
	- Includes v2 feedback

[v2]:	Changes between v1 and v2 are
	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
	- feedback related to pmc clocks in Tegra PMC driver from v1
	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
	  by the clock driver using helper functions from Tegra PMC.

 	  Note:
	  To use helper functions from PMC driver, PMC early init need to
	  happen prior to using helper functions and these helper functions are
	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
	  clock registration which happen in clock_init prior to Tegra PMC
	  probe.
	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
	  tegra_mc_init.
	  This implementation of configuring PMC registers thru helper
	  functions in clock driver needs proper changes across PMC, Clock,
	  EMC and MC inits to have it work across all Tegra platforms.

	  Currently PLLM Override is not enabled in the bootloader so proper
	  patches for this fix will be taken care separately.

[v1]:	v1 includes patches for below fixes.
	- adding clk_out_1, clk_out_2, clk_out_3, blink controls to Tegra PMC
	  driver and removing clk-tegra-pmc.
	- updated clock provider from tegra_car to pmc in the device tree
	  tegra210-smaug.dts that uses clk_out_2.
	- Added helper functions in PMC driver for WB0 PLLM overrides and PLLE
	  IDDQ programming to use by clock driver and updated clock driver to
	  use these helper functions and removed direct PMC access from clock
	  driver and all pmc base address references in clock driver.



Sowjanya Komatineni (19):
  dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks
  clk: tegra: Change CLK_M_DIV clocks to OSC_DIV clocks
  clk: tegra: Fix Tegra PMC clock out parents
  dt-bindings: tegra: Convert Tegra PMC bindings to YAML
  dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
  soc: tegra: Add Tegra PMC clock registrations into PMC driver
  dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock
  soc: tegra: Add support for 32KHz blink clock
  clk: tegra: Remove tegra_pmc_clk_init along with clk ids
  dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
  ASoC: tegra: Use device managed resource APIs to get the clock
  ASoC: tegra: Add initial parent configuration for audio mclk
  ASoC: tegra: Add fallback implementation for audio mclk
  clk: tegra: Remove audio related clock enables from clocks init_table
  ARM: dts: tegra: Add clock-cells property to pmc
  arm64: tegra: Add clock-cells property to Tegra PMC node
  ARM: tegra: Update sound node clocks in device tree
  arm64: tegra: smaug: Change clk_out_2 provider to pmc
  ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car to pmc

 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  37 ++-
 .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml     | 291 +++++++++++++++++
 .../devicetree/bindings/sound/nau8825.txt          |   2 +-
 arch/arm/boot/dts/tegra114-dalmore.dts             |   7 +-
 arch/arm/boot/dts/tegra114.dtsi                    |   4 +-
 arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi        |   7 +-
 arch/arm/boot/dts/tegra124-apalis.dtsi             |   7 +-
 arch/arm/boot/dts/tegra124-jetson-tk1.dts          |   7 +-
 arch/arm/boot/dts/tegra124-nyan.dtsi               |   7 +-
 arch/arm/boot/dts/tegra124-venice2.dts             |   7 +-
 arch/arm/boot/dts/tegra124.dtsi                    |   4 +-
 arch/arm/boot/dts/tegra20.dtsi                     |   4 +-
 arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi         |   7 +-
 arch/arm/boot/dts/tegra30-apalis.dtsi              |   7 +-
 arch/arm/boot/dts/tegra30-beaver.dts               |   7 +-
 arch/arm/boot/dts/tegra30-cardhu.dtsi              |   7 +-
 arch/arm/boot/dts/tegra30-colibri.dtsi             |   7 +-
 arch/arm/boot/dts/tegra30.dtsi                     |   4 +-
 arch/arm64/boot/dts/nvidia/tegra132.dtsi           |   4 +-
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts      |   2 +-
 arch/arm64/boot/dts/nvidia/tegra210.dtsi           |   2 +
 drivers/clk/tegra/Makefile                         |   1 -
 drivers/clk/tegra/clk-id.h                         |  11 +-
 drivers/clk/tegra/clk-tegra-fixed.c                |  32 +-
 drivers/clk/tegra/clk-tegra-pmc.c                  | 122 -------
 drivers/clk/tegra/clk-tegra114.c                   |  41 +--
 drivers/clk/tegra/clk-tegra124.c                   |  46 +--
 drivers/clk/tegra/clk-tegra20.c                    |   9 +-
 drivers/clk/tegra/clk-tegra210.c                   |  30 +-
 drivers/clk/tegra/clk-tegra30.c                    |  31 +-
 drivers/clk/tegra/clk.h                            |   1 -
 drivers/soc/tegra/pmc.c                            | 355 +++++++++++++++++++++
 include/dt-bindings/clock/tegra114-car.h           |  18 +-
 include/dt-bindings/clock/tegra124-car-common.h    |  18 +-
 include/dt-bindings/clock/tegra20-car.h            |   2 +-
 include/dt-bindings/clock/tegra210-car.h           |  18 +-
 include/dt-bindings/clock/tegra30-car.h            |  18 +-
 include/dt-bindings/soc/tegra-pmc.h                |  16 +
 sound/soc/tegra/tegra_alc5632.c                    |   7 +-
 sound/soc/tegra/tegra_asoc_utils.c                 |  79 +++--
 sound/soc/tegra/tegra_asoc_utils.h                 |   1 -
 sound/soc/tegra/tegra_max98090.c                   |  22 +-
 sound/soc/tegra/tegra_rt5640.c                     |  22 +-
 sound/soc/tegra/tegra_rt5677.c                     |   7 +-
 sound/soc/tegra/tegra_sgtl5000.c                   |   7 +-
 sound/soc/tegra/tegra_wm8753.c                     |  22 +-
 sound/soc/tegra/tegra_wm8903.c                     |  22 +-
 sound/soc/tegra/tegra_wm9712.c                     |   8 +-
 sound/soc/tegra/trimslice.c                        |  18 +-
 49 files changed, 967 insertions(+), 448 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
 delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c
 create mode 100644 include/dt-bindings/soc/tegra-pmc.h

-- 
2.7.4


^ permalink raw reply	[flat|nested] 54+ messages in thread

* [PATCH v4 01/19] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-18 21:19   ` Rob Herring
  2019-12-17 20:03 ` [PATCH v4 02/19] clk: tegra: Change CLK_M_DIV clocks " Sowjanya Komatineni
                   ` (17 subsequent siblings)
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has
OSC_DIV2 and OSC_DIV4 clocks from OSC pads.

This patch changes CLK_M_DIV2 and CLK_M_DIV4 clock ids to OSC_DIV2
and OSC_DIV4 clock ids for Tegra30 through Tegra210.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 include/dt-bindings/clock/tegra114-car.h        | 4 ++--
 include/dt-bindings/clock/tegra124-car-common.h | 4 ++--
 include/dt-bindings/clock/tegra210-car.h        | 4 ++--
 include/dt-bindings/clock/tegra30-car.h         | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index bb5c2c999c05..f4880959b094 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -226,8 +226,8 @@
 #define TEGRA114_CLK_FUSE_BURN 199
 #define TEGRA114_CLK_CLK_32K 200
 #define TEGRA114_CLK_CLK_M 201
-#define TEGRA114_CLK_CLK_M_DIV2 202
-#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_OSC_DIV2 202
+#define TEGRA114_CLK_OSC_DIV4 203
 #define TEGRA114_CLK_PLL_REF 204
 #define TEGRA114_CLK_PLL_C 205
 #define TEGRA114_CLK_PLL_C_OUT1 206
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index 0c4f5be0a742..e7e601a88d3d 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -225,8 +225,8 @@
 #define TEGRA124_CLK_FUSE_BURN 199
 #define TEGRA124_CLK_CLK_32K 200
 #define TEGRA124_CLK_CLK_M 201
-#define TEGRA124_CLK_CLK_M_DIV2 202
-#define TEGRA124_CLK_CLK_M_DIV4 203
+#define TEGRA124_CLK_OSC_DIV2 202
+#define TEGRA124_CLK_OSC_DIV4 203
 #define TEGRA124_CLK_PLL_REF 204
 #define TEGRA124_CLK_PLL_C 205
 #define TEGRA124_CLK_PLL_C_OUT1 206
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 44f60623f99b..6f65c14bf013 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -260,8 +260,8 @@
 #define TEGRA210_CLK_FUSE_BURN 231
 #define TEGRA210_CLK_CLK_32K 232
 #define TEGRA210_CLK_CLK_M 233
-#define TEGRA210_CLK_CLK_M_DIV2 234
-#define TEGRA210_CLK_CLK_M_DIV4 235
+#define TEGRA210_CLK_OSC_DIV2 234
+#define TEGRA210_CLK_OSC_DIV4 235
 #define TEGRA210_CLK_PLL_REF 236
 #define TEGRA210_CLK_PLL_C 237
 #define TEGRA210_CLK_PLL_C_OUT1 238
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 3c90f1535551..907a8a04c280 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -194,8 +194,8 @@
 #define TEGRA30_CLK_TVO 169
 #define TEGRA30_CLK_CLK_32K 170
 #define TEGRA30_CLK_CLK_M 171
-#define TEGRA30_CLK_CLK_M_DIV2 172
-#define TEGRA30_CLK_CLK_M_DIV4 173
+#define TEGRA30_CLK_OSC_DIV2 172
+#define TEGRA30_CLK_OSC_DIV4 173
 #define TEGRA30_CLK_PLL_REF 174
 #define TEGRA30_CLK_PLL_C 175
 #define TEGRA30_CLK_PLL_C_OUT1 176
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 02/19] clk: tegra: Change CLK_M_DIV clocks to OSC_DIV clocks
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
  2019-12-17 20:03 ` [PATCH v4 01/19] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-17 20:03 ` [PATCH v4 03/19] clk: tegra: Fix Tegra PMC clock out parents Sowjanya Komatineni
                   ` (16 subsequent siblings)
  18 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks from CLK_M and instead
it has OSC_DIV2 and OSC_DIV4 clocks from OSC pads.

This patch removes CLK_M_DIV2 and CLK_M_DIV4 fixed clocks and adds
OSC_DIV2 and OSC_DIV4 fixed clocks with OSC as parent for Tegra30
through Tegra210 clock drivers.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/clk/tegra/clk-id.h          |  4 ++--
 drivers/clk/tegra/clk-tegra-fixed.c | 32 ++++++++++++++++----------------
 drivers/clk/tegra/clk-tegra114.c    | 19 ++++---------------
 drivers/clk/tegra/clk-tegra124.c    |  8 ++++----
 drivers/clk/tegra/clk-tegra210.c    |  8 ++++----
 drivers/clk/tegra/clk-tegra30.c     |  8 ++++----
 6 files changed, 34 insertions(+), 45 deletions(-)

diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index c4faebd32760..1bf21766d3e8 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -44,8 +44,8 @@ enum clk_id {
 	tegra_clk_clk72Mhz,
 	tegra_clk_clk72Mhz_8,
 	tegra_clk_clk_m,
-	tegra_clk_clk_m_div2,
-	tegra_clk_clk_m_div4,
+	tegra_clk_osc_div2,
+	tegra_clk_osc_div4,
 	tegra_clk_clk_out_1,
 	tegra_clk_clk_out_1_mux,
 	tegra_clk_clk_out_2,
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
index 7c6c8abfcde6..8304f8cf9dd2 100644
--- a/drivers/clk/tegra/clk-tegra-fixed.c
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -56,6 +56,22 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
 					0, 1, clk_m_div);
 	*dt_clk = clk;
 
+	/* osc_div2 */
+	dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
+	if (dt_clk) {
+		clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
+						0, 1, 2);
+		*dt_clk = clk;
+	}
+
+	/* osc_div4 */
+	dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
+	if (dt_clk) {
+		clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
+						0, 1, 4);
+		*dt_clk = clk;
+	}
+
 	/* pll_ref */
 	val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
 	pll_ref_div = 1 << val;
@@ -84,22 +100,6 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
 		clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
 		*dt_clk = clk;
 	}
-
-	/* clk_m_div2 */
-	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
-	if (dt_clk) {
-		clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
-					CLK_SET_RATE_PARENT, 1, 2);
-		*dt_clk = clk;
-	}
-
-	/* clk_m_div4 */
-	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
-	if (dt_clk) {
-		clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
-					CLK_SET_RATE_PARENT, 1, 4);
-		*dt_clk = clk;
-	}
 }
 
 void tegra_clk_osc_resume(void __iomem *clk_base)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 4efcaaf51b3a..9d2ca387114c 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -735,8 +735,8 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
 	[tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
 	[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
-	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
-	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
+	[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
+	[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
 	[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
 	[tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
 	[tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
@@ -815,8 +815,8 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
 	{ .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
 	{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
-	{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
-	{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
+	{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
+	{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
 	{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
 	{ .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
 	{ .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
@@ -900,17 +900,6 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
 	/* clk_32k */
 	clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
 	clks[TEGRA114_CLK_CLK_32K] = clk;
-
-	/* clk_m_div2 */
-	clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
-					CLK_SET_RATE_PARENT, 1, 2);
-	clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
-
-	/* clk_m_div4 */
-	clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
-					CLK_SET_RATE_PARENT, 1, 4);
-	clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
-
 }
 
 static void __init tegra114_pll_init(void __iomem *clk_base,
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index b3110d5b5a6c..15f42718f4cb 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -860,8 +860,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
 	[tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
 	[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
-	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
-	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
+	[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
+	[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
 	[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
 	[tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
 	[tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
@@ -941,8 +941,8 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
 	{ .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
 	{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
-	{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
-	{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
+	{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
+	{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
 	{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
 	{ .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
 	{ .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 762cd186f714..5687fcda620e 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2371,8 +2371,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
 	[tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
 	[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
-	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
-	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
+	[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
+	[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
 	[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
 	[tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
 	[tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
@@ -2497,8 +2497,8 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
 	{ .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
 	{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
-	{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
-	{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
+	{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
+	{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
 	{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
 	{ .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
 	{ .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c8bc18e4d7e5..1322188edb72 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -581,8 +581,8 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
 	{ .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
 	{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
-	{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
-	{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
+	{ .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
+	{ .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
 	{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
 	{ .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
 	{ .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
@@ -683,8 +683,8 @@ static struct tegra_devclk devclks[] __initdata = {
 static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
 	[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
-	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
-	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
+	[tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
+	[tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
 	[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
 	[tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
 	[tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 03/19] clk: tegra: Fix Tegra PMC clock out parents
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
  2019-12-17 20:03 ` [PATCH v4 01/19] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks Sowjanya Komatineni
  2019-12-17 20:03 ` [PATCH v4 02/19] clk: tegra: Change CLK_M_DIV clocks " Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-17 20:03 ` [PATCH v4 04/19] dt-bindings: tegra: Convert Tegra PMC bindings to YAML Sowjanya Komatineni
                   ` (15 subsequent siblings)
  18 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra PMC clock out parents are osc, osc_div2, osc_div4 and extern
clock.

Clock driver is using incorrect parents clk_m, clk_m_div2, clk_m_div4
for PMC clocks.

This patch fixes this.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/clk/tegra/clk-tegra-pmc.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
index bec3e008335f..5e044ba1ae36 100644
--- a/drivers/clk/tegra/clk-tegra-pmc.c
+++ b/drivers/clk/tegra/clk-tegra-pmc.c
@@ -49,16 +49,16 @@ struct pmc_clk_init_data {
 
 static DEFINE_SPINLOCK(clk_out_lock);
 
-static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
-	"clk_m_div4", "extern1",
+static const char *clk_out1_parents[] = { "osc", "osc_div2",
+	"osc_div4", "extern1",
 };
 
-static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
-	"clk_m_div4", "extern2",
+static const char *clk_out2_parents[] = { "osc", "osc_div2",
+	"osc_div4", "extern2",
 };
 
-static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
-	"clk_m_div4", "extern3",
+static const char *clk_out3_parents[] = { "osc", "osc_div2",
+	"osc_div4", "extern3",
 };
 
 static struct pmc_clk_init_data pmc_clks[] = {
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 04/19] dt-bindings: tegra: Convert Tegra PMC bindings to YAML
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (2 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 03/19] clk: tegra: Fix Tegra PMC clock out parents Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-18 21:29   ` Rob Herring
  2019-12-17 20:03 ` [PATCH v4 05/19] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings Sowjanya Komatineni
                   ` (14 subsequent siblings)
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

This patch adds YAML schema for Tegra PMC bindings.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml     | 291 +++++++++++++++++++++
 1 file changed, 291 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
new file mode 100644
index 000000000000..ab614f1be177
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -0,0 +1,291 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra Power Management Controller (PMC)
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jonathan Hunter <jonathanh@nvidia.com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: nvidia,tegra20-pmc
+          - const: nvidia,tegra20-pmc
+          - const: nvidia,tegra30-pmc
+          - const: nvidia,tegra114-pmc
+          - const: nvidia,tegra124-pmc
+          - const: nvidia,tegra210-pmc
+
+  reg:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pclk, clk32k_in
+    description:
+      pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
+      input to Tegra.
+
+  clocks:
+    maxItems: 2
+
+  '#clock-cells':
+    const: 1
+    description:
+      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
+      Consumer of PMC clock should specify the desired clock by having
+      the clock ID in its "clocks" phandle cell with pmc clock provider.
+      See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
+      clock IDs.
+
+  nvidia,invert-interrupt:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description: Inverts the PMU interrupt signal.
+      The PMU is an external Power Management Unit, whose interrupt output
+      signal is fed into the PMC. This signal is optionally inverted, and
+      then fed into the ARM GIC. The PMC is not involved in the detection
+      or handling of this interrupt signal, merely its inversion.
+
+  nvidia,core-power-req-active-high:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description: Core power request active-high.
+
+  nvidia,sys-clock-req-active-high:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description: System clock request active-high.
+
+  nvidia,combined-power-req:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description: combined power request for CPU and Core.
+
+  nvidia,cpu-pwr-good-en:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      CPU power good signal from external PMIC to PMC is enabled.
+
+  nvidia,suspend-mode:
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - enum: [0, 1, 2]
+    description:
+      The suspend mode that the platform should use.
+      Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
+      Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
+      Mode 2 is for LP2, CPU voltage off
+
+  nvidia,cpu-pwr-good-time:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: CPU power good time in uSec.
+
+  nvidia,cpu-pwr-off-time:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: CPU power off time in uSec.
+
+  nvidia,core-pwr-good-time:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description:
+      <Oscillator-stable-time Power-stable-time>
+      Core power good time in uSec.
+
+  nvidia,core-pwr-off-time:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Core power off time in uSec.
+
+  nvidia,lp0-vec:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description:
+      <start length> Starting address and length of LP0 vector.
+      The LP0 vector contains the warm boot code that is executed
+      by AVP when resuming from the LP0 state.
+      The AVP (Audio-Video Processor) is an ARM7 processor and
+      always being the first boot processor when chip is power on
+      or resume from deep sleep mode. When the system is resumed
+      from the deep sleep mode, the warm boot code will restore
+      some PLLs, clocks and then brings up CPU0 for resuming the
+      system.
+
+  i2c-thermtrip:
+    type: object
+    description:
+      On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
+      hardware-triggered thermal reset will be enabled.
+
+    properties:
+      nvidia,i2c-controller-id:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          ID of I2C controller to send poweroff command to PMU.
+          Valid values are described in section 9.2.148
+          "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
+          Manual.
+
+      nvidia,bus-addr:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: Bus address of the PMU on the I2C bus.
+
+      nvidia,reg-addr:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: PMU I2C register address to issue poweroff command.
+
+      nvidia,reg-data:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: Poweroff command to write to PMU.
+
+      nvidia,pinmux-id:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          Pinmux used by the hardware when issuing Poweroff command.
+          Defaults to 0. Valid values are described in section 12.5.2
+          "Pinmux Support" of the Tegra4 Technical Reference Manual.
+
+    required:
+      - nvidia,i2c-controller-id
+      - nvidia,bus-addr
+      - nvidia,reg-addr
+      - nvidia,reg-data
+
+  powergates:
+    type: object
+    description:
+      This node contains a hierarchy of power domain nodes, which should
+      match the powergates on the Tegra SoC. Each powergate node
+      represents a power-domain on the Tegra SoC that can be power-gated
+      by the Tegra PMC.
+      Hardware blocks belonging to a power domain should contain
+      "power-domains" property that is a phandle pointing to corresponding
+      powergate node.
+      Please refer to Tegra TRM for mode details on the powergate nodes to
+      use for each power-gate block inside Tegra.
+
+    patternProperties:
+      "^[a-z0-9]+$":
+        if:
+          type: object
+        then:
+          patternProperties:
+            clocks:
+              description:
+                Must contain an entry for each clock required by the PMC
+                for controlling a power-gate.
+                See ../clocks/clock-bindings.txt document for more details.
+
+            resets:
+              description:
+                Must contain an entry for each reset required by the PMC
+                for controlling a power-gate.
+                See ../reset/reset.txt for more details.
+
+            '#power-domain-cells':
+              description: Must be 0.
+
+    required:
+      - clocks
+      - resets
+      - '#power-domain-cells'
+
+patternProperties:
+  "^.*@[0-9a-f]+$":
+    type: object
+
+    properties:
+      pins:
+        $ref: /schemas/types.yaml#/definitions/string
+        description: Must contain name of the pad(s) to be configured.
+
+      low-power-enable:
+        $ref: /schemas/types.yaml#/definitions/flag
+        description: Configure the pad into power down mode.
+
+      low-power-disable:
+        $ref: /schemas/types.yaml#/definitions/flag
+        description: Configure the pad into active mode.
+
+      power-source:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
+          TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
+          The values are defined in
+          include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
+          Power state can be configured on all Tegra124 and Tegra132
+          pads. None of the Tegra124 or Tegra132 pads support signaling
+          voltage switching.
+          All of the listed Tegra210 pads except pex-cntrl support power
+          state configuration. Signaling voltage switching is supported
+          on below Tegra210 pads.
+          audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
+          sdmmc3, spi, spi-hv, and uart.
+
+    required:
+      - pins
+
+required:
+  - compatible
+  - reg
+  - clock-names
+  - clocks
+  - '#clock-cells'
+
+if:
+  properties:
+    nvidia,suspend-mode:
+      contains:
+        const: 2
+
+then:
+  required:
+    - nvidia,cpu-pwr-good-time
+    - nvidia,cpu-pwr-off-time
+    - nvidia,core-pwr-good-time
+    - nvidia,core-pwr-off-time
+
+examples:
+  - |
+    #include <dt-bindings/soc/tegra-pmc.h>
+
+    pmc: pmc@7000e400 {
+              compatible = "nvidia,tegra210-pmc";
+              reg = <0x0 0x7000e400 0x0 0x400>;
+              clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+              clock-names = "pclk", "clk32k_in";
+              #clock-cells = <1>;
+
+              powergates {
+                    pd_audio: aud {
+                            clocks = <&tegra_car TEGRA210_CLK_APE>,
+                                     <&tegra_car TEGRA210_CLK_APB2APE>;
+                            resets = <&tegra_car 198>;
+                            #power-domain-cells = <0>;
+                    };
+
+                    pd_xusbss: xusba {
+                            clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+                            resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+                            #power-domain-cells = <0>;
+                    };
+              };
+
+              sdmmc1_3v3: sdmmc1-3v3 {
+                      pins = "sdmmc1";
+                      power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+              };
+
+              sdmmc1_1v8: sdmmc1-1v8 {
+                      pins = "sdmmc1";
+                      power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+              };
+
+              nvidia,invert-interrupt;
+              nvidia,suspend-mode = <0>;
+              nvidia,cpu-pwr-good-time = <0>;
+              nvidia,cpu-pwr-off-time = <0>;
+              nvidia,core-pwr-good-time = <4587 3876>;
+              nvidia,core-pwr-off-time = <39065>;
+              nvidia,core-power-req-active-high;
+              nvidia,sys-clock-req-active-high;
+    };
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 05/19] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (3 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 04/19] dt-bindings: tegra: Convert Tegra PMC bindings to YAML Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-18  7:56   ` Dmitry Osipenko
  2019-12-17 20:03 ` [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver Sowjanya Komatineni
                   ` (13 subsequent siblings)
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra PMC has 3 clocks clk_out_1, clk_out_2, and clk_out_3.

This patch documents PMC clock bindings and adds a header defining
Tegra PMC clock ids.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      | 37 +++++++++++++++++++++-
 include/dt-bindings/soc/tegra-pmc.h                | 15 +++++++++
 2 files changed, 51 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/soc/tegra-pmc.h

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index cb12f33a247f..80cdcad4ab8c 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -21,6 +21,10 @@ Required properties:
 - clock-names : Must include the following entries:
   "pclk" (The Tegra clock of that name),
   "clk32k_in" (The 32KHz clock input to Tegra).
+- #clock-cells : Should be 1 for Tegra30 and higher.
+  In clock consumers, this cell represents the PMC clock ID.
+  The assignments may be found in header file
+  <dt-bindings/soc/tegra-pmc.h>.
 
 Optional properties:
 - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
@@ -80,11 +84,12 @@ Optional nodes:
 Example:
 
 / SoC dts including file
-pmc@7000f400 {
+pmc: pmc@7000f400 {
 	compatible = "nvidia,tegra20-pmc";
 	reg = <0x7000e400 0x400>;
 	clocks = <&tegra_car 110>, <&clk32k_in>;
 	clock-names = "pclk", "clk32k_in";
+	#clock-cells = <1>;
 	nvidia,invert-interrupt;
 	nvidia,suspend-mode = <1>;
 	nvidia,cpu-pwr-good-time = <2000>;
@@ -171,6 +176,7 @@ Example:
 		reg = <0x0 0x7000e400 0x0 0x400>;
 		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 
 		powergates {
 			pd_audio: aud {
@@ -260,6 +266,7 @@ Pad configuration state example:
 		reg = <0x0 0x7000e400 0x0 0x400>;
 		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 
 		...
 
@@ -298,3 +305,31 @@ Pinctrl client example:
 		pinctrl-1 = <&hdmi_on>;
 		pinctrl-names = "hdmi-on", "hdmi-off";
 	};
+
+== Clock Control ==
+
+Tegra PMC has 3 clocks clk_1, clk_2 and clk_3. Each of these clocks has
+source selection and enable/disable gate.
+Parent/source for these clocks can be either of osc, osc_div2, osc_div4,
+or extern clock from Tegra CAR module.
+
+Clock configuration example:
+	pmc: pmc@7000e400 {
+		compatible = "nvidia,tegra210-pmc";
+		reg = <0x0 0x7000e400 0x0 0x400>;
+		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
+	};
+
+Clock consumer example:
+	i2c@7000c500 {
+		cam_sensor {
+			...
+			clocks = <&pmc TEGRA_PMC_CLK_OUT_3>;
+			clock-names = "mclk";
+			assigned-clocks = <&pmc TEGRA_PMC_CLK_OUT_3>;
+			assigned-clock-parents = <&tegra_car TEGRA210_CLK_EXTERN3>;
+			...
+		};
+	};
diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h
new file mode 100644
index 000000000000..f7c866404456
--- /dev/null
+++ b/include/dt-bindings/soc/tegra-pmc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H
+#define _DT_BINDINGS_SOC_TEGRA_PMC_H
+
+#define TEGRA_PMC_CLK_OUT_1		0
+#define TEGRA_PMC_CLK_OUT_2		1
+#define TEGRA_PMC_CLK_OUT_3		2
+
+#define TEGRA_PMC_CLK_MAX		3
+
+#endif	/* _DT_BINDINGS_SOC_TEGRA_PMC_H */
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (4 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 05/19] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-18  8:30   ` Dmitry Osipenko
  2019-12-17 20:03 ` [PATCH v4 07/19] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock Sowjanya Komatineni
                   ` (12 subsequent siblings)
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
these PMC clocks are registered by Tegra clock driver with each clock as
separate mux and gate clocks using clk_register_mux and clk_register_gate
by passing PMC base address and register offsets and PMC programming for
these clocks happens through direct PMC access by the clock driver.

With this, when PMC is in secure mode any direct PMC access from the
non-secure world does not go through and these clocks will not be
functional.

This patch adds these PMC clocks registration to pmc driver with PMC as
a clock provider and registers each clock as single clock.

clk_ops callback implementations for these clocks uses tegra_pmc_readl and
tegra_pmc_writel which supports PMC programming in both secure mode and
non-secure mode.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/soc/tegra/pmc.c | 248 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 248 insertions(+)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index ea0e11a09c12..6d65194a6e71 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -13,6 +13,9 @@
 
 #include <linux/arm-smccc.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/clk-conf.h>
 #include <linux/clk/tegra.h>
 #include <linux/debugfs.h>
 #include <linux/delay.h>
@@ -48,6 +51,7 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
 #include <dt-bindings/gpio/tegra186-gpio.h>
 #include <dt-bindings/gpio/tegra194-gpio.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 #define PMC_CNTRL			0x0
 #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
@@ -100,6 +104,7 @@
 #define PMC_WAKE2_STATUS		0x168
 #define PMC_SW_WAKE2_STATUS		0x16c
 
+#define PMC_CLK_OUT_CNTRL		0x1a8
 #define PMC_SENSOR_CTRL			0x1b0
 #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
 #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
@@ -155,6 +160,64 @@
 #define  TEGRA_SMC_PMC_READ	0xaa
 #define  TEGRA_SMC_PMC_WRITE	0xbb
 
+struct pmc_clk {
+	struct clk_hw	hw;
+	unsigned long	offs;
+	u32		mux_mask;
+	u32		mux_shift;
+	u32		gate_shift;
+};
+
+#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
+
+struct pmc_clk_init_data {
+	char *name;
+	const char *const *parents;
+	int num_parents;
+	int clk_id;
+	u8 mux_shift;
+	u8 gate_shift;
+};
+
+static const char * const clk_out1_parents[] = { "osc", "osc_div2",
+	"osc_div4", "extern1",
+};
+
+static const char * const clk_out2_parents[] = { "osc", "osc_div2",
+	"osc_div4", "extern2",
+};
+
+static const char * const clk_out3_parents[] = { "osc", "osc_div2",
+	"osc_div4", "extern3",
+};
+
+static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
+	{
+		.name = "clk_out_1",
+		.parents = clk_out1_parents,
+		.num_parents = ARRAY_SIZE(clk_out1_parents),
+		.clk_id = TEGRA_PMC_CLK_OUT_1,
+		.mux_shift = 6,
+		.gate_shift = 2,
+	},
+	{
+		.name = "clk_out_2",
+		.parents = clk_out2_parents,
+		.num_parents = ARRAY_SIZE(clk_out2_parents),
+		.clk_id = TEGRA_PMC_CLK_OUT_2,
+		.mux_shift = 14,
+		.gate_shift = 10,
+	},
+	{
+		.name = "clk_out_3",
+		.parents = clk_out3_parents,
+		.num_parents = ARRAY_SIZE(clk_out3_parents),
+		.clk_id = TEGRA_PMC_CLK_OUT_3,
+		.mux_shift = 22,
+		.gate_shift = 18,
+	},
+};
+
 struct tegra_powergate {
 	struct generic_pm_domain genpd;
 	struct tegra_pmc *pmc;
@@ -254,6 +317,9 @@ struct tegra_pmc_soc {
 	 */
 	const struct tegra_wake_event *wake_events;
 	unsigned int num_wake_events;
+
+	const struct pmc_clk_init_data *pmc_clks_data;
+	unsigned int num_pmc_clks;
 };
 
 static const char * const tegra186_reset_sources[] = {
@@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
 	return NOTIFY_OK;
 }
 
+static void pmc_clk_fence_udelay(u32 offset)
+{
+	tegra_pmc_readl(pmc, offset);
+	/* pmc clk propagation delay 2 us */
+	udelay(2);
+}
+
+static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
+{
+	struct pmc_clk *clk = to_pmc_clk(hw);
+	u32 val;
+
+	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
+	val &= clk->mux_mask;
+
+	return val;
+}
+
+static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct pmc_clk *clk = to_pmc_clk(hw);
+	u32 val;
+
+	val = tegra_pmc_readl(pmc, clk->offs);
+	val &= ~(clk->mux_mask << clk->mux_shift);
+	val |= index << clk->mux_shift;
+	tegra_pmc_writel(pmc, val, clk->offs);
+	pmc_clk_fence_udelay(clk->offs);
+
+	return 0;
+}
+
+static int pmc_clk_is_enabled(struct clk_hw *hw)
+{
+	struct pmc_clk *clk = to_pmc_clk(hw);
+
+	return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift) ? 1 : 0;
+}
+
+static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
+{
+	u32 val;
+
+	val = tegra_pmc_readl(pmc, offs);
+	val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
+	tegra_pmc_writel(pmc, val, offs);
+	pmc_clk_fence_udelay(offs);
+}
+
+static int pmc_clk_enable(struct clk_hw *hw)
+{
+	struct pmc_clk *clk = to_pmc_clk(hw);
+
+	pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
+
+	return 0;
+}
+
+static void pmc_clk_disable(struct clk_hw *hw)
+{
+	struct pmc_clk *clk = to_pmc_clk(hw);
+
+	pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
+}
+
+static const struct clk_ops pmc_clk_ops = {
+	.get_parent = pmc_clk_mux_get_parent,
+	.set_parent = pmc_clk_mux_set_parent,
+	.determine_rate = __clk_mux_determine_rate,
+	.is_enabled = pmc_clk_is_enabled,
+	.enable = pmc_clk_enable,
+	.disable = pmc_clk_disable,
+};
+
+static struct clk *
+tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
+			   unsigned long offset)
+{
+	struct clk_init_data init;
+	struct pmc_clk *pmc_clk;
+
+	pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
+	if (!pmc_clk)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = data->name;
+	init.ops = &pmc_clk_ops;
+	init.parent_names = data->parents;
+	init.num_parents = data->num_parents;
+	init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
+		     CLK_SET_PARENT_GATE;
+
+	pmc_clk->hw.init = &init;
+	pmc_clk->offs = offset;
+	pmc_clk->mux_mask = 3;
+	pmc_clk->mux_shift = data->mux_shift;
+	pmc_clk->gate_shift = data->gate_shift;
+
+	return clk_register(NULL, &pmc_clk->hw);
+}
+
+static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
+				     struct device_node *np)
+{
+	struct clk *clk;
+	struct clk_onecell_data *clk_data;
+	unsigned int num_clks;
+	int i, err = -ENOMEM;
+
+	num_clks = pmc->soc->num_pmc_clks;
+
+	if (!num_clks)
+		return;
+
+	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
+	if (!clk_data)
+		goto err_clk;
+
+	clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX, sizeof(*clk_data->clks),
+				 GFP_KERNEL);
+	if (!clk_data->clks)
+		goto free_clkdata;
+
+	clk_data->clk_num = TEGRA_PMC_CLK_MAX;
+
+	for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
+		clk_data->clks[i] = ERR_PTR(-ENOENT);
+
+	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
+		const struct pmc_clk_init_data *data;
+
+		data = pmc->soc->pmc_clks_data + i;
+
+		clk = tegra_pmc_clk_out_register(data, PMC_CLK_OUT_CNTRL);
+		if (IS_ERR(clk)) {
+			dev_err(pmc->dev,
+				"unable to register %s\n", data->name);
+			err = PTR_ERR(clk);
+			goto free_clks;
+		}
+
+		clk_data->clks[data->clk_id] = clk;
+		err = clk_register_clkdev(clk, data->name, NULL);
+		if (err) {
+			dev_err(pmc->dev,
+				"unable to register %s clock lookup\n",
+				data->name);
+			goto free_clks;
+		}
+	}
+
+	err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+	if (err) {
+		dev_err(pmc->dev, "failed to add pmc clk provider\n");
+		goto free_clks;
+	}
+
+	return;
+
+free_clks:
+	kfree(clk_data->clks);
+free_clkdata:
+	kfree(clk_data);
+err_clk:
+	WARN(1, "failed to register Tegra PMC clocks: %d\n", err);
+}
+
 static int tegra_pmc_probe(struct platform_device *pdev)
 {
 	void __iomem *base;
@@ -2281,6 +2514,7 @@ static int tegra_pmc_probe(struct platform_device *pdev)
 	pmc->base = base;
 	mutex_unlock(&pmc->powergates_lock);
 
+	tegra_pmc_clock_register(pmc, pdev->dev.of_node);
 	platform_set_drvdata(pdev, pmc);
 
 	return 0;
@@ -2422,6 +2656,8 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
 	.num_reset_sources = 0,
 	.reset_levels = NULL,
 	.num_reset_levels = 0,
+	.pmc_clks_data = NULL,
+	.num_pmc_clks = 0,
 };
 
 static const char * const tegra30_powergates[] = {
@@ -2469,6 +2705,8 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
 	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
 	.reset_levels = NULL,
 	.num_reset_levels = 0,
+	.pmc_clks_data = tegra_pmc_clks_data,
+	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
 };
 
 static const char * const tegra114_powergates[] = {
@@ -2520,6 +2758,8 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
 	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
 	.reset_levels = NULL,
 	.num_reset_levels = 0,
+	.pmc_clks_data = tegra_pmc_clks_data,
+	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
 };
 
 static const char * const tegra124_powergates[] = {
@@ -2631,6 +2871,8 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
 	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
 	.reset_levels = NULL,
 	.num_reset_levels = 0,
+	.pmc_clks_data = tegra_pmc_clks_data,
+	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
 };
 
 static const char * const tegra210_powergates[] = {
@@ -2745,6 +2987,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
 	.num_reset_levels = 0,
 	.num_wake_events = ARRAY_SIZE(tegra210_wake_events),
 	.wake_events = tegra210_wake_events,
+	.pmc_clks_data = tegra_pmc_clks_data,
+	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
 };
 
 #define TEGRA186_IO_PAD_TABLE(_pad)					     \
@@ -2874,6 +3118,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
 	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
 	.num_wake_events = ARRAY_SIZE(tegra186_wake_events),
 	.wake_events = tegra186_wake_events,
+	.pmc_clks_data = NULL,
+	.num_pmc_clks = 0,
 };
 
 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
@@ -2991,6 +3237,8 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {
 	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
 	.num_wake_events = ARRAY_SIZE(tegra194_wake_events),
 	.wake_events = tegra194_wake_events,
+	.pmc_clks_data = NULL,
+	.num_pmc_clks = 0,
 };
 
 static const struct of_device_id tegra_pmc_match[] = {
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 07/19] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (5 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-18 21:30   ` Rob Herring
  2019-12-17 20:03 ` [PATCH v4 08/19] soc: tegra: Add support for " Sowjanya Komatineni
                   ` (11 subsequent siblings)
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra PMC has blink functionality that allows 32KHz clock out to
blink pin of the Tegra.

This patch adds id for this blink clock to use for enabling or
disabling blink output through device tree.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 include/dt-bindings/soc/tegra-pmc.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h
index f7c866404456..a99a457471ee 100644
--- a/include/dt-bindings/soc/tegra-pmc.h
+++ b/include/dt-bindings/soc/tegra-pmc.h
@@ -9,7 +9,8 @@
 #define TEGRA_PMC_CLK_OUT_1		0
 #define TEGRA_PMC_CLK_OUT_2		1
 #define TEGRA_PMC_CLK_OUT_3		2
+#define TEGRA_PMC_CLK_BLINK		3
 
-#define TEGRA_PMC_CLK_MAX		3
+#define TEGRA_PMC_CLK_MAX		4
 
 #endif	/* _DT_BINDINGS_SOC_TEGRA_PMC_H */
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 08/19] soc: tegra: Add support for 32KHz blink clock
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (6 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 07/19] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-18  5:08   ` Dmitry Osipenko
  2019-12-17 20:03 ` [PATCH v4 09/19] clk: tegra: Remove tegra_pmc_clk_init along with clk ids Sowjanya Komatineni
                   ` (10 subsequent siblings)
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra PMC has blink control to output 32 Khz clock out to Tegra
blink pin. Blink pad DPD state and enable controls are part of
Tegra PMC register space.

Currently Tegra clock driver registers blink control by passing
PMC address and register offset to clk_register_gate which performs
direct PMC access during clk_ops and with this when PMC is in secure
mode, any access from non-secure world does not go through.

This patch adds blink control registration to the Tegra PMC driver
using PMC specific clock gate operations that use tegra_pmc_readl
and tegra_pmc_writel to support both secure mode and non-secure
mode PMC register access.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/soc/tegra/pmc.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 6d65194a6e71..19996c21c60d 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -61,12 +61,15 @@
 #define  PMC_CNTRL_SYSCLK_OE		BIT(11) /* system clock enable */
 #define  PMC_CNTRL_SYSCLK_POLARITY	BIT(10) /* sys clk polarity */
 #define  PMC_CNTRL_PWRREQ_POLARITY	BIT(8)
+#define  PMC_CNTRL_BLINK_EN		7
 #define  PMC_CNTRL_MAIN_RST		BIT(4)
 
 #define PMC_WAKE_MASK			0x0c
 #define PMC_WAKE_LEVEL			0x10
 #define PMC_WAKE_STATUS			0x14
 #define PMC_SW_WAKE_STATUS		0x18
+#define PMC_DPD_PADS_ORIDE		0x1c
+#define  PMC_DPD_PADS_ORIDE_BLINK	20
 
 #define DPD_SAMPLE			0x020
 #define  DPD_SAMPLE_ENABLE		BIT(0)
@@ -79,6 +82,7 @@
 
 #define PWRGATE_STATUS			0x38
 
+#define PMC_BLINK_TIMER			0x40
 #define PMC_IMPL_E_33V_PWR		0x40
 
 #define PMC_PWR_DET			0x48
@@ -170,6 +174,14 @@ struct pmc_clk {
 
 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
 
+struct pmc_clk_gate {
+	struct clk_hw	hw;
+	unsigned long	offs;
+	u32		shift;
+};
+
+#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
+
 struct pmc_clk_init_data {
 	char *name;
 	const char *const *parents;
@@ -320,6 +332,7 @@ struct tegra_pmc_soc {
 
 	const struct pmc_clk_init_data *pmc_clks_data;
 	unsigned int num_pmc_clks;
+	bool has_blink_output;
 };
 
 static const char * const tegra186_reset_sources[] = {
@@ -2330,6 +2343,60 @@ tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
 	return clk_register(NULL, &pmc_clk->hw);
 }
 
+static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
+{
+	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
+
+	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
+}
+
+static int pmc_clk_gate_enable(struct clk_hw *hw)
+{
+	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
+
+	pmc_clk_set_state(gate->offs, gate->shift, 1);
+
+	return 0;
+}
+
+static void pmc_clk_gate_disable(struct clk_hw *hw)
+{
+	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
+
+	pmc_clk_set_state(gate->offs, gate->shift, 0);
+}
+
+static const struct clk_ops pmc_clk_gate_ops = {
+	.is_enabled = pmc_clk_gate_is_enabled,
+	.enable = pmc_clk_gate_enable,
+	.disable = pmc_clk_gate_disable,
+};
+
+static struct clk *
+tegra_pmc_clk_gate_register(const char *name, const char *parent_name,
+			    unsigned long flags, unsigned long offset,
+			    u32 shift)
+{
+	struct clk_init_data init;
+	struct pmc_clk_gate *gate;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	init.ops = &pmc_clk_gate_ops;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+	init.flags = flags;
+
+	gate->hw.init = &init;
+	gate->offs = offset;
+	gate->shift = shift;
+
+	return clk_register(NULL, &gate->hw);
+}
+
 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
 				     struct device_node *np)
 {
@@ -2339,6 +2406,8 @@ static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
 	int i, err = -ENOMEM;
 
 	num_clks = pmc->soc->num_pmc_clks;
+	if (pmc->soc->has_blink_output)
+		num_clks += 1;
 
 	if (!num_clks)
 		return;
@@ -2380,6 +2449,37 @@ static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
 		}
 	}
 
+	if (pmc->soc->has_blink_output) {
+		tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
+		clk = tegra_pmc_clk_gate_register("blink_override",
+						  "clk_32k", 0,
+						  PMC_DPD_PADS_ORIDE,
+						  PMC_DPD_PADS_ORIDE_BLINK);
+		if (IS_ERR(clk)) {
+			dev_err(pmc->dev, "unable to register blink_override\n");
+			err = PTR_ERR(clk);
+			goto free_clks;
+		}
+
+		clk = tegra_pmc_clk_gate_register("blink",
+						  "blink_override", 0,
+						  PMC_CNTRL,
+						  PMC_CNTRL_BLINK_EN);
+		if (IS_ERR(clk)) {
+			dev_err(pmc->dev, "unable to register blink\n");
+			err = PTR_ERR(clk);
+			goto free_clks;
+		}
+
+		clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
+		err = clk_register_clkdev(clk, "blink", NULL);
+		if (err) {
+			dev_err(pmc->dev,
+				"unable to register blink clock lookup\n");
+			goto free_clks;
+		}
+	}
+
 	err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
 	if (err) {
 		dev_err(pmc->dev, "failed to add pmc clk provider\n");
@@ -2658,6 +2758,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
 	.num_reset_levels = 0,
 	.pmc_clks_data = NULL,
 	.num_pmc_clks = 0,
+	.has_blink_output = true,
 };
 
 static const char * const tegra30_powergates[] = {
@@ -2707,6 +2808,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
 	.num_reset_levels = 0,
 	.pmc_clks_data = tegra_pmc_clks_data,
 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
+	.has_blink_output = true,
 };
 
 static const char * const tegra114_powergates[] = {
@@ -2760,6 +2862,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
 	.num_reset_levels = 0,
 	.pmc_clks_data = tegra_pmc_clks_data,
 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
+	.has_blink_output = true,
 };
 
 static const char * const tegra124_powergates[] = {
@@ -2873,6 +2976,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
 	.num_reset_levels = 0,
 	.pmc_clks_data = tegra_pmc_clks_data,
 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
+	.has_blink_output = true,
 };
 
 static const char * const tegra210_powergates[] = {
@@ -2989,6 +3093,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
 	.wake_events = tegra210_wake_events,
 	.pmc_clks_data = tegra_pmc_clks_data,
 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
+	.has_blink_output = true,
 };
 
 #define TEGRA186_IO_PAD_TABLE(_pad)					     \
@@ -3120,6 +3225,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
 	.wake_events = tegra186_wake_events,
 	.pmc_clks_data = NULL,
 	.num_pmc_clks = 0,
+	.has_blink_output = false,
 };
 
 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
@@ -3239,6 +3345,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {
 	.wake_events = tegra194_wake_events,
 	.pmc_clks_data = NULL,
 	.num_pmc_clks = 0,
+	.has_blink_output = false,
 };
 
 static const struct of_device_id tegra_pmc_match[] = {
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 09/19] clk: tegra: Remove tegra_pmc_clk_init along with clk ids
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (7 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 08/19] soc: tegra: Add support for " Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-17 20:03 ` [PATCH v4 10/19] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings Sowjanya Komatineni
                   ` (9 subsequent siblings)
  18 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2,
clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct
PMC register access during clk_ops and these PMC register read and write
access will not happen when PMC is in secure mode.

Any direct PMC register access from non-secure world will not go
through.

All the PMC clocks are moved to Tegra PMC driver with PMC as a clock
provider.

This patch removes tegra_pmc_clk_init along with corresponding clk ids
from Tegra clock driver.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/clk/tegra/Makefile        |   1 -
 drivers/clk/tegra/clk-id.h        |   7 ---
 drivers/clk/tegra/clk-tegra-pmc.c | 122 --------------------------------------
 drivers/clk/tegra/clk-tegra114.c  |  17 +-----
 drivers/clk/tegra/clk-tegra124.c  |  33 ++++-------
 drivers/clk/tegra/clk-tegra20.c   |   4 --
 drivers/clk/tegra/clk-tegra210.c  |  17 +-----
 drivers/clk/tegra/clk-tegra30.c   |  18 +-----
 drivers/clk/tegra/clk.h           |   1 -
 9 files changed, 19 insertions(+), 201 deletions(-)
 delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index df966ca06788..1f7c30f87ece 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -12,7 +12,6 @@ obj-y					+= clk-sdmmc-mux.o
 obj-y					+= clk-super.o
 obj-y					+= clk-tegra-audio.o
 obj-y					+= clk-tegra-periph.o
-obj-y					+= clk-tegra-pmc.o
 obj-y					+= clk-tegra-fixed.o
 obj-y					+= clk-tegra-super-gen4.o
 obj-$(CONFIG_TEGRA_CLK_EMC)		+= clk-emc.o
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 1bf21766d3e8..c82f8ce9e93e 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -32,7 +32,6 @@ enum clk_id {
 	tegra_clk_audio4,
 	tegra_clk_audio4_2x,
 	tegra_clk_audio4_mux,
-	tegra_clk_blink,
 	tegra_clk_bsea,
 	tegra_clk_bsev,
 	tegra_clk_cclk_g,
@@ -46,12 +45,6 @@ enum clk_id {
 	tegra_clk_clk_m,
 	tegra_clk_osc_div2,
 	tegra_clk_osc_div4,
-	tegra_clk_clk_out_1,
-	tegra_clk_clk_out_1_mux,
-	tegra_clk_clk_out_2,
-	tegra_clk_clk_out_2_mux,
-	tegra_clk_clk_out_3,
-	tegra_clk_clk_out_3_mux,
 	tegra_clk_cml0,
 	tegra_clk_cml1,
 	tegra_clk_csi,
diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
deleted file mode 100644
index 5e044ba1ae36..000000000000
--- a/drivers/clk/tegra/clk-tegra-pmc.c
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
- */
-
-#include <linux/io.h>
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-#include <linux/clk/tegra.h>
-
-#include "clk.h"
-#include "clk-id.h"
-
-#define PMC_CLK_OUT_CNTRL 0x1a8
-#define PMC_DPD_PADS_ORIDE 0x1c
-#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
-#define PMC_CTRL 0
-#define PMC_CTRL_BLINK_ENB 7
-#define PMC_BLINK_TIMER 0x40
-
-struct pmc_clk_init_data {
-	char *mux_name;
-	char *gate_name;
-	const char **parents;
-	int num_parents;
-	int mux_id;
-	int gate_id;
-	char *dev_name;
-	u8 mux_shift;
-	u8 gate_shift;
-};
-
-#define PMC_CLK(_num, _mux_shift, _gate_shift)\
-	{\
-		.mux_name = "clk_out_" #_num "_mux",\
-		.gate_name = "clk_out_" #_num,\
-		.parents = clk_out ##_num ##_parents,\
-		.num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
-		.mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
-		.gate_id = tegra_clk_clk_out_ ##_num,\
-		.dev_name = "extern" #_num,\
-		.mux_shift = _mux_shift,\
-		.gate_shift = _gate_shift,\
-	}
-
-static DEFINE_SPINLOCK(clk_out_lock);
-
-static const char *clk_out1_parents[] = { "osc", "osc_div2",
-	"osc_div4", "extern1",
-};
-
-static const char *clk_out2_parents[] = { "osc", "osc_div2",
-	"osc_div4", "extern2",
-};
-
-static const char *clk_out3_parents[] = { "osc", "osc_div2",
-	"osc_div4", "extern3",
-};
-
-static struct pmc_clk_init_data pmc_clks[] = {
-	PMC_CLK(1, 6, 2),
-	PMC_CLK(2, 14, 10),
-	PMC_CLK(3, 22, 18),
-};
-
-void __init tegra_pmc_clk_init(void __iomem *pmc_base,
-				struct tegra_clk *tegra_clks)
-{
-	struct clk *clk;
-	struct clk **dt_clk;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
-		struct pmc_clk_init_data *data;
-
-		data = pmc_clks + i;
-
-		dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
-		if (!dt_clk)
-			continue;
-
-		clk = clk_register_mux(NULL, data->mux_name, data->parents,
-				data->num_parents,
-				CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
-				pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
-				3, 0, &clk_out_lock);
-		*dt_clk = clk;
-
-
-		dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
-		if (!dt_clk)
-			continue;
-
-		clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
-					CLK_SET_RATE_PARENT,
-					pmc_base + PMC_CLK_OUT_CNTRL,
-					data->gate_shift, 0, &clk_out_lock);
-		*dt_clk = clk;
-		clk_register_clkdev(clk, data->dev_name, data->gate_name);
-	}
-
-	/* blink */
-	writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
-	clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
-				pmc_base + PMC_DPD_PADS_ORIDE,
-				PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
-
-	dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
-	if (!dt_clk)
-		return;
-
-	clk = clk_register_gate(NULL, "blink", "blink_override", 0,
-				pmc_base + PMC_CTRL,
-				PMC_CTRL_BLINK_ENB, 0, NULL);
-	clk_register_clkdev(clk, "blink", NULL);
-	*dt_clk = clk;
-}
-
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 9d2ca387114c..4077dd3a1bd9 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -778,10 +778,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
 	[tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
 	[tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
-	[tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
-	[tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
-	[tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
-	[tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
 	[tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
 	[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
 	[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
@@ -803,9 +799,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
 	[tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
 	[tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
-	[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
-	[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
-	[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
 	[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
 	[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
 	[tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
@@ -863,10 +856,9 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
 	{ .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
 	{ .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
-	{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
-	{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
-	{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
-	{ .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
+	{ .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
+	{ .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
+	{ .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
 	{ .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
 	{ .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
 	{ .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
@@ -1145,8 +1137,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
 	{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
 	{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
-	{ TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
-	{ TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1348,7 +1338,6 @@ static void __init tegra114_clock_init(struct device_node *np)
 	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
 			     tegra114_audio_plls,
 			     ARRAY_SIZE(tegra114_audio_plls), 24000000);
-	tegra_pmc_clk_init(pmc_base, tegra114_clks);
 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
 					&pll_x_params);
 
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 15f42718f4cb..266a0c040933 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -902,10 +902,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
 	[tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
 	[tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
-	[tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
-	[tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
-	[tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
-	[tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
 	[tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
 	[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
 	[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
@@ -931,9 +927,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
 	[tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
 	[tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
-	[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
-	[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
-	[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
 	[tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
 };
 
@@ -988,10 +981,9 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
 	{ .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
 	{ .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
-	{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
-	{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
-	{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
-	{ .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
+	{ .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },
+	{ .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },
+	{ .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },
 	{ .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
 	{ .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
 	{ .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
@@ -1301,8 +1293,6 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
 	{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
 	{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
 	{ TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
-	{ TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
-	{ TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1457,11 +1447,9 @@ static void __init tegra132_clock_apply_init_table(void)
  * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
  * @np: struct device_node * of the DT node for the SoC CAR IP block
  *
- * Register most of the clocks controlled by the CAR IP block, along
- * with a few clocks controlled by the PMC IP block.  Everything in
- * this function should be common to Tegra124 and Tegra132.  XXX The
- * PMC clock initialization should probably be moved to PMC-specific
- * driver code.  No return value.
+ * Register most of the clocks controlled by the CAR IP block.
+ * Everything in this function should be common to Tegra124 and Tegra132.
+ * No return value.
  */
 static void __init tegra124_132_clock_init_pre(struct device_node *np)
 {
@@ -1504,7 +1492,6 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
 	tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
 			     tegra124_audio_plls,
 			     ARRAY_SIZE(tegra124_audio_plls), 24576000);
-	tegra_pmc_clk_init(pmc_base, tegra124_clks);
 
 	/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
 	plld_base = readl(clk_base + PLLD_BASE);
@@ -1516,11 +1503,11 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
  * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
  * @np: struct device_node * of the DT node for the SoC CAR IP block
  *
- * Register most of the along with a few clocks controlled by the PMC
- * IP block.  Everything in this function should be common to Tegra124
+ * Register most of the clocks controlled by the CAR IP block.
+ * Everything in this function should be common to Tegra124
  * and Tegra132.  This function must be called after
- * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
- * not be set.  No return value.
+ * tegra124_132_clock_init_pre(), otherwise clk_base will not be set.
+ * No return value.
  */
 static void __init tegra124_132_clock_init_post(struct device_node *np)
 {
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 4d8222f5c638..fe536f1d770d 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -458,7 +458,6 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
 	{ .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
 	{ .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
-	{ .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
 	{ .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
 	{ .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
 	{ .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
@@ -537,7 +536,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
 	[tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
 	[tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
-	[tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
 	[tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
 	[tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
 	[tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
@@ -1034,7 +1032,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
 	{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
 	{ TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
-	{ TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
 	{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
@@ -1148,7 +1145,6 @@ static void __init tegra20_clock_init(struct device_node *np)
 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
 	tegra20_periph_clk_init();
 	tegra20_audio_clk_init();
-	tegra_pmc_clk_init(pmc_base, tegra20_clks);
 
 	tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
 
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 5687fcda620e..39dbfad73bf9 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2417,10 +2417,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
 	[tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
 	[tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
-	[tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
-	[tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
-	[tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
-	[tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
 	[tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
 	[tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
 	[tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
@@ -2452,9 +2448,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
 	[tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
 	[tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
-	[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
-	[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
-	[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
 	[tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
 	[tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
 	[tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
@@ -2540,10 +2533,9 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
 	{ .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
 	{ .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
-	{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
-	{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
-	{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
-	{ .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
+	{ .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
+	{ .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
+	{ .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
 	{ .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
 	{ .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
 	{ .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
@@ -3451,8 +3443,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
 	{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
 	{ TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
-	{ TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
-	{ TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -3693,7 +3683,6 @@ static void __init tegra210_clock_init(struct device_node *np)
 	tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
 			     tegra210_audio_plls,
 			     ARRAY_SIZE(tegra210_audio_plls), 24576000);
-	tegra_pmc_clk_init(pmc_base, tegra210_clks);
 
 	/* For Tegra210, PLLD is the only source for DSIA & DSIB */
 	value = readl(clk_base + PLLD_BASE);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 1322188edb72..7bbdb5a4dec4 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -569,10 +569,9 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
 	{ .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
 	{ .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
-	{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
-	{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
-	{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
-	{ .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
+	{ .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
+	{ .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
+	{ .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
 	{ .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
 	{ .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
 	{ .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
@@ -711,13 +710,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
 	[tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
 	[tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
-	[tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
-	[tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
-	[tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
-	[tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
-	[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
-	[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
-	[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
 	[tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
 	[tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
 	[tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
@@ -1230,9 +1222,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
 	{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
 	{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
-	{ TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
-	{ TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
-	{ TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1364,7 +1353,6 @@ static void __init tegra30_clock_init(struct device_node *np)
 	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
 			     tegra30_audio_plls,
 			     ARRAY_SIZE(tegra30_audio_plls), 24000000);
-	tegra_pmc_clk_init(pmc_base, tegra30_clks);
 
 	tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
 
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 416a6b09f6a3..2c9a68302e02 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -854,7 +854,6 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
 			struct tegra_clk *tegra_clks,
 			struct tegra_clk_pll_params *pll_params);
 
-void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
 		       unsigned long *input_freqs, unsigned int num,
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 10/19] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (8 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 09/19] clk: tegra: Remove tegra_pmc_clk_init along with clk ids Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-18 21:32   ` Rob Herring
  2019-12-17 20:03 ` [PATCH v4 11/19] ASoC: tegra: Use device managed resource APIs to get the clock Sowjanya Komatineni
                   ` (8 subsequent siblings)
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block and
these clocks are moved to Tegra PMC driver with pmc as clock provider
and uses clock ids from dt-bindings/soc/tegra-pmc.h

So, this patch removes ids for these clocks from Tegra clock dt-bindings.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 include/dt-bindings/clock/tegra114-car.h        | 14 +++++++-------
 include/dt-bindings/clock/tegra124-car-common.h | 14 +++++++-------
 include/dt-bindings/clock/tegra20-car.h         |  2 +-
 include/dt-bindings/clock/tegra210-car.h        | 14 +++++++-------
 include/dt-bindings/clock/tegra30-car.h         | 14 +++++++-------
 5 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index f4880959b094..2818ba12e1f7 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -270,10 +270,10 @@
 #define TEGRA114_CLK_AUDIO3 242
 #define TEGRA114_CLK_AUDIO4 243
 #define TEGRA114_CLK_SPDIF 244
-#define TEGRA114_CLK_CLK_OUT_1 245
-#define TEGRA114_CLK_CLK_OUT_2 246
-#define TEGRA114_CLK_CLK_OUT_3 247
-#define TEGRA114_CLK_BLINK 248
+/* 245 */
+/* 246 */
+/* 247 */
+/* 248 */
 /* 249 */
 /* 250 */
 /* 251 */
@@ -333,9 +333,9 @@
 #define TEGRA114_CLK_AUDIO3_MUX 303
 #define TEGRA114_CLK_AUDIO4_MUX 304
 #define TEGRA114_CLK_SPDIF_MUX 305
-#define TEGRA114_CLK_CLK_OUT_1_MUX 306
-#define TEGRA114_CLK_CLK_OUT_2_MUX 307
-#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+/* 306 */
+/* 307 */
+/* 308 */
 #define TEGRA114_CLK_DSIA_MUX 309
 #define TEGRA114_CLK_DSIB_MUX 310
 #define TEGRA114_CLK_XUSB_SS_DIV2 311
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index e7e601a88d3d..366bac3043f2 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -269,10 +269,10 @@
 #define TEGRA124_CLK_AUDIO3 242
 #define TEGRA124_CLK_AUDIO4 243
 #define TEGRA124_CLK_SPDIF 244
-#define TEGRA124_CLK_CLK_OUT_1 245
-#define TEGRA124_CLK_CLK_OUT_2 246
-#define TEGRA124_CLK_CLK_OUT_3 247
-#define TEGRA124_CLK_BLINK 248
+/* 245 */
+/* 246 */
+/* 247 */
+/* 248 */
 /* 249 */
 /* 250 */
 /* 251 */
@@ -332,9 +332,9 @@
 #define TEGRA124_CLK_AUDIO3_MUX 303
 #define TEGRA124_CLK_AUDIO4_MUX 304
 #define TEGRA124_CLK_SPDIF_MUX 305
-#define TEGRA124_CLK_CLK_OUT_1_MUX 306
-#define TEGRA124_CLK_CLK_OUT_2_MUX 307
-#define TEGRA124_CLK_CLK_OUT_3_MUX 308
+/* 306 */
+/* 307 */
+/* 308 */
 /* 309 */
 /* 310 */
 #define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index b21a0eb32921..fe541f627965 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -131,7 +131,7 @@
 #define TEGRA20_CLK_CCLK 108
 #define TEGRA20_CLK_HCLK 109
 #define TEGRA20_CLK_PCLK 110
-#define TEGRA20_CLK_BLINK 111
+/* 111 */
 #define TEGRA20_CLK_PLL_A 112
 #define TEGRA20_CLK_PLL_A_OUT0 113
 #define TEGRA20_CLK_PLL_C 114
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 6f65c14bf013..098a73d36c33 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -304,10 +304,10 @@
 #define TEGRA210_CLK_AUDIO3 274
 #define TEGRA210_CLK_AUDIO4 275
 #define TEGRA210_CLK_SPDIF 276
-#define TEGRA210_CLK_CLK_OUT_1 277
-#define TEGRA210_CLK_CLK_OUT_2 278
-#define TEGRA210_CLK_CLK_OUT_3 279
-#define TEGRA210_CLK_BLINK 280
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
 #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
 #define TEGRA210_CLK_SOR0_OUT 281
 #define TEGRA210_CLK_SOR1_OUT 282
@@ -386,9 +386,9 @@
 #define TEGRA210_CLK_AUDIO3_MUX 353
 #define TEGRA210_CLK_AUDIO4_MUX 354
 #define TEGRA210_CLK_SPDIF_MUX 355
-#define TEGRA210_CLK_CLK_OUT_1_MUX 356
-#define TEGRA210_CLK_CLK_OUT_2_MUX 357
-#define TEGRA210_CLK_CLK_OUT_3_MUX 358
+/* 356 */
+/* 357 */
+/* 358 */
 #define TEGRA210_CLK_DSIA_MUX 359
 #define TEGRA210_CLK_DSIB_MUX 360
 /* 361 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 907a8a04c280..2a63a9c4de5c 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -230,11 +230,11 @@
 #define TEGRA30_CLK_AUDIO3 204
 #define TEGRA30_CLK_AUDIO4 205
 #define TEGRA30_CLK_SPDIF 206
-#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
-#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
-#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
+/* 207 */
+/* 208 */
+/* 209 */
 #define TEGRA30_CLK_SCLK 210
-#define TEGRA30_CLK_BLINK 211
+/* 211 */
 #define TEGRA30_CLK_CCLK_G 212
 #define TEGRA30_CLK_CCLK_LP 213
 #define TEGRA30_CLK_TWD 214
@@ -260,9 +260,9 @@
 /* 297 */
 /* 298 */
 /* 299 */
-#define TEGRA30_CLK_CLK_OUT_1_MUX 300
-#define TEGRA30_CLK_CLK_OUT_2_MUX 301
-#define TEGRA30_CLK_CLK_OUT_3_MUX 302
+/* 300 */
+/* 301 */
+/* 302 */
 #define TEGRA30_CLK_AUDIO0_MUX 303
 #define TEGRA30_CLK_AUDIO1_MUX 304
 #define TEGRA30_CLK_AUDIO2_MUX 305
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 11/19] ASoC: tegra: Use device managed resource APIs to get the clock
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (9 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 10/19] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-17 20:03 ` [PATCH v4 12/19] ASoC: tegra: Add initial parent configuration for audio mclk Sowjanya Komatineni
                   ` (7 subsequent siblings)
  18 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

tegra_asoc_utils uses clk_get() and clk_put() to get the clock
and to free them explicitly.

This patch updates it to use device managed resource API
devm_clk_get() so the clock will be automatically released and freed
when the device is unbound and removes tegra_asoc_utils_fini() as
its no longer needed.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 sound/soc/tegra/tegra_alc5632.c    |  7 +------
 sound/soc/tegra/tegra_asoc_utils.c | 34 ++++++----------------------------
 sound/soc/tegra/tegra_asoc_utils.h |  1 -
 sound/soc/tegra/tegra_max98090.c   | 22 ++++++----------------
 sound/soc/tegra/tegra_rt5640.c     | 22 ++++++----------------
 sound/soc/tegra/tegra_rt5677.c     |  7 +------
 sound/soc/tegra/tegra_sgtl5000.c   |  7 +------
 sound/soc/tegra/tegra_wm8753.c     | 22 ++++++----------------
 sound/soc/tegra/tegra_wm8903.c     | 22 ++++++----------------
 sound/soc/tegra/tegra_wm9712.c     |  8 ++------
 sound/soc/tegra/trimslice.c        | 18 ++++--------------
 11 files changed, 39 insertions(+), 131 deletions(-)

diff --git a/sound/soc/tegra/tegra_alc5632.c b/sound/soc/tegra/tegra_alc5632.c
index 9e8b1497efd3..50a6d2ff4442 100644
--- a/sound/soc/tegra/tegra_alc5632.c
+++ b/sound/soc/tegra/tegra_alc5632.c
@@ -205,13 +205,11 @@ static int tegra_alc5632_probe(struct platform_device *pdev)
 	if (ret) {
 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
 			ret);
-		goto err_fini_utils;
+		goto err_put_cpu_of_node;
 	}
 
 	return 0;
 
-err_fini_utils:
-	tegra_asoc_utils_fini(&alc5632->util_data);
 err_put_cpu_of_node:
 	of_node_put(tegra_alc5632_dai.cpus->of_node);
 	tegra_alc5632_dai.cpus->of_node = NULL;
@@ -226,12 +224,9 @@ static int tegra_alc5632_probe(struct platform_device *pdev)
 static int tegra_alc5632_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
-	struct tegra_alc5632 *machine = snd_soc_card_get_drvdata(card);
 
 	snd_soc_unregister_card(card);
 
-	tegra_asoc_utils_fini(&machine->util_data);
-
 	of_node_put(tegra_alc5632_dai.cpus->of_node);
 	tegra_alc5632_dai.cpus->of_node = NULL;
 	tegra_alc5632_dai.platforms->of_node = NULL;
diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
index 536a578e9512..38535962029c 100644
--- a/sound/soc/tegra/tegra_asoc_utils.c
+++ b/sound/soc/tegra/tegra_asoc_utils.c
@@ -175,52 +175,30 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
 		return -EINVAL;
 	}
 
-	data->clk_pll_a = clk_get(dev, "pll_a");
+	data->clk_pll_a = devm_clk_get(dev, "pll_a");
 	if (IS_ERR(data->clk_pll_a)) {
 		dev_err(data->dev, "Can't retrieve clk pll_a\n");
-		ret = PTR_ERR(data->clk_pll_a);
-		goto err;
+		return PTR_ERR(data->clk_pll_a);
 	}
 
-	data->clk_pll_a_out0 = clk_get(dev, "pll_a_out0");
+	data->clk_pll_a_out0 = devm_clk_get(dev, "pll_a_out0");
 	if (IS_ERR(data->clk_pll_a_out0)) {
 		dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
-		ret = PTR_ERR(data->clk_pll_a_out0);
-		goto err_put_pll_a;
+		return PTR_ERR(data->clk_pll_a_out0);
 	}
 
-	data->clk_cdev1 = clk_get(dev, "mclk");
+	data->clk_cdev1 = devm_clk_get(dev, "mclk");
 	if (IS_ERR(data->clk_cdev1)) {
 		dev_err(data->dev, "Can't retrieve clk cdev1\n");
-		ret = PTR_ERR(data->clk_cdev1);
-		goto err_put_pll_a_out0;
+		return PTR_ERR(data->clk_cdev1);
 	}
 
 	ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
-	if (ret)
-		goto err_put_cdev1;
 
-	return 0;
-
-err_put_cdev1:
-	clk_put(data->clk_cdev1);
-err_put_pll_a_out0:
-	clk_put(data->clk_pll_a_out0);
-err_put_pll_a:
-	clk_put(data->clk_pll_a);
-err:
 	return ret;
 }
 EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
 
-void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
-{
-	clk_put(data->clk_cdev1);
-	clk_put(data->clk_pll_a_out0);
-	clk_put(data->clk_pll_a);
-}
-EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
-
 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 MODULE_DESCRIPTION("Tegra ASoC utility code");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/tegra/tegra_asoc_utils.h b/sound/soc/tegra/tegra_asoc_utils.h
index 0c13818dee75..a34439587d59 100644
--- a/sound/soc/tegra/tegra_asoc_utils.h
+++ b/sound/soc/tegra/tegra_asoc_utils.h
@@ -34,6 +34,5 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
 int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data);
 int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
 			  struct device *dev);
-void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data);
 
 #endif
diff --git a/sound/soc/tegra/tegra_max98090.c b/sound/soc/tegra/tegra_max98090.c
index 4954a33ff46b..f554a3d4571f 100644
--- a/sound/soc/tegra/tegra_max98090.c
+++ b/sound/soc/tegra/tegra_max98090.c
@@ -218,19 +218,18 @@ static int tegra_max98090_probe(struct platform_device *pdev)
 
 	ret = snd_soc_of_parse_card_name(card, "nvidia,model");
 	if (ret)
-		goto err;
+		return ret;
 
 	ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing");
 	if (ret)
-		goto err;
+		return ret;
 
 	tegra_max98090_dai.codecs->of_node = of_parse_phandle(np,
 			"nvidia,audio-codec", 0);
 	if (!tegra_max98090_dai.codecs->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,audio-codec' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	tegra_max98090_dai.cpus->of_node = of_parse_phandle(np,
@@ -238,40 +237,31 @@ static int tegra_max98090_probe(struct platform_device *pdev)
 	if (!tegra_max98090_dai.cpus->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,i2s-controller' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	tegra_max98090_dai.platforms->of_node = tegra_max98090_dai.cpus->of_node;
 
 	ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
 	if (ret)
-		goto err;
+		return ret;
 
 	ret = snd_soc_register_card(card);
 	if (ret) {
 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
 			ret);
-		goto err_fini_utils;
+		return ret;
 	}
 
 	return 0;
-
-err_fini_utils:
-	tegra_asoc_utils_fini(&machine->util_data);
-err:
-	return ret;
 }
 
 static int tegra_max98090_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
-	struct tegra_max98090 *machine = snd_soc_card_get_drvdata(card);
 
 	snd_soc_unregister_card(card);
 
-	tegra_asoc_utils_fini(&machine->util_data);
-
 	return 0;
 }
 
diff --git a/sound/soc/tegra/tegra_rt5640.c b/sound/soc/tegra/tegra_rt5640.c
index d46915a3ec4c..5c695dfea009 100644
--- a/sound/soc/tegra/tegra_rt5640.c
+++ b/sound/soc/tegra/tegra_rt5640.c
@@ -164,19 +164,18 @@ static int tegra_rt5640_probe(struct platform_device *pdev)
 
 	ret = snd_soc_of_parse_card_name(card, "nvidia,model");
 	if (ret)
-		goto err;
+		return ret;
 
 	ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing");
 	if (ret)
-		goto err;
+		return ret;
 
 	tegra_rt5640_dai.codecs->of_node = of_parse_phandle(np,
 			"nvidia,audio-codec", 0);
 	if (!tegra_rt5640_dai.codecs->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,audio-codec' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	tegra_rt5640_dai.cpus->of_node = of_parse_phandle(np,
@@ -184,40 +183,31 @@ static int tegra_rt5640_probe(struct platform_device *pdev)
 	if (!tegra_rt5640_dai.cpus->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,i2s-controller' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	tegra_rt5640_dai.platforms->of_node = tegra_rt5640_dai.cpus->of_node;
 
 	ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
 	if (ret)
-		goto err;
+		return ret;
 
 	ret = snd_soc_register_card(card);
 	if (ret) {
 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
 			ret);
-		goto err_fini_utils;
+		return ret;
 	}
 
 	return 0;
-
-err_fini_utils:
-	tegra_asoc_utils_fini(&machine->util_data);
-err:
-	return ret;
 }
 
 static int tegra_rt5640_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
-	struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
 
 	snd_soc_unregister_card(card);
 
-	tegra_asoc_utils_fini(&machine->util_data);
-
 	return 0;
 }
 
diff --git a/sound/soc/tegra/tegra_rt5677.c b/sound/soc/tegra/tegra_rt5677.c
index 81cb6cc6236e..fb86f76728b3 100644
--- a/sound/soc/tegra/tegra_rt5677.c
+++ b/sound/soc/tegra/tegra_rt5677.c
@@ -270,13 +270,11 @@ static int tegra_rt5677_probe(struct platform_device *pdev)
 	if (ret) {
 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
 			ret);
-		goto err_fini_utils;
+		goto err_put_cpu_of_node;
 	}
 
 	return 0;
 
-err_fini_utils:
-	tegra_asoc_utils_fini(&machine->util_data);
 err_put_cpu_of_node:
 	of_node_put(tegra_rt5677_dai.cpus->of_node);
 	tegra_rt5677_dai.cpus->of_node = NULL;
@@ -291,12 +289,9 @@ static int tegra_rt5677_probe(struct platform_device *pdev)
 static int tegra_rt5677_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
-	struct tegra_rt5677 *machine = snd_soc_card_get_drvdata(card);
 
 	snd_soc_unregister_card(card);
 
-	tegra_asoc_utils_fini(&machine->util_data);
-
 	tegra_rt5677_dai.platforms->of_node = NULL;
 	of_node_put(tegra_rt5677_dai.codecs->of_node);
 	tegra_rt5677_dai.codecs->of_node = NULL;
diff --git a/sound/soc/tegra/tegra_sgtl5000.c b/sound/soc/tegra/tegra_sgtl5000.c
index e13b81d29cf3..586f56f435f4 100644
--- a/sound/soc/tegra/tegra_sgtl5000.c
+++ b/sound/soc/tegra/tegra_sgtl5000.c
@@ -156,13 +156,11 @@ static int tegra_sgtl5000_driver_probe(struct platform_device *pdev)
 	if (ret) {
 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
 			ret);
-		goto err_fini_utils;
+		goto err_put_cpu_of_node;
 	}
 
 	return 0;
 
-err_fini_utils:
-	tegra_asoc_utils_fini(&machine->util_data);
 err_put_cpu_of_node:
 	of_node_put(tegra_sgtl5000_dai.cpus->of_node);
 	tegra_sgtl5000_dai.cpus->of_node = NULL;
@@ -177,13 +175,10 @@ static int tegra_sgtl5000_driver_probe(struct platform_device *pdev)
 static int tegra_sgtl5000_driver_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
-	struct tegra_sgtl5000 *machine = snd_soc_card_get_drvdata(card);
 	int ret;
 
 	ret = snd_soc_unregister_card(card);
 
-	tegra_asoc_utils_fini(&machine->util_data);
-
 	of_node_put(tegra_sgtl5000_dai.cpus->of_node);
 	tegra_sgtl5000_dai.cpus->of_node = NULL;
 	tegra_sgtl5000_dai.platforms->of_node = NULL;
diff --git a/sound/soc/tegra/tegra_wm8753.c b/sound/soc/tegra/tegra_wm8753.c
index f6dd790dad71..f76cfdc963ed 100644
--- a/sound/soc/tegra/tegra_wm8753.c
+++ b/sound/soc/tegra/tegra_wm8753.c
@@ -127,19 +127,18 @@ static int tegra_wm8753_driver_probe(struct platform_device *pdev)
 
 	ret = snd_soc_of_parse_card_name(card, "nvidia,model");
 	if (ret)
-		goto err;
+		return ret;
 
 	ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing");
 	if (ret)
-		goto err;
+		return ret;
 
 	tegra_wm8753_dai.codecs->of_node = of_parse_phandle(np,
 			"nvidia,audio-codec", 0);
 	if (!tegra_wm8753_dai.codecs->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,audio-codec' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	tegra_wm8753_dai.cpus->of_node = of_parse_phandle(np,
@@ -147,40 +146,31 @@ static int tegra_wm8753_driver_probe(struct platform_device *pdev)
 	if (!tegra_wm8753_dai.cpus->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,i2s-controller' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	tegra_wm8753_dai.platforms->of_node = tegra_wm8753_dai.cpus->of_node;
 
 	ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
 	if (ret)
-		goto err;
+		return ret;
 
 	ret = snd_soc_register_card(card);
 	if (ret) {
 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
 			ret);
-		goto err_fini_utils;
+		return ret;
 	}
 
 	return 0;
-
-err_fini_utils:
-	tegra_asoc_utils_fini(&machine->util_data);
-err:
-	return ret;
 }
 
 static int tegra_wm8753_driver_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
-	struct tegra_wm8753 *machine = snd_soc_card_get_drvdata(card);
 
 	snd_soc_unregister_card(card);
 
-	tegra_asoc_utils_fini(&machine->util_data);
-
 	return 0;
 }
 
diff --git a/sound/soc/tegra/tegra_wm8903.c b/sound/soc/tegra/tegra_wm8903.c
index f08d3489c3cf..f5f78c3512cd 100644
--- a/sound/soc/tegra/tegra_wm8903.c
+++ b/sound/soc/tegra/tegra_wm8903.c
@@ -301,19 +301,18 @@ static int tegra_wm8903_driver_probe(struct platform_device *pdev)
 
 	ret = snd_soc_of_parse_card_name(card, "nvidia,model");
 	if (ret)
-		goto err;
+		return ret;
 
 	ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing");
 	if (ret)
-		goto err;
+		return ret;
 
 	tegra_wm8903_dai.codecs->of_node = of_parse_phandle(np,
 						"nvidia,audio-codec", 0);
 	if (!tegra_wm8903_dai.codecs->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,audio-codec' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	tegra_wm8903_dai.cpus->of_node = of_parse_phandle(np,
@@ -321,40 +320,31 @@ static int tegra_wm8903_driver_probe(struct platform_device *pdev)
 	if (!tegra_wm8903_dai.cpus->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,i2s-controller' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	tegra_wm8903_dai.platforms->of_node = tegra_wm8903_dai.cpus->of_node;
 
 	ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
 	if (ret)
-		goto err;
+		return ret;
 
 	ret = snd_soc_register_card(card);
 	if (ret) {
 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
 			ret);
-		goto err_fini_utils;
+		return ret;
 	}
 
 	return 0;
-
-err_fini_utils:
-	tegra_asoc_utils_fini(&machine->util_data);
-err:
-	return ret;
 }
 
 static int tegra_wm8903_driver_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
-	struct tegra_wm8903 *machine = snd_soc_card_get_drvdata(card);
 
 	snd_soc_unregister_card(card);
 
-	tegra_asoc_utils_fini(&machine->util_data);
-
 	return 0;
 }
 
diff --git a/sound/soc/tegra/tegra_wm9712.c b/sound/soc/tegra/tegra_wm9712.c
index b85bd9f89073..726edfa21a29 100644
--- a/sound/soc/tegra/tegra_wm9712.c
+++ b/sound/soc/tegra/tegra_wm9712.c
@@ -113,19 +113,17 @@ static int tegra_wm9712_driver_probe(struct platform_device *pdev)
 
 	ret = tegra_asoc_utils_set_ac97_rate(&machine->util_data);
 	if (ret)
-		goto asoc_utils_fini;
+		goto codec_unregister;
 
 	ret = snd_soc_register_card(card);
 	if (ret) {
 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
 			ret);
-		goto asoc_utils_fini;
+		goto codec_unregister;
 	}
 
 	return 0;
 
-asoc_utils_fini:
-	tegra_asoc_utils_fini(&machine->util_data);
 codec_unregister:
 	platform_device_del(machine->codec);
 codec_put:
@@ -140,8 +138,6 @@ static int tegra_wm9712_driver_remove(struct platform_device *pdev)
 
 	snd_soc_unregister_card(card);
 
-	tegra_asoc_utils_fini(&machine->util_data);
-
 	platform_device_unregister(machine->codec);
 
 	return 0;
diff --git a/sound/soc/tegra/trimslice.c b/sound/soc/tegra/trimslice.c
index 3f67ddd13674..e51c67092c8f 100644
--- a/sound/soc/tegra/trimslice.c
+++ b/sound/soc/tegra/trimslice.c
@@ -125,8 +125,7 @@ static int tegra_snd_trimslice_probe(struct platform_device *pdev)
 	if (!trimslice_tlv320aic23_dai.codecs->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,audio-codec' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	trimslice_tlv320aic23_dai.cpus->of_node = of_parse_phandle(np,
@@ -134,8 +133,7 @@ static int tegra_snd_trimslice_probe(struct platform_device *pdev)
 	if (!trimslice_tlv320aic23_dai.cpus->of_node) {
 		dev_err(&pdev->dev,
 			"Property 'nvidia,i2s-controller' missing or invalid\n");
-		ret = -EINVAL;
-		goto err;
+		return -EINVAL;
 	}
 
 	trimslice_tlv320aic23_dai.platforms->of_node =
@@ -143,32 +141,24 @@ static int tegra_snd_trimslice_probe(struct platform_device *pdev)
 
 	ret = tegra_asoc_utils_init(&trimslice->util_data, &pdev->dev);
 	if (ret)
-		goto err;
+		return ret;
 
 	ret = snd_soc_register_card(card);
 	if (ret) {
 		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
 			ret);
-		goto err_fini_utils;
+		return ret;
 	}
 
 	return 0;
-
-err_fini_utils:
-	tegra_asoc_utils_fini(&trimslice->util_data);
-err:
-	return ret;
 }
 
 static int tegra_snd_trimslice_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
-	struct tegra_trimslice *trimslice = snd_soc_card_get_drvdata(card);
 
 	snd_soc_unregister_card(card);
 
-	tegra_asoc_utils_fini(&trimslice->util_data);
-
 	return 0;
 }
 
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 12/19] ASoC: tegra: Add initial parent configuration for audio mclk
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (10 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 11/19] ASoC: tegra: Use device managed resource APIs to get the clock Sowjanya Komatineni
@ 2019-12-17 20:03 ` Sowjanya Komatineni
  2019-12-17 20:04 ` [PATCH v4 13/19] ASoC: tegra: Add fallback implementation " Sowjanya Komatineni
                   ` (6 subsequent siblings)
  18 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:03 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra PMC clock clk_out_1 is dedicated for audio mclk from Tegra30
through Tegra210 and currently Tegra clock driver does initial parent
configuration for audio mclk "clk_out_1" and enables them by default.

With the move of Tera PMC clocks from clock driver to Tegra PMC
driver, initial parent configuration for audio clocks are through
the device tree using assigned-clock-parents property.

Default clock parents can be specified in device tree using
assigned-clocks and assigned-clock-parents and there is no need
to have clock driver do parent configuration and enable audio related
clocks.

This patch has implementation of doing initial parent confgiuration
in audio driver when default parent configuration is not specified
in the device tree using assigned-clock properties.

This patch configures PLLA_OUT0 as parent to extern1 and extern1
as parent to clk_out_1 and uses clk_out_1 as cdev1 clock to allow
mclk control from this driver.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 sound/soc/tegra/tegra_asoc_utils.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
index 38535962029c..fe9ca8acd0fb 100644
--- a/sound/soc/tegra/tegra_asoc_utils.c
+++ b/sound/soc/tegra/tegra_asoc_utils.c
@@ -158,6 +158,7 @@ EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate);
 int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
 			  struct device *dev)
 {
+	struct clk *clk_out_1, *clk_extern1;
 	int ret;
 
 	data->dev = dev;
@@ -193,6 +194,41 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
 		return PTR_ERR(data->clk_cdev1);
 	}
 
+	/*
+	 * If clock parents are not set in DT, configure here to use clk_out_1
+	 * as mclk and extern1 as parent for Tegra30 and higher.
+	 */
+	if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) &&
+	    data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) {
+		clk_extern1 = devm_clk_get(dev, "extern1");
+		if (IS_ERR(clk_extern1)) {
+			dev_err(data->dev, "Can't retrieve clk extern1\n");
+			return PTR_ERR(clk_extern1);
+		}
+
+		ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0);
+		if (ret < 0) {
+			dev_err(data->dev,
+				"Set parent failed for clk extern1\n");
+			return ret;
+		}
+
+		clk_out_1 = devm_clk_get(dev, "clk_out_1");
+		if (IS_ERR(clk_out_1)) {
+			dev_err(data->dev, "Can't retrieve clk clk_out_1\n");
+			return PTR_ERR(clk_out_1);
+		}
+
+		ret = clk_set_parent(clk_out_1, clk_extern1);
+		if (ret < 0) {
+			dev_err(data->dev,
+				"Set parent failed for clk_out_1\n");
+			return ret;
+		}
+
+		data->clk_cdev1 = clk_out_1;
+	}
+
 	ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
 
 	return ret;
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (11 preceding siblings ...)
  2019-12-17 20:03 ` [PATCH v4 12/19] ASoC: tegra: Add initial parent configuration for audio mclk Sowjanya Komatineni
@ 2019-12-17 20:04 ` Sowjanya Komatineni
  2019-12-18  6:59   ` Dmitry Osipenko
  2019-12-17 20:04 ` [PATCH v4 14/19] clk: tegra: Remove audio related clock enables from clocks init_table Sowjanya Komatineni
                   ` (5 subsequent siblings)
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:04 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
are moved to Tegra PMC driver with pmc as clock provider and using pmc
clock ids.

New device tree uses clk_out_1 from pmc clock provider.

So, this patch adds implementation for mclk fallback to extern1 when
retrieving mclk returns -ENOENT to be backward compatible of new device
tree with older kernels.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
index fe9ca8acd0fb..1b88c6043082 100644
--- a/sound/soc/tegra/tegra_asoc_utils.c
+++ b/sound/soc/tegra/tegra_asoc_utils.c
@@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
 	data->clk_cdev1 = devm_clk_get(dev, "mclk");
 	if (IS_ERR(data->clk_cdev1)) {
 		dev_err(data->dev, "Can't retrieve clk cdev1\n");
-		return PTR_ERR(data->clk_cdev1);
+		if (PTR_ERR(data->clk_cdev1) != -ENOENT)
+			return PTR_ERR(data->clk_cdev1);
+		/* Fall back to extern1 */
+		data->clk_cdev1 = devm_clk_get(dev, "extern1");
+		if (IS_ERR(data->clk_cdev1)) {
+			dev_err(data->dev, "Can't retrieve clk extern1\n");
+			return PTR_ERR(data->clk_cdev1);
+		}
+
+		dev_err(data->dev, "Falling back to extern1\n");
 	}
 
 	/*
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 14/19] clk: tegra: Remove audio related clock enables from clocks init_table
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (12 preceding siblings ...)
  2019-12-17 20:04 ` [PATCH v4 13/19] ASoC: tegra: Add fallback implementation " Sowjanya Komatineni
@ 2019-12-17 20:04 ` Sowjanya Komatineni
  2019-12-17 20:04 ` [PATCH v4 15/19] ARM: dts: tegra: Add clock-cells property to pmc Sowjanya Komatineni
                   ` (4 subsequent siblings)
  18 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:04 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Current clock driver enables PLLA, cdev1 on Tegra20 and extern1 on Tegra30
and above as a part of clocks init and there is no need to have this
clock enabled during the boot.

extern1 is used as parent for clk_out_1 and clk_out_1 is dedicated
for audio mclk on Tegra30 and above Tegra platforms and these clocks
are taken care by ASoC driver.

So, this patch removes parenting and enabling extern1 from clock init
of Tegra30 and above and removes enabling cdev1 from Tegra20 clock init.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c | 5 ++---
 drivers/clk/tegra/clk-tegra124.c | 5 ++---
 drivers/clk/tegra/clk-tegra20.c  | 5 ++---
 drivers/clk/tegra/clk-tegra210.c | 5 ++---
 drivers/clk/tegra/clk-tegra30.c  | 5 ++---
 5 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 4077dd3a1bd9..5821b636deb3 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1134,9 +1134,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
-	{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
-	{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
-	{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
+	{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
+	{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
 	{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 266a0c040933..3e49d6d39af4 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1290,9 +1290,8 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
 	{ TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
-	{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
-	{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
-	{ TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
+	{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 0 },
+	{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },
 	{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index fe536f1d770d..0da402c144d8 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1029,9 +1029,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
 	{ TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
 	{ TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
-	{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
-	{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
-	{ TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
+	{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 },
+	{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
 	{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 39dbfad73bf9..1deae4f9fca7 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3440,9 +3440,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
-	{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
-	{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
-	{ TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
+	{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },
+	{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
 	{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 7bbdb5a4dec4..349acfafa8b9 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1219,9 +1219,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
 	{ TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
-	{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
-	{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
-	{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
+	{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
+	{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
 	{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
 	{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 15/19] ARM: dts: tegra: Add clock-cells property to pmc
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (13 preceding siblings ...)
  2019-12-17 20:04 ` [PATCH v4 14/19] clk: tegra: Remove audio related clock enables from clocks init_table Sowjanya Komatineni
@ 2019-12-17 20:04 ` Sowjanya Komatineni
  2019-12-18 21:36   ` Dmitry Osipenko
  2019-12-17 20:04 ` [PATCH v4 16/19] arm64: tegra: Add clock-cells property to Tegra PMC node Sowjanya Komatineni
                   ` (3 subsequent siblings)
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:04 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra PMC has clk_out_1, clk_out_2, clk_out_3, and blink clock.

These clocks are moved from clock driver to pmc driver with pmc
as the clock provider for these clocks.

This patch adds #clock-cells property with 1 clock specifier to
the Tegra PMC node in device tree.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi | 4 +++-
 arch/arm/boot/dts/tegra124.dtsi | 4 +++-
 arch/arm/boot/dts/tegra20.dtsi  | 4 +++-
 arch/arm/boot/dts/tegra30.dtsi  | 4 +++-
 4 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 0d7a6327e404..b8f12f24f314 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/memory/tegra114-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
 	compatible = "nvidia,tegra114";
@@ -514,11 +515,12 @@
 		status = "disabled";
 	};
 
-	pmc@7000e400 {
+	pmc: pmc@7000e400 {
 		compatible = "nvidia,tegra114-pmc";
 		reg = <0x7000e400 0x400>;
 		clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 	};
 
 	fuse@7000f800 {
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 413bfb981de8..d0802c4ae3bf 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/tegra124-car.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
 	compatible = "nvidia,tegra124";
@@ -595,11 +596,12 @@
 		clocks = <&tegra_car TEGRA124_CLK_RTC>;
 	};
 
-	pmc@7000e400 {
+	pmc: pmc@7000e400 {
 		compatible = "nvidia,tegra124-pmc";
 		reg = <0x0 0x7000e400 0x0 0x400>;
 		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 	};
 
 	fuse@7000f800 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9c58e7fcf5c0..85a64747bec6 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/memory/tegra20-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
 	compatible = "nvidia,tegra20";
@@ -608,11 +609,12 @@
 		status = "disabled";
 	};
 
-	pmc@7000e400 {
+	pmc: pmc@7000e400 {
 		compatible = "nvidia,tegra20-pmc";
 		reg = <0x7000e400 0x400>;
 		clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 	};
 
 	mc: memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 55ae050042ce..4d5e9d0001d3 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/memory/tegra30-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
 	compatible = "nvidia,tegra30";
@@ -714,11 +715,12 @@
 		status = "disabled";
 	};
 
-	pmc@7000e400 {
+	pmc: pmc@7000e400 {
 		compatible = "nvidia,tegra30-pmc";
 		reg = <0x7000e400 0x400>;
 		clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 	};
 
 	mc: memory-controller@7000f000 {
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 16/19] arm64: tegra: Add clock-cells property to Tegra PMC node
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (14 preceding siblings ...)
  2019-12-17 20:04 ` [PATCH v4 15/19] ARM: dts: tegra: Add clock-cells property to pmc Sowjanya Komatineni
@ 2019-12-17 20:04 ` Sowjanya Komatineni
  2019-12-17 20:04 ` [PATCH v4 17/19] ARM: tegra: Update sound node clocks in device tree Sowjanya Komatineni
                   ` (2 subsequent siblings)
  18 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:04 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra132 and Tegra210 PMC block has clk_out_1, clk_out_2, clk_out_3,
and a blink clock as a part of PMC.

These clocks are moved from clock driver to pmc driver with pmc as a
clock provider.

Clock ids for these clocks are defined in pmc dt-bindings.

This patch updated device tree to include pmc dt-binding and adds
#clock-cells property with one clock specifier to pmc node.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++-
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 631a7f77c386..5bdb4a6a6b90 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
 	compatible = "nvidia,tegra132", "nvidia,tegra124";
@@ -577,11 +578,12 @@
 		clock-names = "rtc";
 	};
 
-	pmc@7000e400 {
+	pmc: pmc@7000e400 {
 		compatible = "nvidia,tegra124-pmc";
 		reg = <0x0 0x7000e400 0x0 0x400>;
 		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 	};
 
 	fuse@7000f800 {
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 48c63256ba7f..0d0432d3b37a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/reset/tegra210-car.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
 	compatible = "nvidia,tegra210";
@@ -780,6 +781,7 @@
 		reg = <0x0 0x7000e400 0x0 0x400>;
 		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 17/19] ARM: tegra: Update sound node clocks in device tree
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (15 preceding siblings ...)
  2019-12-17 20:04 ` [PATCH v4 16/19] arm64: tegra: Add clock-cells property to Tegra PMC node Sowjanya Komatineni
@ 2019-12-17 20:04 ` Sowjanya Komatineni
  2019-12-18  6:39   ` Dmitry Osipenko
  2019-12-18  7:47   ` Dmitry Osipenko
  2019-12-17 20:04 ` [PATCH v4 18/19] arm64: tegra: smaug: Change clk_out_2 provider to pmc Sowjanya Komatineni
  2019-12-17 20:04 ` [PATCH v4 19/19] ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car " Sowjanya Komatineni
  18 siblings, 2 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:04 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

clk_out_1, clk_out_2, and clk_out_3 are part of Tegra PMC block
and are moved from clock driver to pmc driver with pmc as clock
provider.
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
	t=1576613055; bh=aZWp4sScdv8qprM+UpGS0w1DX7YelR50gFqoThf23X4=;
	h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
	 In-Reply-To:References:X-NVConfidentiality:MIME-Version:
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	b=p9EmVtuTvJK6owqo0lmnZnAvftCWc6+7Mkp/Ks9y26tKN5c4jU+I+YEAaMWoHuzd+
	 7n0vS98WNMGomj19IUXoaH49IeTgPAlqOkU57IIiL2qEnX3sYNYpl/rCRUIs7vd33t
	 LSn8tQeu9Lz+Yfl8hvXcN3sdxRQOEPDYwzWG+tVy1FCnwouTHSfBhgado2Tx/9cWgi
	 HlSWkzjvodag7mAmZtLCl5P4J+oVEJnpYnjSZKNojqszn8u651ErvnVI/VbhZwQ0G5
	 Yg8kEr8YECPk2L4MXUe8J2YmKtNyZaADOkUhjyxqMjZ2bGrB9RDm5dKNFxkWuEeSpb
	 U3nMi7MNcvBmQ==

clk_out_1 is dedicated for audio mclk on Tegra30 through Tegra210.

This patch updates device tree sound node to use clk_out_1 from
pmc provider as mclk and uses assigned-clock properties to specify
clock parents for clk_out_1 and extern1.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 arch/arm/boot/dts/tegra114-dalmore.dts      | 7 ++++++-
 arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 7 ++++++-
 arch/arm/boot/dts/tegra124-apalis.dtsi      | 7 ++++++-
 arch/arm/boot/dts/tegra124-jetson-tk1.dts   | 7 ++++++-
 arch/arm/boot/dts/tegra124-nyan.dtsi        | 7 ++++++-
 arch/arm/boot/dts/tegra124-venice2.dts      | 7 ++++++-
 arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi  | 7 ++++++-
 arch/arm/boot/dts/tegra30-apalis.dtsi       | 7 ++++++-
 arch/arm/boot/dts/tegra30-beaver.dts        | 7 ++++++-
 arch/arm/boot/dts/tegra30-cardhu.dtsi       | 7 ++++++-
 arch/arm/boot/dts/tegra30-colibri.dtsi      | 7 ++++++-
 11 files changed, 66 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 97a5c3504bbe..c1914b590f5c 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1296,7 +1296,12 @@
 
 		clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
 			 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA114_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA114_CLK_EXTERN1>;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index 0462ed2dd8b8..ac6e3dda09a6 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -2009,8 +2009,13 @@
 		nvidia,audio-codec = <&sgtl5000>;
 		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
 			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA124_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA124_CLK_EXTERN1>;
 	};
 
 	thermal-zones {
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index d1e8593ef0d9..ab3dc9494528 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -2001,8 +2001,13 @@
 		nvidia,audio-codec = <&sgtl5000>;
 		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
 			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA124_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA124_CLK_EXTERN1>;
 	};
 
 	thermal-zones {
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index d5fd642f8b77..5b69ac9d3fc3 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -2058,8 +2058,13 @@
 
 		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
 			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA124_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA124_CLK_EXTERN1>;
 	};
 
 	thermal-zones {
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index 3b10f475037f..2bb7785311d6 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -788,9 +788,14 @@
 
 		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
 			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA124_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 
+		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA124_CLK_EXTERN1>;
+
 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
 		nvidia,mic-det-gpios =
 				<&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 7309393bfced..6b2e886b8fee 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -1266,8 +1266,13 @@
 
 		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
 			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA124_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA124_CLK_EXTERN1>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
index 8b7a827d604d..136a3db93e98 100644
--- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
@@ -1189,7 +1189,12 @@
 		nvidia,audio-codec = <&sgtl5000>;
 		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
 			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA30_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA30_CLK_EXTERN1>;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index c18f6f61d764..e41c81cdfaf4 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -1171,7 +1171,12 @@
 		nvidia,audio-codec = <&sgtl5000>;
 		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
 			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA30_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA30_CLK_EXTERN1>;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index a3b0f3555cd2..5df26b0055b4 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -2111,7 +2111,12 @@
 
 		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
 			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA30_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA30_CLK_EXTERN1>;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 7ce61edd52f5..e01dfc8e2840 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -619,8 +619,13 @@
 
 		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
 			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA30_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA30_CLK_EXTERN1>;
 	};
 
 	gpio-keys {
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 1f9198bb24ff..1eeeaa66f467 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -1030,8 +1030,13 @@
 		nvidia,audio-codec = <&sgtl5000>;
 		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
 			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA30_CLK_EXTERN1>;
+			 <&pmc TEGRA_PMC_CLK_OUT_1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
+
+		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+				  <&pmc TEGRA_PMC_CLK_OUT_1>;
+		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+					 <&tegra_car TEGRA30_CLK_EXTERN1>;
 	};
 };
 
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 18/19] arm64: tegra: smaug: Change clk_out_2 provider to pmc
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (16 preceding siblings ...)
  2019-12-17 20:04 ` [PATCH v4 17/19] ARM: tegra: Update sound node clocks in device tree Sowjanya Komatineni
@ 2019-12-17 20:04 ` Sowjanya Komatineni
  2019-12-17 20:04 ` [PATCH v4 19/19] ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car " Sowjanya Komatineni
  18 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:04 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

clk_out_2 is one of the clocks from Tegra PMC block and Tegra PMC
clocks are moved from clock driver to pmc driver with pmc as clock
provider and using pmc clock ids.

This patch changes clk_out_2 provider to pmc and uses corresponding
pmc clock id for clk_out_2.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 72c7a04ac1df..4376c38d78f4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1592,7 +1592,7 @@
 			reg = <0x1a>;
 			interrupt-parent = <&gpio>;
 			interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
+			clocks = <&pmc TEGRA_PMC_CLK_OUT_2>;
 			clock-names = "mclk";
 
 			nuvoton,jkdet-enable;
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* [PATCH v4 19/19] ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car to pmc
  2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
                   ` (17 preceding siblings ...)
  2019-12-17 20:04 ` [PATCH v4 18/19] arm64: tegra: smaug: Change clk_out_2 provider to pmc Sowjanya Komatineni
@ 2019-12-17 20:04 ` Sowjanya Komatineni
  2019-12-18 21:32   ` Rob Herring
  18 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-17 20:04 UTC (permalink / raw)
  To: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

Tegra clk_out_1, clk_out_2, and clk_out_3 are part of PMC block and
these clocks are moved from clock drvier to pmc driver with pmc as
a provider for these clocks.

Update bindings document to use pmc as clock provider for clk_out_2 and
change id to pmc clock id.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 Documentation/devicetree/bindings/sound/nau8825.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/sound/nau8825.txt b/Documentation/devicetree/bindings/sound/nau8825.txt
index d16d96839bcb..487eb9574ee2 100644
--- a/Documentation/devicetree/bindings/sound/nau8825.txt
+++ b/Documentation/devicetree/bindings/sound/nau8825.txt
@@ -101,5 +101,5 @@ Example:
       nuvoton,crosstalk-enable;
 
       clock-names = "mclk";
-      clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
+      clocks = <&pmc TEGRA_PMC_CLK_OUT_2>;
   };
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 08/19] soc: tegra: Add support for 32KHz blink clock
  2019-12-17 20:03 ` [PATCH v4 08/19] soc: tegra: Add support for " Sowjanya Komatineni
@ 2019-12-18  5:08   ` Dmitry Osipenko
  0 siblings, 0 replies; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  5:08 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

17.12.2019 23:03, Sowjanya Komatineni пишет:
> Tegra PMC has blink control to output 32 Khz clock out to Tegra
> blink pin. Blink pad DPD state and enable controls are part of
> Tegra PMC register space.
> 
> Currently Tegra clock driver registers blink control by passing
> PMC address and register offset to clk_register_gate which performs
> direct PMC access during clk_ops and with this when PMC is in secure
> mode, any access from non-secure world does not go through.
> 
> This patch adds blink control registration to the Tegra PMC driver
> using PMC specific clock gate operations that use tegra_pmc_readl
> and tegra_pmc_writel to support both secure mode and non-secure
> mode PMC register access.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  drivers/soc/tegra/pmc.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 107 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index 6d65194a6e71..19996c21c60d 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -61,12 +61,15 @@
>  #define  PMC_CNTRL_SYSCLK_OE		BIT(11) /* system clock enable */
>  #define  PMC_CNTRL_SYSCLK_POLARITY	BIT(10) /* sys clk polarity */
>  #define  PMC_CNTRL_PWRREQ_POLARITY	BIT(8)
> +#define  PMC_CNTRL_BLINK_EN		7
>  #define  PMC_CNTRL_MAIN_RST		BIT(4)
>  
>  #define PMC_WAKE_MASK			0x0c
>  #define PMC_WAKE_LEVEL			0x10
>  #define PMC_WAKE_STATUS			0x14
>  #define PMC_SW_WAKE_STATUS		0x18
> +#define PMC_DPD_PADS_ORIDE		0x1c
> +#define  PMC_DPD_PADS_ORIDE_BLINK	20
>  
>  #define DPD_SAMPLE			0x020
>  #define  DPD_SAMPLE_ENABLE		BIT(0)
> @@ -79,6 +82,7 @@
>  
>  #define PWRGATE_STATUS			0x38
>  
> +#define PMC_BLINK_TIMER			0x40
>  #define PMC_IMPL_E_33V_PWR		0x40
>  
>  #define PMC_PWR_DET			0x48
> @@ -170,6 +174,14 @@ struct pmc_clk {
>  
>  #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>  
> +struct pmc_clk_gate {
> +	struct clk_hw	hw;
> +	unsigned long	offs;
> +	u32		shift;
> +};
> +
> +#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
> +
>  struct pmc_clk_init_data {
>  	char *name;
>  	const char *const *parents;
> @@ -320,6 +332,7 @@ struct tegra_pmc_soc {
>  
>  	const struct pmc_clk_init_data *pmc_clks_data;
>  	unsigned int num_pmc_clks;
> +	bool has_blink_output;
>  };
>  
>  static const char * const tegra186_reset_sources[] = {
> @@ -2330,6 +2343,60 @@ tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>  	return clk_register(NULL, &pmc_clk->hw);
>  }
>  
> +static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
> +{
> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
> +
> +	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
> +}
> +
> +static int pmc_clk_gate_enable(struct clk_hw *hw)
> +{
> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
> +
> +	pmc_clk_set_state(gate->offs, gate->shift, 1);
> +
> +	return 0;
> +}
> +
> +static void pmc_clk_gate_disable(struct clk_hw *hw)
> +{
> +	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
> +
> +	pmc_clk_set_state(gate->offs, gate->shift, 0);
> +}
> +
> +static const struct clk_ops pmc_clk_gate_ops = {
> +	.is_enabled = pmc_clk_gate_is_enabled,
> +	.enable = pmc_clk_gate_enable,
> +	.disable = pmc_clk_gate_disable,
> +};
> +
> +static struct clk *
> +tegra_pmc_clk_gate_register(const char *name, const char *parent_name,
> +			    unsigned long flags, unsigned long offset,
> +			    u32 shift)
> +{
> +	struct clk_init_data init;
> +	struct pmc_clk_gate *gate;
> +
> +	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> +	if (!gate)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init.name = name;
> +	init.ops = &pmc_clk_gate_ops;
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +	init.flags = flags;

What about "init.flags = 0"?

> +	gate->hw.init = &init;
> +	gate->offs = offset;
> +	gate->shift = shift;
> +
> +	return clk_register(NULL, &gate->hw);
> +}
> +
>  static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>  				     struct device_node *np)
>  {
> @@ -2339,6 +2406,8 @@ static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>  	int i, err = -ENOMEM;
>  
>  	num_clks = pmc->soc->num_pmc_clks;
> +	if (pmc->soc->has_blink_output)
> +		num_clks += 1;
>  
>  	if (!num_clks)
>  		return;
> @@ -2380,6 +2449,37 @@ static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>  		}
>  	}
>  
> +	if (pmc->soc->has_blink_output) {
> +		tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
> +		clk = tegra_pmc_clk_gate_register("blink_override",
> +						  "clk_32k", 0,
> +						  PMC_DPD_PADS_ORIDE,
> +						  PMC_DPD_PADS_ORIDE_BLINK);
> +		if (IS_ERR(clk)) {
> +			dev_err(pmc->dev, "unable to register blink_override\n");
> +			err = PTR_ERR(clk);
> +			goto free_clks;
> +		}
> +
> +		clk = tegra_pmc_clk_gate_register("blink",
> +						  "blink_override", 0,
> +						  PMC_CNTRL,
> +						  PMC_CNTRL_BLINK_EN);
> +		if (IS_ERR(clk)) {
> +			dev_err(pmc->dev, "unable to register blink\n");
> +			err = PTR_ERR(clk);
> +			goto free_clks;
> +		}
> +
> +		clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
> +		err = clk_register_clkdev(clk, "blink", NULL);
> +		if (err) {
> +			dev_err(pmc->dev,
> +				"unable to register blink clock lookup\n");
> +			goto free_clks;
> +		}
> +	}
> +
>  	err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
>  	if (err) {
>  		dev_err(pmc->dev, "failed to add pmc clk provider\n");
> @@ -2658,6 +2758,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
>  	.num_reset_levels = 0,
>  	.pmc_clks_data = NULL,
>  	.num_pmc_clks = 0,
> +	.has_blink_output = true,
>  };
>  
>  static const char * const tegra30_powergates[] = {
> @@ -2707,6 +2808,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
>  	.num_reset_levels = 0,
>  	.pmc_clks_data = tegra_pmc_clks_data,
>  	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
> +	.has_blink_output = true,
>  };
>  
>  static const char * const tegra114_powergates[] = {
> @@ -2760,6 +2862,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
>  	.num_reset_levels = 0,
>  	.pmc_clks_data = tegra_pmc_clks_data,
>  	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
> +	.has_blink_output = true,
>  };
>  
>  static const char * const tegra124_powergates[] = {
> @@ -2873,6 +2976,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
>  	.num_reset_levels = 0,
>  	.pmc_clks_data = tegra_pmc_clks_data,
>  	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
> +	.has_blink_output = true,
>  };
>  
>  static const char * const tegra210_powergates[] = {
> @@ -2989,6 +3093,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
>  	.wake_events = tegra210_wake_events,
>  	.pmc_clks_data = tegra_pmc_clks_data,
>  	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
> +	.has_blink_output = true,
>  };
>  
>  #define TEGRA186_IO_PAD_TABLE(_pad)					     \
> @@ -3120,6 +3225,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
>  	.wake_events = tegra186_wake_events,
>  	.pmc_clks_data = NULL,
>  	.num_pmc_clks = 0,
> +	.has_blink_output = false,
>  };
>  
>  static const struct tegra_io_pad_soc tegra194_io_pads[] = {
> @@ -3239,6 +3345,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {
>  	.wake_events = tegra194_wake_events,
>  	.pmc_clks_data = NULL,
>  	.num_pmc_clks = 0,
> +	.has_blink_output = false,
>  };
>  
>  static const struct of_device_id tegra_pmc_match[] = {
> 


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 17/19] ARM: tegra: Update sound node clocks in device tree
  2019-12-17 20:04 ` [PATCH v4 17/19] ARM: tegra: Update sound node clocks in device tree Sowjanya Komatineni
@ 2019-12-18  6:39   ` Dmitry Osipenko
  2019-12-18  7:47   ` Dmitry Osipenko
  1 sibling, 0 replies; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  6:39 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

17.12.2019 23:04, Sowjanya Komatineni пишет:
> clk_out_1, clk_out_2, and clk_out_3 are part of Tegra PMC block
> and are moved from clock driver to pmc driver with pmc as clock
> provider.
> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
> 	t=1576613055; bh=aZWp4sScdv8qprM+UpGS0w1DX7YelR50gFqoThf23X4=;
> 	h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
> 	 In-Reply-To:References:X-NVConfidentiality:MIME-Version:
> 	 Content-Type;
> 	b=p9EmVtuTvJK6owqo0lmnZnAvftCWc6+7Mkp/Ks9y26tKN5c4jU+I+YEAaMWoHuzd+
> 	 7n0vS98WNMGomj19IUXoaH49IeTgPAlqOkU57IIiL2qEnX3sYNYpl/rCRUIs7vd33t
> 	 LSn8tQeu9Lz+Yfl8hvXcN3sdxRQOEPDYwzWG+tVy1FCnwouTHSfBhgado2Tx/9cWgi
> 	 HlSWkzjvodag7mAmZtLCl5P4J+oVEJnpYnjSZKNojqszn8u651ErvnVI/VbhZwQ0G5
> 	 Yg8kEr8YECPk2L4MXUe8J2YmKtNyZaADOkUhjyxqMjZ2bGrB9RDm5dKNFxkWuEeSpb
> 	 U3nMi7MNcvBmQ==

Looks like NVIDIA's mail server has some problems.

[snip]

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-17 20:04 ` [PATCH v4 13/19] ASoC: tegra: Add fallback implementation " Sowjanya Komatineni
@ 2019-12-18  6:59   ` Dmitry Osipenko
  2019-12-18  7:01     ` Dmitry Osipenko
  0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  6:59 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

17.12.2019 23:04, Sowjanya Komatineni пишет:
> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
> are moved to Tegra PMC driver with pmc as clock provider and using pmc
> clock ids.
> 
> New device tree uses clk_out_1 from pmc clock provider.
> 
> So, this patch adds implementation for mclk fallback to extern1 when
> retrieving mclk returns -ENOENT to be backward compatible of new device
> tree with older kernels.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
> index fe9ca8acd0fb..1b88c6043082 100644
> --- a/sound/soc/tegra/tegra_asoc_utils.c
> +++ b/sound/soc/tegra/tegra_asoc_utils.c
> @@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
>  	data->clk_cdev1 = devm_clk_get(dev, "mclk");
>  	if (IS_ERR(data->clk_cdev1)) {
>  		dev_err(data->dev, "Can't retrieve clk cdev1\n");
> -		return PTR_ERR(data->clk_cdev1);
> +		if (PTR_ERR(data->clk_cdev1) != -ENOENT)
> +			return PTR_ERR(data->clk_cdev1);
> +		/* Fall back to extern1 */
> +		data->clk_cdev1 = devm_clk_get(dev, "extern1");
> +		if (IS_ERR(data->clk_cdev1)) {
> +			dev_err(data->dev, "Can't retrieve clk extern1\n");
> +			return PTR_ERR(data->clk_cdev1);
> +		}
> +
> +		dev_err(data->dev, "Falling back to extern1\n");
>  	}
>  
>  	/*
> 

[    1.769091] ------------[ cut here ]------------
[    1.769249] WARNING: CPU: 2 PID: 1 at drivers/clk/clk.c:954
clk_core_disable+0xa5/0x1d4
[    1.769330] clk_out_1 already disabled
[    1.769459] Modules linked in:
[    1.769541] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
5.5.0-rc1-next-20191213-00167-g6b9fbcdac8f3-dirty #266
[    1.769676] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
[    1.769775] [<c010e4bd>] (unwind_backtrace) from [<c010a0fd>]
(show_stack+0x11/0x14)
[    1.769918] [<c010a0fd>] (show_stack) from [<c09a37b1>]
(dump_stack+0x85/0x94)
[    1.770061] [<c09a37b1>] (dump_stack) from [<c011f3d1>]
(__warn+0xc1/0xc4)
[    1.770144] [<c011f3d1>] (__warn) from [<c011f691>]
(warn_slowpath_fmt+0x61/0x78)
[    1.770285] [<c011f691>] (warn_slowpath_fmt) from [<c04a0e7d>]
(clk_core_disable+0xa5/0x1d4)
[    1.770427] [<c04a0e7d>] (clk_core_disable) from [<c04a0fc3>]
(clk_core_disable_lock+0x17/0x20)
[    1.770516] [<c04a0fc3>] (clk_core_disable_lock) from [<c07792bb>]
(tegra_asoc_utils_set_rate+0x53/0x208)
[    1.770662] [<c07792bb>] (tegra_asoc_utils_set_rate) from
[<c077b8c5>] (tegra_rt5640_probe+0xd5/0x128)
[    1.770808] [<c077b8c5>] (tegra_rt5640_probe) from [<c0555eb7>]
(platform_drv_probe+0x33/0x68)
[    1.770958] [<c0555eb7>] (platform_drv_probe) from [<c055471d>]
(really_probe+0x14d/0x240)
[    1.771099] [<c055471d>] (really_probe) from [<c055493f>]
(driver_probe_device+0x43/0x11c)
[    1.771187] [<c055493f>] (driver_probe_device) from [<c0554b25>]
(device_driver_attach+0x3d/0x40)
[    1.771328] [<c0554b25>] (device_driver_attach) from [<c0554b5f>]
(__driver_attach+0x37/0x78)
[    1.771469] [<c0554b5f>] (__driver_attach) from [<c05532fb>]
(bus_for_each_dev+0x43/0x6c)
[    1.771609] [<c05532fb>] (bus_for_each_dev) from [<c0553e0f>]
(bus_add_driver+0xe3/0x148)
[    1.771692] [<c0553e0f>] (bus_add_driver) from [<c055531d>]
(driver_register+0x39/0xa0)
[    1.771833] [<c055531d>] (driver_register) from [<c0102c2f>]
(do_one_initcall+0x43/0x1bc)
[    1.771979] [<c0102c2f>] (do_one_initcall) from [<c1000ce5>]
(kernel_init_freeable+0x121/0x194)
[    1.772129] [<c1000ce5>] (kernel_init_freeable) from [<c09b40e9>]
(kernel_init+0xd/0xd0)
[    1.772215] [<c09b40e9>] (kernel_init) from [<c01010bd>]
(ret_from_fork+0x11/0x34)
[    1.772349] Exception stack(0xde907fb0 to 0xde907ff8)


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-18  6:59   ` Dmitry Osipenko
@ 2019-12-18  7:01     ` Dmitry Osipenko
  2019-12-18  7:14       ` Sowjanya Komatineni
  0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  7:01 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

18.12.2019 09:59, Dmitry Osipenko пишет:
> 17.12.2019 23:04, Sowjanya Komatineni пишет:
>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
>> are moved to Tegra PMC driver with pmc as clock provider and using pmc
>> clock ids.
>>
>> New device tree uses clk_out_1 from pmc clock provider.
>>
>> So, this patch adds implementation for mclk fallback to extern1 when
>> retrieving mclk returns -ENOENT to be backward compatible of new device
>> tree with older kernels.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>>  sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
>>  1 file changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
>> index fe9ca8acd0fb..1b88c6043082 100644
>> --- a/sound/soc/tegra/tegra_asoc_utils.c
>> +++ b/sound/soc/tegra/tegra_asoc_utils.c
>> @@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
>>  	data->clk_cdev1 = devm_clk_get(dev, "mclk");
>>  	if (IS_ERR(data->clk_cdev1)) {
>>  		dev_err(data->dev, "Can't retrieve clk cdev1\n");
>> -		return PTR_ERR(data->clk_cdev1);
>> +		if (PTR_ERR(data->clk_cdev1) != -ENOENT)
>> +			return PTR_ERR(data->clk_cdev1);
>> +		/* Fall back to extern1 */
>> +		data->clk_cdev1 = devm_clk_get(dev, "extern1");
>> +		if (IS_ERR(data->clk_cdev1)) {
>> +			dev_err(data->dev, "Can't retrieve clk extern1\n");
>> +			return PTR_ERR(data->clk_cdev1);
>> +		}
>> +
>> +		dev_err(data->dev, "Falling back to extern1\n");
>>  	}
>>  
>>  	/*
>>
> 
> [    1.769091] ------------[ cut here ]------------
> [    1.769249] WARNING: CPU: 2 PID: 1 at drivers/clk/clk.c:954
> clk_core_disable+0xa5/0x1d4
> [    1.769330] clk_out_1 already disabled
> [    1.769459] Modules linked in:
> [    1.769541] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
> 5.5.0-rc1-next-20191213-00167-g6b9fbcdac8f3-dirty #266
> [    1.769676] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
> [    1.769775] [<c010e4bd>] (unwind_backtrace) from [<c010a0fd>]
> (show_stack+0x11/0x14)
> [    1.769918] [<c010a0fd>] (show_stack) from [<c09a37b1>]
> (dump_stack+0x85/0x94)
> [    1.770061] [<c09a37b1>] (dump_stack) from [<c011f3d1>]
> (__warn+0xc1/0xc4)
> [    1.770144] [<c011f3d1>] (__warn) from [<c011f691>]
> (warn_slowpath_fmt+0x61/0x78)
> [    1.770285] [<c011f691>] (warn_slowpath_fmt) from [<c04a0e7d>]
> (clk_core_disable+0xa5/0x1d4)
> [    1.770427] [<c04a0e7d>] (clk_core_disable) from [<c04a0fc3>]
> (clk_core_disable_lock+0x17/0x20)
> [    1.770516] [<c04a0fc3>] (clk_core_disable_lock) from [<c07792bb>]
> (tegra_asoc_utils_set_rate+0x53/0x208)
> [    1.770662] [<c07792bb>] (tegra_asoc_utils_set_rate) from
> [<c077b8c5>] (tegra_rt5640_probe+0xd5/0x128)
> [    1.770808] [<c077b8c5>] (tegra_rt5640_probe) from [<c0555eb7>]
> (platform_drv_probe+0x33/0x68)
> [    1.770958] [<c0555eb7>] (platform_drv_probe) from [<c055471d>]
> (really_probe+0x14d/0x240)
> [    1.771099] [<c055471d>] (really_probe) from [<c055493f>]
> (driver_probe_device+0x43/0x11c)
> [    1.771187] [<c055493f>] (driver_probe_device) from [<c0554b25>]
> (device_driver_attach+0x3d/0x40)
> [    1.771328] [<c0554b25>] (device_driver_attach) from [<c0554b5f>]
> (__driver_attach+0x37/0x78)
> [    1.771469] [<c0554b5f>] (__driver_attach) from [<c05532fb>]
> (bus_for_each_dev+0x43/0x6c)
> [    1.771609] [<c05532fb>] (bus_for_each_dev) from [<c0553e0f>]
> (bus_add_driver+0xe3/0x148)
> [    1.771692] [<c0553e0f>] (bus_add_driver) from [<c055531d>]
> (driver_register+0x39/0xa0)
> [    1.771833] [<c055531d>] (driver_register) from [<c0102c2f>]
> (do_one_initcall+0x43/0x1bc)
> [    1.771979] [<c0102c2f>] (do_one_initcall) from [<c1000ce5>]
> (kernel_init_freeable+0x121/0x194)
> [    1.772129] [<c1000ce5>] (kernel_init_freeable) from [<c09b40e9>]
> (kernel_init+0xd/0xd0)
> [    1.772215] [<c09b40e9>] (kernel_init) from [<c01010bd>]
> (ret_from_fork+0x11/0x34)
> [    1.772349] Exception stack(0xde907fb0 to 0xde907ff8)
> 

Although, that's probably related to the "ASoC: tegra: Add initial
parent configuration for audio mclk".


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-18  7:01     ` Dmitry Osipenko
@ 2019-12-18  7:14       ` Sowjanya Komatineni
  2019-12-18  7:22         ` Dmitry Osipenko
  0 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-18  7:14 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/17/19 11:01 PM, Dmitry Osipenko wrote:
> 18.12.2019 09:59, Dmitry Osipenko пишет:
>> 17.12.2019 23:04, Sowjanya Komatineni пишет:
>>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
>>> are moved to Tegra PMC driver with pmc as clock provider and using pmc
>>> clock ids.
>>>
>>> New device tree uses clk_out_1 from pmc clock provider.
>>>
>>> So, this patch adds implementation for mclk fallback to extern1 when
>>> retrieving mclk returns -ENOENT to be backward compatible of new device
>>> tree with older kernels.
>>>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>>   sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
>>>   1 file changed, 10 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
>>> index fe9ca8acd0fb..1b88c6043082 100644
>>> --- a/sound/soc/tegra/tegra_asoc_utils.c
>>> +++ b/sound/soc/tegra/tegra_asoc_utils.c
>>> @@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
>>>   	data->clk_cdev1 = devm_clk_get(dev, "mclk");
>>>   	if (IS_ERR(data->clk_cdev1)) {
>>>   		dev_err(data->dev, "Can't retrieve clk cdev1\n");
>>> -		return PTR_ERR(data->clk_cdev1);
>>> +		if (PTR_ERR(data->clk_cdev1) != -ENOENT)
>>> +			return PTR_ERR(data->clk_cdev1);
>>> +		/* Fall back to extern1 */
>>> +		data->clk_cdev1 = devm_clk_get(dev, "extern1");
>>> +		if (IS_ERR(data->clk_cdev1)) {
>>> +			dev_err(data->dev, "Can't retrieve clk extern1\n");
>>> +			return PTR_ERR(data->clk_cdev1);
>>> +		}
>>> +
>>> +		dev_err(data->dev, "Falling back to extern1\n");
>>>   	}
>>>   
>>>   	/*
>>>
>> [    1.769091] ------------[ cut here ]------------
>> [    1.769249] WARNING: CPU: 2 PID: 1 at drivers/clk/clk.c:954
>> clk_core_disable+0xa5/0x1d4
>> [    1.769330] clk_out_1 already disabled
>> [    1.769459] Modules linked in:
>> [    1.769541] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
>> 5.5.0-rc1-next-20191213-00167-g6b9fbcdac8f3-dirty #266
>> [    1.769676] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
>> [    1.769775] [<c010e4bd>] (unwind_backtrace) from [<c010a0fd>]
>> (show_stack+0x11/0x14)
>> [    1.769918] [<c010a0fd>] (show_stack) from [<c09a37b1>]
>> (dump_stack+0x85/0x94)
>> [    1.770061] [<c09a37b1>] (dump_stack) from [<c011f3d1>]
>> (__warn+0xc1/0xc4)
>> [    1.770144] [<c011f3d1>] (__warn) from [<c011f691>]
>> (warn_slowpath_fmt+0x61/0x78)
>> [    1.770285] [<c011f691>] (warn_slowpath_fmt) from [<c04a0e7d>]
>> (clk_core_disable+0xa5/0x1d4)
>> [    1.770427] [<c04a0e7d>] (clk_core_disable) from [<c04a0fc3>]
>> (clk_core_disable_lock+0x17/0x20)
>> [    1.770516] [<c04a0fc3>] (clk_core_disable_lock) from [<c07792bb>]
>> (tegra_asoc_utils_set_rate+0x53/0x208)
>> [    1.770662] [<c07792bb>] (tegra_asoc_utils_set_rate) from
>> [<c077b8c5>] (tegra_rt5640_probe+0xd5/0x128)
>> [    1.770808] [<c077b8c5>] (tegra_rt5640_probe) from [<c0555eb7>]
>> (platform_drv_probe+0x33/0x68)
>> [    1.770958] [<c0555eb7>] (platform_drv_probe) from [<c055471d>]
>> (really_probe+0x14d/0x240)
>> [    1.771099] [<c055471d>] (really_probe) from [<c055493f>]
>> (driver_probe_device+0x43/0x11c)
>> [    1.771187] [<c055493f>] (driver_probe_device) from [<c0554b25>]
>> (device_driver_attach+0x3d/0x40)
>> [    1.771328] [<c0554b25>] (device_driver_attach) from [<c0554b5f>]
>> (__driver_attach+0x37/0x78)
>> [    1.771469] [<c0554b5f>] (__driver_attach) from [<c05532fb>]
>> (bus_for_each_dev+0x43/0x6c)
>> [    1.771609] [<c05532fb>] (bus_for_each_dev) from [<c0553e0f>]
>> (bus_add_driver+0xe3/0x148)
>> [    1.771692] [<c0553e0f>] (bus_add_driver) from [<c055531d>]
>> (driver_register+0x39/0xa0)
>> [    1.771833] [<c055531d>] (driver_register) from [<c0102c2f>]
>> (do_one_initcall+0x43/0x1bc)
>> [    1.771979] [<c0102c2f>] (do_one_initcall) from [<c1000ce5>]
>> (kernel_init_freeable+0x121/0x194)
>> [    1.772129] [<c1000ce5>] (kernel_init_freeable) from [<c09b40e9>]
>> (kernel_init+0xd/0xd0)
>> [    1.772215] [<c09b40e9>] (kernel_init) from [<c01010bd>]
>> (ret_from_fork+0x11/0x34)
>> [    1.772349] Exception stack(0xde907fb0 to 0xde907ff8)
>>
> Although, that's probably related to the "ASoC: tegra: Add initial
> parent configuration for audio mclk".
>
Actually I see these warnings of already unprepared and already disabled 
for pll_a, pll_a_out0, and clk_out_1 even without this whole patch 
series as well.

I think its from tegra_asoc_utils_set_rate() doing clk_disable_unprepare 
and these clocks are already unprepared and disabled so its just warning 
from clk_core_unprepare and clk_core_disable.



^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-18  7:14       ` Sowjanya Komatineni
@ 2019-12-18  7:22         ` Dmitry Osipenko
  2019-12-18  7:31           ` Dmitry Osipenko
  0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  7:22 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

18.12.2019 10:14, Sowjanya Komatineni пишет:
> 
> On 12/17/19 11:01 PM, Dmitry Osipenko wrote:
>> 18.12.2019 09:59, Dmitry Osipenko пишет:
>>> 17.12.2019 23:04, Sowjanya Komatineni пишет:
>>>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
>>>> are moved to Tegra PMC driver with pmc as clock provider and using pmc
>>>> clock ids.
>>>>
>>>> New device tree uses clk_out_1 from pmc clock provider.
>>>>
>>>> So, this patch adds implementation for mclk fallback to extern1 when
>>>> retrieving mclk returns -ENOENT to be backward compatible of new device
>>>> tree with older kernels.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>>   sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
>>>>   1 file changed, 10 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/sound/soc/tegra/tegra_asoc_utils.c
>>>> b/sound/soc/tegra/tegra_asoc_utils.c
>>>> index fe9ca8acd0fb..1b88c6043082 100644
>>>> --- a/sound/soc/tegra/tegra_asoc_utils.c
>>>> +++ b/sound/soc/tegra/tegra_asoc_utils.c
>>>> @@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct
>>>> tegra_asoc_utils_data *data,
>>>>       data->clk_cdev1 = devm_clk_get(dev, "mclk");
>>>>       if (IS_ERR(data->clk_cdev1)) {
>>>>           dev_err(data->dev, "Can't retrieve clk cdev1\n");
>>>> -        return PTR_ERR(data->clk_cdev1);
>>>> +        if (PTR_ERR(data->clk_cdev1) != -ENOENT)
>>>> +            return PTR_ERR(data->clk_cdev1);
>>>> +        /* Fall back to extern1 */
>>>> +        data->clk_cdev1 = devm_clk_get(dev, "extern1");
>>>> +        if (IS_ERR(data->clk_cdev1)) {
>>>> +            dev_err(data->dev, "Can't retrieve clk extern1\n");
>>>> +            return PTR_ERR(data->clk_cdev1);
>>>> +        }
>>>> +
>>>> +        dev_err(data->dev, "Falling back to extern1\n");
>>>>       }
>>>>         /*
>>>>
>>> [    1.769091] ------------[ cut here ]------------
>>> [    1.769249] WARNING: CPU: 2 PID: 1 at drivers/clk/clk.c:954
>>> clk_core_disable+0xa5/0x1d4
>>> [    1.769330] clk_out_1 already disabled
>>> [    1.769459] Modules linked in:
>>> [    1.769541] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
>>> 5.5.0-rc1-next-20191213-00167-g6b9fbcdac8f3-dirty #266
>>> [    1.769676] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
>>> [    1.769775] [<c010e4bd>] (unwind_backtrace) from [<c010a0fd>]
>>> (show_stack+0x11/0x14)
>>> [    1.769918] [<c010a0fd>] (show_stack) from [<c09a37b1>]
>>> (dump_stack+0x85/0x94)
>>> [    1.770061] [<c09a37b1>] (dump_stack) from [<c011f3d1>]
>>> (__warn+0xc1/0xc4)
>>> [    1.770144] [<c011f3d1>] (__warn) from [<c011f691>]
>>> (warn_slowpath_fmt+0x61/0x78)
>>> [    1.770285] [<c011f691>] (warn_slowpath_fmt) from [<c04a0e7d>]
>>> (clk_core_disable+0xa5/0x1d4)
>>> [    1.770427] [<c04a0e7d>] (clk_core_disable) from [<c04a0fc3>]
>>> (clk_core_disable_lock+0x17/0x20)
>>> [    1.770516] [<c04a0fc3>] (clk_core_disable_lock) from [<c07792bb>]
>>> (tegra_asoc_utils_set_rate+0x53/0x208)
>>> [    1.770662] [<c07792bb>] (tegra_asoc_utils_set_rate) from
>>> [<c077b8c5>] (tegra_rt5640_probe+0xd5/0x128)
>>> [    1.770808] [<c077b8c5>] (tegra_rt5640_probe) from [<c0555eb7>]
>>> (platform_drv_probe+0x33/0x68)
>>> [    1.770958] [<c0555eb7>] (platform_drv_probe) from [<c055471d>]
>>> (really_probe+0x14d/0x240)
>>> [    1.771099] [<c055471d>] (really_probe) from [<c055493f>]
>>> (driver_probe_device+0x43/0x11c)
>>> [    1.771187] [<c055493f>] (driver_probe_device) from [<c0554b25>]
>>> (device_driver_attach+0x3d/0x40)
>>> [    1.771328] [<c0554b25>] (device_driver_attach) from [<c0554b5f>]
>>> (__driver_attach+0x37/0x78)
>>> [    1.771469] [<c0554b5f>] (__driver_attach) from [<c05532fb>]
>>> (bus_for_each_dev+0x43/0x6c)
>>> [    1.771609] [<c05532fb>] (bus_for_each_dev) from [<c0553e0f>]
>>> (bus_add_driver+0xe3/0x148)
>>> [    1.771692] [<c0553e0f>] (bus_add_driver) from [<c055531d>]
>>> (driver_register+0x39/0xa0)
>>> [    1.771833] [<c055531d>] (driver_register) from [<c0102c2f>]
>>> (do_one_initcall+0x43/0x1bc)
>>> [    1.771979] [<c0102c2f>] (do_one_initcall) from [<c1000ce5>]
>>> (kernel_init_freeable+0x121/0x194)
>>> [    1.772129] [<c1000ce5>] (kernel_init_freeable) from [<c09b40e9>]
>>> (kernel_init+0xd/0xd0)
>>> [    1.772215] [<c09b40e9>] (kernel_init) from [<c01010bd>]
>>> (ret_from_fork+0x11/0x34)
>>> [    1.772349] Exception stack(0xde907fb0 to 0xde907ff8)
>>>
>> Although, that's probably related to the "ASoC: tegra: Add initial
>> parent configuration for audio mclk".
>>
> Actually I see these warnings of already unprepared and already disabled
> for pll_a, pll_a_out0, and clk_out_1 even without this whole patch
> series as well.
> 
> I think its from tegra_asoc_utils_set_rate() doing clk_disable_unprepare
> and these clocks are already unprepared and disabled so its just warning
> from clk_core_unprepare and clk_core_disable.

Doesn't happen for me without this series.

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-18  7:22         ` Dmitry Osipenko
@ 2019-12-18  7:31           ` Dmitry Osipenko
  2019-12-18 15:43             ` Sowjanya Komatineni
  0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  7:31 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

18.12.2019 10:22, Dmitry Osipenko пишет:
> 18.12.2019 10:14, Sowjanya Komatineni пишет:
>>
>> On 12/17/19 11:01 PM, Dmitry Osipenko wrote:
>>> 18.12.2019 09:59, Dmitry Osipenko пишет:
>>>> 17.12.2019 23:04, Sowjanya Komatineni пишет:
>>>>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
>>>>> are moved to Tegra PMC driver with pmc as clock provider and using pmc
>>>>> clock ids.
>>>>>
>>>>> New device tree uses clk_out_1 from pmc clock provider.
>>>>>
>>>>> So, this patch adds implementation for mclk fallback to extern1 when
>>>>> retrieving mclk returns -ENOENT to be backward compatible of new device
>>>>> tree with older kernels.
>>>>>
>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>> ---
>>>>>   sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
>>>>>   1 file changed, 10 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/sound/soc/tegra/tegra_asoc_utils.c
>>>>> b/sound/soc/tegra/tegra_asoc_utils.c
>>>>> index fe9ca8acd0fb..1b88c6043082 100644
>>>>> --- a/sound/soc/tegra/tegra_asoc_utils.c
>>>>> +++ b/sound/soc/tegra/tegra_asoc_utils.c
>>>>> @@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct
>>>>> tegra_asoc_utils_data *data,
>>>>>       data->clk_cdev1 = devm_clk_get(dev, "mclk");
>>>>>       if (IS_ERR(data->clk_cdev1)) {
>>>>>           dev_err(data->dev, "Can't retrieve clk cdev1\n");
>>>>> -        return PTR_ERR(data->clk_cdev1);
>>>>> +        if (PTR_ERR(data->clk_cdev1) != -ENOENT)
>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>> +        /* Fall back to extern1 */
>>>>> +        data->clk_cdev1 = devm_clk_get(dev, "extern1");
>>>>> +        if (IS_ERR(data->clk_cdev1)) {
>>>>> +            dev_err(data->dev, "Can't retrieve clk extern1\n");
>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>> +        }
>>>>> +
>>>>> +        dev_err(data->dev, "Falling back to extern1\n");
>>>>>       }
>>>>>         /*
>>>>>
>>>> [    1.769091] ------------[ cut here ]------------
>>>> [    1.769249] WARNING: CPU: 2 PID: 1 at drivers/clk/clk.c:954
>>>> clk_core_disable+0xa5/0x1d4
>>>> [    1.769330] clk_out_1 already disabled
>>>> [    1.769459] Modules linked in:
>>>> [    1.769541] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
>>>> 5.5.0-rc1-next-20191213-00167-g6b9fbcdac8f3-dirty #266
>>>> [    1.769676] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
>>>> [    1.769775] [<c010e4bd>] (unwind_backtrace) from [<c010a0fd>]
>>>> (show_stack+0x11/0x14)
>>>> [    1.769918] [<c010a0fd>] (show_stack) from [<c09a37b1>]
>>>> (dump_stack+0x85/0x94)
>>>> [    1.770061] [<c09a37b1>] (dump_stack) from [<c011f3d1>]
>>>> (__warn+0xc1/0xc4)
>>>> [    1.770144] [<c011f3d1>] (__warn) from [<c011f691>]
>>>> (warn_slowpath_fmt+0x61/0x78)
>>>> [    1.770285] [<c011f691>] (warn_slowpath_fmt) from [<c04a0e7d>]
>>>> (clk_core_disable+0xa5/0x1d4)
>>>> [    1.770427] [<c04a0e7d>] (clk_core_disable) from [<c04a0fc3>]
>>>> (clk_core_disable_lock+0x17/0x20)
>>>> [    1.770516] [<c04a0fc3>] (clk_core_disable_lock) from [<c07792bb>]
>>>> (tegra_asoc_utils_set_rate+0x53/0x208)
>>>> [    1.770662] [<c07792bb>] (tegra_asoc_utils_set_rate) from
>>>> [<c077b8c5>] (tegra_rt5640_probe+0xd5/0x128)
>>>> [    1.770808] [<c077b8c5>] (tegra_rt5640_probe) from [<c0555eb7>]
>>>> (platform_drv_probe+0x33/0x68)
>>>> [    1.770958] [<c0555eb7>] (platform_drv_probe) from [<c055471d>]
>>>> (really_probe+0x14d/0x240)
>>>> [    1.771099] [<c055471d>] (really_probe) from [<c055493f>]
>>>> (driver_probe_device+0x43/0x11c)
>>>> [    1.771187] [<c055493f>] (driver_probe_device) from [<c0554b25>]
>>>> (device_driver_attach+0x3d/0x40)
>>>> [    1.771328] [<c0554b25>] (device_driver_attach) from [<c0554b5f>]
>>>> (__driver_attach+0x37/0x78)
>>>> [    1.771469] [<c0554b5f>] (__driver_attach) from [<c05532fb>]
>>>> (bus_for_each_dev+0x43/0x6c)
>>>> [    1.771609] [<c05532fb>] (bus_for_each_dev) from [<c0553e0f>]
>>>> (bus_add_driver+0xe3/0x148)
>>>> [    1.771692] [<c0553e0f>] (bus_add_driver) from [<c055531d>]
>>>> (driver_register+0x39/0xa0)
>>>> [    1.771833] [<c055531d>] (driver_register) from [<c0102c2f>]
>>>> (do_one_initcall+0x43/0x1bc)
>>>> [    1.771979] [<c0102c2f>] (do_one_initcall) from [<c1000ce5>]
>>>> (kernel_init_freeable+0x121/0x194)
>>>> [    1.772129] [<c1000ce5>] (kernel_init_freeable) from [<c09b40e9>]
>>>> (kernel_init+0xd/0xd0)
>>>> [    1.772215] [<c09b40e9>] (kernel_init) from [<c01010bd>]
>>>> (ret_from_fork+0x11/0x34)
>>>> [    1.772349] Exception stack(0xde907fb0 to 0xde907ff8)
>>>>
>>> Although, that's probably related to the "ASoC: tegra: Add initial
>>> parent configuration for audio mclk".
>>>
>> Actually I see these warnings of already unprepared and already disabled
>> for pll_a, pll_a_out0, and clk_out_1 even without this whole patch
>> series as well.
>>
>> I think its from tegra_asoc_utils_set_rate() doing clk_disable_unprepare
>> and these clocks are already unprepared and disabled so its just warning
>> from clk_core_unprepare and clk_core_disable.
> 
> Doesn't happen for me without this series.

But sound works with both old/new device-trees.

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 17/19] ARM: tegra: Update sound node clocks in device tree
  2019-12-17 20:04 ` [PATCH v4 17/19] ARM: tegra: Update sound node clocks in device tree Sowjanya Komatineni
  2019-12-18  6:39   ` Dmitry Osipenko
@ 2019-12-18  7:47   ` Dmitry Osipenko
  1 sibling, 0 replies; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  7:47 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

17.12.2019 23:04, Sowjanya Komatineni пишет:
> clk_out_1, clk_out_2, and clk_out_3 are part of Tegra PMC block
> and are moved from clock driver to pmc driver with pmc as clock
> provider.
> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
> 	t=1576613055; bh=aZWp4sScdv8qprM+UpGS0w1DX7YelR50gFqoThf23X4=;
> 	h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
> 	 In-Reply-To:References:X-NVConfidentiality:MIME-Version:
> 	 Content-Type;
> 	b=p9EmVtuTvJK6owqo0lmnZnAvftCWc6+7Mkp/Ks9y26tKN5c4jU+I+YEAaMWoHuzd+
> 	 7n0vS98WNMGomj19IUXoaH49IeTgPAlqOkU57IIiL2qEnX3sYNYpl/rCRUIs7vd33t
> 	 LSn8tQeu9Lz+Yfl8hvXcN3sdxRQOEPDYwzWG+tVy1FCnwouTHSfBhgado2Tx/9cWgi
> 	 HlSWkzjvodag7mAmZtLCl5P4J+oVEJnpYnjSZKNojqszn8u651ErvnVI/VbhZwQ0G5
> 	 Yg8kEr8YECPk2L4MXUe8J2YmKtNyZaADOkUhjyxqMjZ2bGrB9RDm5dKNFxkWuEeSpb
> 	 U3nMi7MNcvBmQ==
> 
> clk_out_1 is dedicated for audio mclk on Tegra30 through Tegra210.
> 
> This patch updates device tree sound node to use clk_out_1 from
> pmc provider as mclk and uses assigned-clock properties to specify
> clock parents for clk_out_1 and extern1.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  arch/arm/boot/dts/tegra114-dalmore.dts      | 7 ++++++-
>  arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 7 ++++++-
>  arch/arm/boot/dts/tegra124-apalis.dtsi      | 7 ++++++-
>  arch/arm/boot/dts/tegra124-jetson-tk1.dts   | 7 ++++++-
>  arch/arm/boot/dts/tegra124-nyan.dtsi        | 7 ++++++-
>  arch/arm/boot/dts/tegra124-venice2.dts      | 7 ++++++-
>  arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi  | 7 ++++++-
>  arch/arm/boot/dts/tegra30-apalis.dtsi       | 7 ++++++-
>  arch/arm/boot/dts/tegra30-beaver.dts        | 7 ++++++-
>  arch/arm/boot/dts/tegra30-cardhu.dtsi       | 7 ++++++-
>  arch/arm/boot/dts/tegra30-colibri.dtsi      | 7 ++++++-
>  11 files changed, 66 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
> index 97a5c3504bbe..c1914b590f5c 100644
> --- a/arch/arm/boot/dts/tegra114-dalmore.dts
> +++ b/arch/arm/boot/dts/tegra114-dalmore.dts
> @@ -1296,7 +1296,12 @@
>  
>  		clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
>  			 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
> -			 <&tegra_car TEGRA114_CLK_EXTERN1>;
> +			 <&pmc TEGRA_PMC_CLK_OUT_1>;
>  		clock-names = "pll_a", "pll_a_out0", "mclk";
> +
> +		assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
> +				  <&pmc TEGRA_PMC_CLK_OUT_1>;

Won't hurt to add a blank line here, similarly in other places below.

> +		assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
> +					 <&tegra_car TEGRA114_CLK_EXTERN1>;

[snip]


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 05/19] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
  2019-12-17 20:03 ` [PATCH v4 05/19] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings Sowjanya Komatineni
@ 2019-12-18  7:56   ` Dmitry Osipenko
  0 siblings, 0 replies; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  7:56 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

17.12.2019 23:03, Sowjanya Komatineni пишет:
> Tegra PMC has 3 clocks clk_out_1, clk_out_2, and clk_out_3.
> 
> This patch documents PMC clock bindings and adds a header defining
> Tegra PMC clock ids.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      | 37 +++++++++++++++++++++-
>  include/dt-bindings/soc/tegra-pmc.h                | 15 +++++++++
>  2 files changed, 51 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/soc/tegra-pmc.h
> 
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> index cb12f33a247f..80cdcad4ab8c 100644
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> @@ -21,6 +21,10 @@ Required properties:
>  - clock-names : Must include the following entries:
>    "pclk" (The Tegra clock of that name),
>    "clk32k_in" (The 32KHz clock input to Tegra).
> +- #clock-cells : Should be 1 for Tegra30 and higher.
> +  In clock consumers, this cell represents the PMC clock ID.
> +  The assignments may be found in header file
> +  <dt-bindings/soc/tegra-pmc.h>.
>  
>  Optional properties:
>  - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
> @@ -80,11 +84,12 @@ Optional nodes:
>  Example:
>  
>  / SoC dts including file
> -pmc@7000f400 {
> +pmc: pmc@7000f400 {
>  	compatible = "nvidia,tegra20-pmc";
>  	reg = <0x7000e400 0x400>;
>  	clocks = <&tegra_car 110>, <&clk32k_in>;
>  	clock-names = "pclk", "clk32k_in";
> +	#clock-cells = <1>;
>  	nvidia,invert-interrupt;
>  	nvidia,suspend-mode = <1>;
>  	nvidia,cpu-pwr-good-time = <2000>;
> @@ -171,6 +176,7 @@ Example:
>  		reg = <0x0 0x7000e400 0x0 0x400>;
>  		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
>  		clock-names = "pclk", "clk32k_in";
> +		#clock-cells = <1>;
>  
>  		powergates {
>  			pd_audio: aud {
> @@ -260,6 +266,7 @@ Pad configuration state example:
>  		reg = <0x0 0x7000e400 0x0 0x400>;
>  		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
>  		clock-names = "pclk", "clk32k_in";
> +		#clock-cells = <1>;
>  
>  		...
>  
> @@ -298,3 +305,31 @@ Pinctrl client example:
>  		pinctrl-1 = <&hdmi_on>;
>  		pinctrl-names = "hdmi-on", "hdmi-off";
>  	};
> +
> +== Clock Control ==
> +
> +Tegra PMC has 3 clocks clk_1, clk_2 and clk_3. Each of these clocks has
> +source selection and enable/disable gate.
> +Parent/source for these clocks can be either of osc, osc_div2, osc_div4,
> +or extern clock from Tegra CAR module.
> +
> +Clock configuration example:
> +	pmc: pmc@7000e400 {
> +		compatible = "nvidia,tegra210-pmc";
> +		reg = <0x0 0x7000e400 0x0 0x400>;
> +		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
> +		clock-names = "pclk", "clk32k_in";
> +		#clock-cells = <1>;
> +	};
> +
> +Clock consumer example:
> +	i2c@7000c500 {
> +		cam_sensor {
> +			...
> +			clocks = <&pmc TEGRA_PMC_CLK_OUT_3>;
> +			clock-names = "mclk";
> +			assigned-clocks = <&pmc TEGRA_PMC_CLK_OUT_3>;
> +			assigned-clock-parents = <&tegra_car TEGRA210_CLK_EXTERN3>;
> +			...
> +		};
> +	};
> diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h
> new file mode 100644
> index 000000000000..f7c866404456
> --- /dev/null
> +++ b/include/dt-bindings/soc/tegra-pmc.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H
> +#define _DT_BINDINGS_SOC_TEGRA_PMC_H
> +
> +#define TEGRA_PMC_CLK_OUT_1		0
> +#define TEGRA_PMC_CLK_OUT_2		1
> +#define TEGRA_PMC_CLK_OUT_3		2
> +
> +#define TEGRA_PMC_CLK_MAX		3
> +
> +#endif	/* _DT_BINDINGS_SOC_TEGRA_PMC_H */
> 

The TXT binding should be removed since you converted it to YAML.

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-17 20:03 ` [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver Sowjanya Komatineni
@ 2019-12-18  8:30   ` Dmitry Osipenko
  2019-12-18  8:35     ` Dmitry Osipenko
  0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  8:30 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

17.12.2019 23:03, Sowjanya Komatineni пишет:
> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
> these PMC clocks are registered by Tegra clock driver with each clock as
> separate mux and gate clocks using clk_register_mux and clk_register_gate
> by passing PMC base address and register offsets and PMC programming for
> these clocks happens through direct PMC access by the clock driver.
> 
> With this, when PMC is in secure mode any direct PMC access from the
> non-secure world does not go through and these clocks will not be
> functional.
> 
> This patch adds these PMC clocks registration to pmc driver with PMC as
> a clock provider and registers each clock as single clock.
> 
> clk_ops callback implementations for these clocks uses tegra_pmc_readl and
> tegra_pmc_writel which supports PMC programming in both secure mode and
> non-secure mode.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  drivers/soc/tegra/pmc.c | 248 ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 248 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index ea0e11a09c12..6d65194a6e71 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -13,6 +13,9 @@
>  
>  #include <linux/arm-smccc.h>
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/clk-conf.h>
>  #include <linux/clk/tegra.h>
>  #include <linux/debugfs.h>
>  #include <linux/delay.h>
> @@ -48,6 +51,7 @@
>  #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>  #include <dt-bindings/gpio/tegra186-gpio.h>
>  #include <dt-bindings/gpio/tegra194-gpio.h>
> +#include <dt-bindings/soc/tegra-pmc.h>
>  
>  #define PMC_CNTRL			0x0
>  #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
> @@ -100,6 +104,7 @@
>  #define PMC_WAKE2_STATUS		0x168
>  #define PMC_SW_WAKE2_STATUS		0x16c
>  
> +#define PMC_CLK_OUT_CNTRL		0x1a8
>  #define PMC_SENSOR_CTRL			0x1b0
>  #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>  #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
> @@ -155,6 +160,64 @@
>  #define  TEGRA_SMC_PMC_READ	0xaa
>  #define  TEGRA_SMC_PMC_WRITE	0xbb
>  
> +struct pmc_clk {
> +	struct clk_hw	hw;
> +	unsigned long	offs;
> +	u32		mux_mask;
> +	u32		mux_shift;
> +	u32		gate_shift;
> +};
> +
> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
> +
> +struct pmc_clk_init_data {
> +	char *name;
> +	const char *const *parents;
> +	int num_parents;
> +	int clk_id;
> +	u8 mux_shift;
> +	u8 gate_shift;
> +};
> +
> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
> +	"osc_div4", "extern1",
> +};
> +
> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
> +	"osc_div4", "extern2",
> +};
> +
> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
> +	"osc_div4", "extern3",
> +};
> +
> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
> +	{
> +		.name = "clk_out_1",
> +		.parents = clk_out1_parents,
> +		.num_parents = ARRAY_SIZE(clk_out1_parents),
> +		.clk_id = TEGRA_PMC_CLK_OUT_1,

> +		.mux_shift = 6,
> +		.gate_shift = 2,

I'd replace these with a single .shift, given that mux_shift =
gate_shift + 4 for all clocks.

> +	},
> +	{
> +		.name = "clk_out_2",
> +		.parents = clk_out2_parents,
> +		.num_parents = ARRAY_SIZE(clk_out2_parents),
> +		.clk_id = TEGRA_PMC_CLK_OUT_2,
> +		.mux_shift = 14,
> +		.gate_shift = 10,
> +	},
> +	{
> +		.name = "clk_out_3",
> +		.parents = clk_out3_parents,
> +		.num_parents = ARRAY_SIZE(clk_out3_parents),
> +		.clk_id = TEGRA_PMC_CLK_OUT_3,
> +		.mux_shift = 22,
> +		.gate_shift = 18,
> +	},
> +};
> +
>  struct tegra_powergate {
>  	struct generic_pm_domain genpd;
>  	struct tegra_pmc *pmc;
> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>  	 */
>  	const struct tegra_wake_event *wake_events;
>  	unsigned int num_wake_events;
> +
> +	const struct pmc_clk_init_data *pmc_clks_data;
> +	unsigned int num_pmc_clks;
>  };
>  
>  static const char * const tegra186_reset_sources[] = {
> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
>  	return NOTIFY_OK;
>  }
>  
> +static void pmc_clk_fence_udelay(u32 offset)
> +{
> +	tegra_pmc_readl(pmc, offset);
> +	/* pmc clk propagation delay 2 us */
> +	udelay(2);
> +}
> +
> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
> +{
> +	struct pmc_clk *clk = to_pmc_clk(hw);
> +	u32 val;
> +
> +	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
> +	val &= clk->mux_mask;
> +
> +	return val;
> +}
> +
> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct pmc_clk *clk = to_pmc_clk(hw);
> +	u32 val;
> +
> +	val = tegra_pmc_readl(pmc, clk->offs);
> +	val &= ~(clk->mux_mask << clk->mux_shift);
> +	val |= index << clk->mux_shift;
> +	tegra_pmc_writel(pmc, val, clk->offs);
> +	pmc_clk_fence_udelay(clk->offs);
> +
> +	return 0;
> +}
> +
> +static int pmc_clk_is_enabled(struct clk_hw *hw)
> +{
> +	struct pmc_clk *clk = to_pmc_clk(hw);
> +
> +	return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift) ? 1 : 0;
> +}
> +
> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
> +{
> +	u32 val;
> +
> +	val = tegra_pmc_readl(pmc, offs);
> +	val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
> +	tegra_pmc_writel(pmc, val, offs);
> +	pmc_clk_fence_udelay(offs);
> +}
> +
> +static int pmc_clk_enable(struct clk_hw *hw)
> +{
> +	struct pmc_clk *clk = to_pmc_clk(hw);
> +
> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
> +
> +	return 0;
> +}
> +
> +static void pmc_clk_disable(struct clk_hw *hw)
> +{
> +	struct pmc_clk *clk = to_pmc_clk(hw);
> +
> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
> +}
> +
> +static const struct clk_ops pmc_clk_ops = {
> +	.get_parent = pmc_clk_mux_get_parent,
> +	.set_parent = pmc_clk_mux_set_parent,
> +	.determine_rate = __clk_mux_determine_rate,
> +	.is_enabled = pmc_clk_is_enabled,
> +	.enable = pmc_clk_enable,
> +	.disable = pmc_clk_disable,
> +};
> +
> +static struct clk *
> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
> +			   unsigned long offset)
> +{
> +	struct clk_init_data init;
> +	struct pmc_clk *pmc_clk;
> +
> +	pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
> +	if (!pmc_clk)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init.name = data->name;
> +	init.ops = &pmc_clk_ops;
> +	init.parent_names = data->parents;
> +	init.num_parents = data->num_parents;
> +	init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
> +		     CLK_SET_PARENT_GATE;
> +
> +	pmc_clk->hw.init = &init;
> +	pmc_clk->offs = offset;
> +	pmc_clk->mux_mask = 3;

If mux_mask is a constant value, perhaps will be better to replace the
variable with a literal?

#define PMC_CLK_OUT_MUX_MASK	GENMASK(1, 0)

> +	pmc_clk->mux_shift = data->mux_shift;
> +	pmc_clk->gate_shift = data->gate_shift;
> +
> +	return clk_register(NULL, &pmc_clk->hw);
> +}
> +
> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
> +				     struct device_node *np)
> +{
> +	struct clk *clk;
> +	struct clk_onecell_data *clk_data;
> +	unsigned int num_clks;
> +	int i, err = -ENOMEM;
> +
> +	num_clks = pmc->soc->num_pmc_clks;
> +
> +	if (!num_clks)
> +		return;
> +
> +	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
> +	if (!clk_data)
> +		goto err_clk;

What about devm_kmalloc, devm_kcalloc?

> +	clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX, sizeof(*clk_data->clks),
> +				 GFP_KERNEL);
> +	if (!clk_data->clks)
> +		goto free_clkdata;
> +
> +	clk_data->clk_num = TEGRA_PMC_CLK_MAX;
> +
> +	for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
> +		clk_data->clks[i] = ERR_PTR(-ENOENT);
> +
> +	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
> +		const struct pmc_clk_init_data *data;
> +
> +		data = pmc->soc->pmc_clks_data + i;
> +
> +		clk = tegra_pmc_clk_out_register(data, PMC_CLK_OUT_CNTRL);> +		if (IS_ERR(clk)) {
> +			dev_err(pmc->dev,
> +				"unable to register %s\n", data->name);
> +			err = PTR_ERR(clk);
Error codes in a message could be useful.

		err = PTR_ERR_OR_ZERO(clk);
		if (err)
			dev_err(pmc->dev, "unable to register %s: %d\n",
				data->name, err);

> +			goto free_clks;
> +		}

-		clk_data->clks[data->clk_id] = clk;

> +		err = clk_register_clkdev(clk, data->name, NULL);
> +		if (err) {
> +			dev_err(pmc->dev,
> +				"unable to register %s clock lookup\n",
> +				data->name);

			dev_err(pmc->dev,
				"unable to register %s clock lookup: %d\n",
				data->name, err);

> +			goto free_clks;
> +		}

I'd move the assignment here for a bit more consistency.

+		clk_data->clks[data->clk_id] = clk;

> +	}
> +
> +	err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
> +	if (err) {
> +		dev_err(pmc->dev, "failed to add pmc clk provider\n");
> +		goto free_clks;
> +	}

[snip]

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-18  8:30   ` Dmitry Osipenko
@ 2019-12-18  8:35     ` Dmitry Osipenko
  2019-12-18 15:46       ` Sowjanya Komatineni
  2019-12-18 21:44       ` Dmitry Osipenko
  0 siblings, 2 replies; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18  8:35 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

18.12.2019 11:30, Dmitry Osipenko пишет:
> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
>> these PMC clocks are registered by Tegra clock driver with each clock as
>> separate mux and gate clocks using clk_register_mux and clk_register_gate
>> by passing PMC base address and register offsets and PMC programming for
>> these clocks happens through direct PMC access by the clock driver.
>>
>> With this, when PMC is in secure mode any direct PMC access from the
>> non-secure world does not go through and these clocks will not be
>> functional.
>>
>> This patch adds these PMC clocks registration to pmc driver with PMC as
>> a clock provider and registers each clock as single clock.
>>
>> clk_ops callback implementations for these clocks uses tegra_pmc_readl and
>> tegra_pmc_writel which supports PMC programming in both secure mode and
>> non-secure mode.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>>  drivers/soc/tegra/pmc.c | 248 ++++++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 248 insertions(+)
>>
>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>> index ea0e11a09c12..6d65194a6e71 100644
>> --- a/drivers/soc/tegra/pmc.c
>> +++ b/drivers/soc/tegra/pmc.c
>> @@ -13,6 +13,9 @@
>>  
>>  #include <linux/arm-smccc.h>
>>  #include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/clk/clk-conf.h>
>>  #include <linux/clk/tegra.h>
>>  #include <linux/debugfs.h>
>>  #include <linux/delay.h>
>> @@ -48,6 +51,7 @@
>>  #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>  #include <dt-bindings/gpio/tegra186-gpio.h>
>>  #include <dt-bindings/gpio/tegra194-gpio.h>
>> +#include <dt-bindings/soc/tegra-pmc.h>
>>  
>>  #define PMC_CNTRL			0x0
>>  #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
>> @@ -100,6 +104,7 @@
>>  #define PMC_WAKE2_STATUS		0x168
>>  #define PMC_SW_WAKE2_STATUS		0x16c
>>  
>> +#define PMC_CLK_OUT_CNTRL		0x1a8
>>  #define PMC_SENSOR_CTRL			0x1b0
>>  #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>>  #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
>> @@ -155,6 +160,64 @@
>>  #define  TEGRA_SMC_PMC_READ	0xaa
>>  #define  TEGRA_SMC_PMC_WRITE	0xbb
>>  
>> +struct pmc_clk {
>> +	struct clk_hw	hw;
>> +	unsigned long	offs;
>> +	u32		mux_mask;
>> +	u32		mux_shift;
>> +	u32		gate_shift;
>> +};
>> +
>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>> +
>> +struct pmc_clk_init_data {
>> +	char *name;
>> +	const char *const *parents;
>> +	int num_parents;
>> +	int clk_id;
>> +	u8 mux_shift;
>> +	u8 gate_shift;
>> +};
>> +
>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>> +	"osc_div4", "extern1",
>> +};
>> +
>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>> +	"osc_div4", "extern2",
>> +};
>> +
>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>> +	"osc_div4", "extern3",
>> +};
>> +
>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>> +	{
>> +		.name = "clk_out_1",
>> +		.parents = clk_out1_parents,
>> +		.num_parents = ARRAY_SIZE(clk_out1_parents),
>> +		.clk_id = TEGRA_PMC_CLK_OUT_1,
> 
>> +		.mux_shift = 6,
>> +		.gate_shift = 2,
> 
> I'd replace these with a single .shift, given that mux_shift =
> gate_shift + 4 for all clocks.
> 
>> +	},
>> +	{
>> +		.name = "clk_out_2",
>> +		.parents = clk_out2_parents,
>> +		.num_parents = ARRAY_SIZE(clk_out2_parents),
>> +		.clk_id = TEGRA_PMC_CLK_OUT_2,
>> +		.mux_shift = 14,
>> +		.gate_shift = 10,
>> +	},
>> +	{
>> +		.name = "clk_out_3",
>> +		.parents = clk_out3_parents,
>> +		.num_parents = ARRAY_SIZE(clk_out3_parents),
>> +		.clk_id = TEGRA_PMC_CLK_OUT_3,
>> +		.mux_shift = 22,
>> +		.gate_shift = 18,
>> +	},
>> +};
>> +
>>  struct tegra_powergate {
>>  	struct generic_pm_domain genpd;
>>  	struct tegra_pmc *pmc;
>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>  	 */
>>  	const struct tegra_wake_event *wake_events;
>>  	unsigned int num_wake_events;
>> +
>> +	const struct pmc_clk_init_data *pmc_clks_data;
>> +	unsigned int num_pmc_clks;
>>  };
>>  
>>  static const char * const tegra186_reset_sources[] = {
>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
>>  	return NOTIFY_OK;
>>  }
>>  
>> +static void pmc_clk_fence_udelay(u32 offset)
>> +{
>> +	tegra_pmc_readl(pmc, offset);
>> +	/* pmc clk propagation delay 2 us */
>> +	udelay(2);
>> +}
>> +
>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>> +{
>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>> +	u32 val;
>> +
>> +	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>> +	val &= clk->mux_mask;
>> +
>> +	return val;
>> +}
>> +
>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> +{
>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>> +	u32 val;
>> +
>> +	val = tegra_pmc_readl(pmc, clk->offs);
>> +	val &= ~(clk->mux_mask << clk->mux_shift);
>> +	val |= index << clk->mux_shift;
>> +	tegra_pmc_writel(pmc, val, clk->offs);
>> +	pmc_clk_fence_udelay(clk->offs);
>> +
>> +	return 0;
>> +}
>> +
>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>> +{
>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>> +
>> +	return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift) ? 1 : 0;
>> +}
>> +
>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
>> +{
>> +	u32 val;
>> +
>> +	val = tegra_pmc_readl(pmc, offs);
>> +	val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>> +	tegra_pmc_writel(pmc, val, offs);
>> +	pmc_clk_fence_udelay(offs);
>> +}
>> +
>> +static int pmc_clk_enable(struct clk_hw *hw)
>> +{
>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>> +
>> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>> +
>> +	return 0;
>> +}
>> +
>> +static void pmc_clk_disable(struct clk_hw *hw)
>> +{
>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>> +
>> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>> +}
>> +
>> +static const struct clk_ops pmc_clk_ops = {
>> +	.get_parent = pmc_clk_mux_get_parent,
>> +	.set_parent = pmc_clk_mux_set_parent,
>> +	.determine_rate = __clk_mux_determine_rate,
>> +	.is_enabled = pmc_clk_is_enabled,
>> +	.enable = pmc_clk_enable,
>> +	.disable = pmc_clk_disable,
>> +};
>> +
>> +static struct clk *
>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>> +			   unsigned long offset)
>> +{
>> +	struct clk_init_data init;
>> +	struct pmc_clk *pmc_clk;
>> +
>> +	pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>> +	if (!pmc_clk)
>> +		return ERR_PTR(-ENOMEM);
>> +
>> +	init.name = data->name;
>> +	init.ops = &pmc_clk_ops;
>> +	init.parent_names = data->parents;
>> +	init.num_parents = data->num_parents;
>> +	init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>> +		     CLK_SET_PARENT_GATE;
>> +
>> +	pmc_clk->hw.init = &init;
>> +	pmc_clk->offs = offset;
>> +	pmc_clk->mux_mask = 3;
> 
> If mux_mask is a constant value, perhaps will be better to replace the
> variable with a literal?
> 
> #define PMC_CLK_OUT_MUX_MASK	GENMASK(1, 0)

Maybe even:

#define PMC_CLK_OUT_MUX_MASK(c)	GENMASK(c->shift + 1, c->shift)

>> +	pmc_clk->mux_shift = data->mux_shift;
>> +	pmc_clk->gate_shift = data->gate_shift;
>> +
>> +	return clk_register(NULL, &pmc_clk->hw);
>> +}
>> +
>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>> +				     struct device_node *np)
>> +{
>> +	struct clk *clk;
>> +	struct clk_onecell_data *clk_data;
>> +	unsigned int num_clks;
>> +	int i, err = -ENOMEM;
>> +
>> +	num_clks = pmc->soc->num_pmc_clks;
>> +
>> +	if (!num_clks)
>> +		return;
>> +
>> +	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>> +	if (!clk_data)
>> +		goto err_clk;
> 
> What about devm_kmalloc, devm_kcalloc?
> 
>> +	clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX, sizeof(*clk_data->clks),
>> +				 GFP_KERNEL);
>> +	if (!clk_data->clks)
>> +		goto free_clkdata;
>> +
>> +	clk_data->clk_num = TEGRA_PMC_CLK_MAX;
>> +
>> +	for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
>> +		clk_data->clks[i] = ERR_PTR(-ENOENT);
>> +
>> +	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>> +		const struct pmc_clk_init_data *data;
>> +
>> +		data = pmc->soc->pmc_clks_data + i;
>> +
>> +		clk = tegra_pmc_clk_out_register(data, PMC_CLK_OUT_CNTRL);> +		if (IS_ERR(clk)) {
>> +			dev_err(pmc->dev,
>> +				"unable to register %s\n", data->name);
>> +			err = PTR_ERR(clk);
> Error codes in a message could be useful.
> 
> 		err = PTR_ERR_OR_ZERO(clk);
> 		if (err)
> 			dev_err(pmc->dev, "unable to register %s: %d\n",
> 				data->name, err);
> 
>> +			goto free_clks;
>> +		}
> 
> -		clk_data->clks[data->clk_id] = clk;
> 
>> +		err = clk_register_clkdev(clk, data->name, NULL);
>> +		if (err) {
>> +			dev_err(pmc->dev,
>> +				"unable to register %s clock lookup\n",
>> +				data->name);
> 
> 			dev_err(pmc->dev,
> 				"unable to register %s clock lookup: %d\n",
> 				data->name, err);
> 
>> +			goto free_clks;
>> +		}
> 
> I'd move the assignment here for a bit more consistency.
> 
> +		clk_data->clks[data->clk_id] = clk;
> 
>> +	}
>> +
>> +	err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
>> +	if (err) {
>> +		dev_err(pmc->dev, "failed to add pmc clk provider\n");
>> +		goto free_clks;
>> +	}
> 
> [snip]
> 


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-18  7:31           ` Dmitry Osipenko
@ 2019-12-18 15:43             ` Sowjanya Komatineni
  2019-12-18 16:29               ` Dmitry Osipenko
  0 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-18 15:43 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/17/19 11:31 PM, Dmitry Osipenko wrote:
> 18.12.2019 10:22, Dmitry Osipenko пишет:
>> 18.12.2019 10:14, Sowjanya Komatineni пишет:
>>> On 12/17/19 11:01 PM, Dmitry Osipenko wrote:
>>>> 18.12.2019 09:59, Dmitry Osipenko пишет:
>>>>> 17.12.2019 23:04, Sowjanya Komatineni пишет:
>>>>>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
>>>>>> are moved to Tegra PMC driver with pmc as clock provider and using pmc
>>>>>> clock ids.
>>>>>>
>>>>>> New device tree uses clk_out_1 from pmc clock provider.
>>>>>>
>>>>>> So, this patch adds implementation for mclk fallback to extern1 when
>>>>>> retrieving mclk returns -ENOENT to be backward compatible of new device
>>>>>> tree with older kernels.
>>>>>>
>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>> ---
>>>>>>    sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
>>>>>>    1 file changed, 10 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/sound/soc/tegra/tegra_asoc_utils.c
>>>>>> b/sound/soc/tegra/tegra_asoc_utils.c
>>>>>> index fe9ca8acd0fb..1b88c6043082 100644
>>>>>> --- a/sound/soc/tegra/tegra_asoc_utils.c
>>>>>> +++ b/sound/soc/tegra/tegra_asoc_utils.c
>>>>>> @@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct
>>>>>> tegra_asoc_utils_data *data,
>>>>>>        data->clk_cdev1 = devm_clk_get(dev, "mclk");
>>>>>>        if (IS_ERR(data->clk_cdev1)) {
>>>>>>            dev_err(data->dev, "Can't retrieve clk cdev1\n");
>>>>>> -        return PTR_ERR(data->clk_cdev1);
>>>>>> +        if (PTR_ERR(data->clk_cdev1) != -ENOENT)
>>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>>> +        /* Fall back to extern1 */
>>>>>> +        data->clk_cdev1 = devm_clk_get(dev, "extern1");
>>>>>> +        if (IS_ERR(data->clk_cdev1)) {
>>>>>> +            dev_err(data->dev, "Can't retrieve clk extern1\n");
>>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>>> +        }
>>>>>> +
>>>>>> +        dev_err(data->dev, "Falling back to extern1\n");
>>>>>>        }
>>>>>>          /*
>>>>>>
>>>>> [    1.769091] ------------[ cut here ]------------
>>>>> [    1.769249] WARNING: CPU: 2 PID: 1 at drivers/clk/clk.c:954
>>>>> clk_core_disable+0xa5/0x1d4
>>>>> [    1.769330] clk_out_1 already disabled
>>>>> [    1.769459] Modules linked in:
>>>>> [    1.769541] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
>>>>> 5.5.0-rc1-next-20191213-00167-g6b9fbcdac8f3-dirty #266
>>>>> [    1.769676] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
>>>>> [    1.769775] [<c010e4bd>] (unwind_backtrace) from [<c010a0fd>]
>>>>> (show_stack+0x11/0x14)
>>>>> [    1.769918] [<c010a0fd>] (show_stack) from [<c09a37b1>]
>>>>> (dump_stack+0x85/0x94)
>>>>> [    1.770061] [<c09a37b1>] (dump_stack) from [<c011f3d1>]
>>>>> (__warn+0xc1/0xc4)
>>>>> [    1.770144] [<c011f3d1>] (__warn) from [<c011f691>]
>>>>> (warn_slowpath_fmt+0x61/0x78)
>>>>> [    1.770285] [<c011f691>] (warn_slowpath_fmt) from [<c04a0e7d>]
>>>>> (clk_core_disable+0xa5/0x1d4)
>>>>> [    1.770427] [<c04a0e7d>] (clk_core_disable) from [<c04a0fc3>]
>>>>> (clk_core_disable_lock+0x17/0x20)
>>>>> [    1.770516] [<c04a0fc3>] (clk_core_disable_lock) from [<c07792bb>]
>>>>> (tegra_asoc_utils_set_rate+0x53/0x208)
>>>>> [    1.770662] [<c07792bb>] (tegra_asoc_utils_set_rate) from
>>>>> [<c077b8c5>] (tegra_rt5640_probe+0xd5/0x128)
>>>>> [    1.770808] [<c077b8c5>] (tegra_rt5640_probe) from [<c0555eb7>]
>>>>> (platform_drv_probe+0x33/0x68)
>>>>> [    1.770958] [<c0555eb7>] (platform_drv_probe) from [<c055471d>]
>>>>> (really_probe+0x14d/0x240)
>>>>> [    1.771099] [<c055471d>] (really_probe) from [<c055493f>]
>>>>> (driver_probe_device+0x43/0x11c)
>>>>> [    1.771187] [<c055493f>] (driver_probe_device) from [<c0554b25>]
>>>>> (device_driver_attach+0x3d/0x40)
>>>>> [    1.771328] [<c0554b25>] (device_driver_attach) from [<c0554b5f>]
>>>>> (__driver_attach+0x37/0x78)
>>>>> [    1.771469] [<c0554b5f>] (__driver_attach) from [<c05532fb>]
>>>>> (bus_for_each_dev+0x43/0x6c)
>>>>> [    1.771609] [<c05532fb>] (bus_for_each_dev) from [<c0553e0f>]
>>>>> (bus_add_driver+0xe3/0x148)
>>>>> [    1.771692] [<c0553e0f>] (bus_add_driver) from [<c055531d>]
>>>>> (driver_register+0x39/0xa0)
>>>>> [    1.771833] [<c055531d>] (driver_register) from [<c0102c2f>]
>>>>> (do_one_initcall+0x43/0x1bc)
>>>>> [    1.771979] [<c0102c2f>] (do_one_initcall) from [<c1000ce5>]
>>>>> (kernel_init_freeable+0x121/0x194)
>>>>> [    1.772129] [<c1000ce5>] (kernel_init_freeable) from [<c09b40e9>]
>>>>> (kernel_init+0xd/0xd0)
>>>>> [    1.772215] [<c09b40e9>] (kernel_init) from [<c01010bd>]
>>>>> (ret_from_fork+0x11/0x34)
>>>>> [    1.772349] Exception stack(0xde907fb0 to 0xde907ff8)
>>>>>
>>>> Although, that's probably related to the "ASoC: tegra: Add initial
>>>> parent configuration for audio mclk".
>>>>
>>> Actually I see these warnings of already unprepared and already disabled
>>> for pll_a, pll_a_out0, and clk_out_1 even without this whole patch
>>> series as well.
>>>
>>> I think its from tegra_asoc_utils_set_rate() doing clk_disable_unprepare
>>> and these clocks are already unprepared and disabled so its just warning
>>> from clk_core_unprepare and clk_core_disable.
>> Doesn't happen for me without this series.

I looked at wrong log, right earlier clock driver keeps them enabled so 
asoc_utils_set_rate() disables the clock fine but now enabling audio 
clock should be done in asoc_utils_init() to let the 
clk_disable_unprepare from asoc_utils_set_rate not to show this warning.

But actually we don't need to have clock enabled in asoc_utils_init 
prior to invoking asoc_utils_set_rate from utils_init and its just warns 
during sound driver probe because clock is already in disabled state. At 
same time it doesn't harm to have it kept enabled in utils_init. So will 
keep it enabled in asoc_utils_init to prevent this warning to show up.

> But sound works with both old/new device-trees.

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-18  8:35     ` Dmitry Osipenko
@ 2019-12-18 15:46       ` Sowjanya Komatineni
  2019-12-18 15:50         ` Sowjanya Komatineni
  2019-12-18 16:48         ` Dmitry Osipenko
  2019-12-18 21:44       ` Dmitry Osipenko
  1 sibling, 2 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-18 15:46 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/18/19 12:35 AM, Dmitry Osipenko wrote:
> 18.12.2019 11:30, Dmitry Osipenko пишет:
>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
>>> these PMC clocks are registered by Tegra clock driver with each clock as
>>> separate mux and gate clocks using clk_register_mux and clk_register_gate
>>> by passing PMC base address and register offsets and PMC programming for
>>> these clocks happens through direct PMC access by the clock driver.
>>>
>>> With this, when PMC is in secure mode any direct PMC access from the
>>> non-secure world does not go through and these clocks will not be
>>> functional.
>>>
>>> This patch adds these PMC clocks registration to pmc driver with PMC as
>>> a clock provider and registers each clock as single clock.
>>>
>>> clk_ops callback implementations for these clocks uses tegra_pmc_readl and
>>> tegra_pmc_writel which supports PMC programming in both secure mode and
>>> non-secure mode.
>>>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>>   drivers/soc/tegra/pmc.c | 248 ++++++++++++++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 248 insertions(+)
>>>
>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>> index ea0e11a09c12..6d65194a6e71 100644
>>> --- a/drivers/soc/tegra/pmc.c
>>> +++ b/drivers/soc/tegra/pmc.c
>>> @@ -13,6 +13,9 @@
>>>   
>>>   #include <linux/arm-smccc.h>
>>>   #include <linux/clk.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/clkdev.h>
>>> +#include <linux/clk/clk-conf.h>
>>>   #include <linux/clk/tegra.h>
>>>   #include <linux/debugfs.h>
>>>   #include <linux/delay.h>
>>> @@ -48,6 +51,7 @@
>>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>   
>>>   #define PMC_CNTRL			0x0
>>>   #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
>>> @@ -100,6 +104,7 @@
>>>   #define PMC_WAKE2_STATUS		0x168
>>>   #define PMC_SW_WAKE2_STATUS		0x16c
>>>   
>>> +#define PMC_CLK_OUT_CNTRL		0x1a8
>>>   #define PMC_SENSOR_CTRL			0x1b0
>>>   #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>>>   #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
>>> @@ -155,6 +160,64 @@
>>>   #define  TEGRA_SMC_PMC_READ	0xaa
>>>   #define  TEGRA_SMC_PMC_WRITE	0xbb
>>>   
>>> +struct pmc_clk {
>>> +	struct clk_hw	hw;
>>> +	unsigned long	offs;
>>> +	u32		mux_mask;
>>> +	u32		mux_shift;
>>> +	u32		gate_shift;
>>> +};
>>> +
>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>> +
>>> +struct pmc_clk_init_data {
>>> +	char *name;
>>> +	const char *const *parents;
>>> +	int num_parents;
>>> +	int clk_id;
>>> +	u8 mux_shift;
>>> +	u8 gate_shift;
>>> +};
>>> +
>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>> +	"osc_div4", "extern1",
>>> +};
>>> +
>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>> +	"osc_div4", "extern2",
>>> +};
>>> +
>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>> +	"osc_div4", "extern3",
>>> +};
>>> +
>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>> +	{
>>> +		.name = "clk_out_1",
>>> +		.parents = clk_out1_parents,
>>> +		.num_parents = ARRAY_SIZE(clk_out1_parents),
>>> +		.clk_id = TEGRA_PMC_CLK_OUT_1,
>>> +		.mux_shift = 6,
>>> +		.gate_shift = 2,
>> I'd replace these with a single .shift, given that mux_shift =
>> gate_shift + 4 for all clocks.
>>
>>> +	},
>>> +	{
>>> +		.name = "clk_out_2",
>>> +		.parents = clk_out2_parents,
>>> +		.num_parents = ARRAY_SIZE(clk_out2_parents),
>>> +		.clk_id = TEGRA_PMC_CLK_OUT_2,
>>> +		.mux_shift = 14,
>>> +		.gate_shift = 10,
>>> +	},
>>> +	{
>>> +		.name = "clk_out_3",
>>> +		.parents = clk_out3_parents,
>>> +		.num_parents = ARRAY_SIZE(clk_out3_parents),
>>> +		.clk_id = TEGRA_PMC_CLK_OUT_3,
>>> +		.mux_shift = 22,
>>> +		.gate_shift = 18,
>>> +	},
>>> +};
>>> +
>>>   struct tegra_powergate {
>>>   	struct generic_pm_domain genpd;
>>>   	struct tegra_pmc *pmc;
>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>   	 */
>>>   	const struct tegra_wake_event *wake_events;
>>>   	unsigned int num_wake_events;
>>> +
>>> +	const struct pmc_clk_init_data *pmc_clks_data;
>>> +	unsigned int num_pmc_clks;
>>>   };
>>>   
>>>   static const char * const tegra186_reset_sources[] = {
>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
>>>   	return NOTIFY_OK;
>>>   }
>>>   
>>> +static void pmc_clk_fence_udelay(u32 offset)
>>> +{
>>> +	tegra_pmc_readl(pmc, offset);
>>> +	/* pmc clk propagation delay 2 us */
>>> +	udelay(2);
>>> +}
>>> +
>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +	u32 val;
>>> +
>>> +	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>> +	val &= clk->mux_mask;
>>> +
>>> +	return val;
>>> +}
>>> +
>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +	u32 val;
>>> +
>>> +	val = tegra_pmc_readl(pmc, clk->offs);
>>> +	val &= ~(clk->mux_mask << clk->mux_shift);
>>> +	val |= index << clk->mux_shift;
>>> +	tegra_pmc_writel(pmc, val, clk->offs);
>>> +	pmc_clk_fence_udelay(clk->offs);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +
>>> +	return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift) ? 1 : 0;
>>> +}
>>> +
>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
>>> +{
>>> +	u32 val;
>>> +
>>> +	val = tegra_pmc_readl(pmc, offs);
>>> +	val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>> +	tegra_pmc_writel(pmc, val, offs);
>>> +	pmc_clk_fence_udelay(offs);
>>> +}
>>> +
>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +
>>> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +
>>> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>> +}
>>> +
>>> +static const struct clk_ops pmc_clk_ops = {
>>> +	.get_parent = pmc_clk_mux_get_parent,
>>> +	.set_parent = pmc_clk_mux_set_parent,
>>> +	.determine_rate = __clk_mux_determine_rate,
>>> +	.is_enabled = pmc_clk_is_enabled,
>>> +	.enable = pmc_clk_enable,
>>> +	.disable = pmc_clk_disable,
>>> +};
>>> +
>>> +static struct clk *
>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>> +			   unsigned long offset)
>>> +{
>>> +	struct clk_init_data init;
>>> +	struct pmc_clk *pmc_clk;
>>> +
>>> +	pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>> +	if (!pmc_clk)
>>> +		return ERR_PTR(-ENOMEM);
>>> +
>>> +	init.name = data->name;
>>> +	init.ops = &pmc_clk_ops;
>>> +	init.parent_names = data->parents;
>>> +	init.num_parents = data->num_parents;
>>> +	init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>> +		     CLK_SET_PARENT_GATE;
>>> +
>>> +	pmc_clk->hw.init = &init;
>>> +	pmc_clk->offs = offset;
>>> +	pmc_clk->mux_mask = 3;
>> If mux_mask is a constant value, perhaps will be better to replace the
>> variable with a literal?
>>
>> #define PMC_CLK_OUT_MUX_MASK	GENMASK(1, 0)
> Maybe even:
>
> #define PMC_CLK_OUT_MUX_MASK(c)	GENMASK(c->shift + 1, c->shift)
>
>>> +	pmc_clk->mux_shift = data->mux_shift;
>>> +	pmc_clk->gate_shift = data->gate_shift;
>>> +
>>> +	return clk_register(NULL, &pmc_clk->hw);
>>> +}
>>> +
>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>> +				     struct device_node *np)
>>> +{
>>> +	struct clk *clk;
>>> +	struct clk_onecell_data *clk_data;
>>> +	unsigned int num_clks;
>>> +	int i, err = -ENOMEM;
>>> +
>>> +	num_clks = pmc->soc->num_pmc_clks;
>>> +
>>> +	if (!num_clks)
>>> +		return;
>>> +
>>> +	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>> +	if (!clk_data)
>>> +		goto err_clk;
>> What about devm_kmalloc, devm_kcalloc?
>>
>>> +	clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX, sizeof(*clk_data->clks),
>>> +				 GFP_KERNEL);
>>> +	if (!clk_data->clks)
>>> +		goto free_clkdata;
>>> +
>>> +	clk_data->clk_num = TEGRA_PMC_CLK_MAX;
>>> +
>>> +	for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
>>> +		clk_data->clks[i] = ERR_PTR(-ENOENT);
>>> +
>>> +	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>> +		const struct pmc_clk_init_data *data;
>>> +
>>> +		data = pmc->soc->pmc_clks_data + i;
>>> +
>>> +		clk = tegra_pmc_clk_out_register(data, PMC_CLK_OUT_CNTRL);> +		if (IS_ERR(clk)) {
>>> +			dev_err(pmc->dev,
>>> +				"unable to register %s\n", data->name);
>>> +			err = PTR_ERR(clk);
>> Error codes in a message could be useful.

Added error code at end of clock register along with WARN message to 
have it common to show warning with error code for all errors including 
kmalloc and kcalloc.

>>
>> 		err = PTR_ERR_OR_ZERO(clk);
>> 		if (err)
>> 			dev_err(pmc->dev, "unable to register %s: %d\n",
>> 				data->name, err);
>>
>>> +			goto free_clks;
>>> +		}
>> -		clk_data->clks[data->clk_id] = clk;
>>
>>> +		err = clk_register_clkdev(clk, data->name, NULL);
>>> +		if (err) {
>>> +			dev_err(pmc->dev,
>>> +				"unable to register %s clock lookup\n",
>>> +				data->name);
>> 			dev_err(pmc->dev,
>> 				"unable to register %s clock lookup: %d\n",
>> 				data->name, err);
>>
>>> +			goto free_clks;
>>> +		}
>> I'd move the assignment here for a bit more consistency.
>>
>> +		clk_data->clks[data->clk_id] = clk;
>>
>>> +	}
>>> +
>>> +	err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
>>> +	if (err) {
>>> +		dev_err(pmc->dev, "failed to add pmc clk provider\n");
>>> +		goto free_clks;
>>> +	}
>> [snip]
>>


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-18 15:46       ` Sowjanya Komatineni
@ 2019-12-18 15:50         ` Sowjanya Komatineni
  2019-12-18 16:52           ` Dmitry Osipenko
  2019-12-18 16:48         ` Dmitry Osipenko
  1 sibling, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-18 15:50 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/18/19 7:46 AM, Sowjanya Komatineni wrote:
>
> On 12/18/19 12:35 AM, Dmitry Osipenko wrote:
>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
>>>> these PMC clocks are registered by Tegra clock driver with each 
>>>> clock as
>>>> separate mux and gate clocks using clk_register_mux and 
>>>> clk_register_gate
>>>> by passing PMC base address and register offsets and PMC 
>>>> programming for
>>>> these clocks happens through direct PMC access by the clock driver.
>>>>
>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>> non-secure world does not go through and these clocks will not be
>>>> functional.
>>>>
>>>> This patch adds these PMC clocks registration to pmc driver with 
>>>> PMC as
>>>> a clock provider and registers each clock as single clock.
>>>>
>>>> clk_ops callback implementations for these clocks uses 
>>>> tegra_pmc_readl and
>>>> tegra_pmc_writel which supports PMC programming in both secure mode 
>>>> and
>>>> non-secure mode.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>>   drivers/soc/tegra/pmc.c | 248 
>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>   1 file changed, 248 insertions(+)
>>>>
>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>> --- a/drivers/soc/tegra/pmc.c
>>>> +++ b/drivers/soc/tegra/pmc.c
>>>> @@ -13,6 +13,9 @@
>>>>     #include <linux/arm-smccc.h>
>>>>   #include <linux/clk.h>
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/clkdev.h>
>>>> +#include <linux/clk/clk-conf.h>
>>>>   #include <linux/clk/tegra.h>
>>>>   #include <linux/debugfs.h>
>>>>   #include <linux/delay.h>
>>>> @@ -48,6 +51,7 @@
>>>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>     #define PMC_CNTRL            0x0
>>>>   #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR 
>>>> polarity */
>>>> @@ -100,6 +104,7 @@
>>>>   #define PMC_WAKE2_STATUS        0x168
>>>>   #define PMC_SW_WAKE2_STATUS        0x16c
>>>>   +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>   #define PMC_SENSOR_CTRL            0x1b0
>>>>   #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>   #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>> @@ -155,6 +160,64 @@
>>>>   #define  TEGRA_SMC_PMC_READ    0xaa
>>>>   #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>   +struct pmc_clk {
>>>> +    struct clk_hw    hw;
>>>> +    unsigned long    offs;
>>>> +    u32        mux_mask;
>>>> +    u32        mux_shift;
>>>> +    u32        gate_shift;
>>>> +};
>>>> +
>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>> +
>>>> +struct pmc_clk_init_data {
>>>> +    char *name;
>>>> +    const char *const *parents;
>>>> +    int num_parents;
>>>> +    int clk_id;
>>>> +    u8 mux_shift;
>>>> +    u8 gate_shift;
>>>> +};
>>>> +
>>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>>> +    "osc_div4", "extern1",
>>>> +};
>>>> +
>>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>>> +    "osc_div4", "extern2",
>>>> +};
>>>> +
>>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>>> +    "osc_div4", "extern3",
>>>> +};
>>>> +
>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>> +    {
>>>> +        .name = "clk_out_1",
>>>> +        .parents = clk_out1_parents,
>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_1,
>>>> +        .mux_shift = 6,
>>>> +        .gate_shift = 2,
>>> I'd replace these with a single .shift, given that mux_shift =
>>> gate_shift + 4 for all clocks.
>>>
>>>> +    },
>>>> +    {
>>>> +        .name = "clk_out_2",
>>>> +        .parents = clk_out2_parents,
>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_2,
>>>> +        .mux_shift = 14,
>>>> +        .gate_shift = 10,
>>>> +    },
>>>> +    {
>>>> +        .name = "clk_out_3",
>>>> +        .parents = clk_out3_parents,
>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_3,
>>>> +        .mux_shift = 22,
>>>> +        .gate_shift = 18,
>>>> +    },
>>>> +};
>>>> +
>>>>   struct tegra_powergate {
>>>>       struct generic_pm_domain genpd;
>>>>       struct tegra_pmc *pmc;
>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>        */
>>>>       const struct tegra_wake_event *wake_events;
>>>>       unsigned int num_wake_events;
>>>> +
>>>> +    const struct pmc_clk_init_data *pmc_clks_data;
>>>> +    unsigned int num_pmc_clks;
>>>>   };
>>>>     static const char * const tegra186_reset_sources[] = {
>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct 
>>>> notifier_block *nb,
>>>>       return NOTIFY_OK;
>>>>   }
>>>>   +static void pmc_clk_fence_udelay(u32 offset)
>>>> +{
>>>> +    tegra_pmc_readl(pmc, offset);
>>>> +    /* pmc clk propagation delay 2 us */
>>>> +    udelay(2);
>>>> +}
>>>> +
>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +    u32 val;
>>>> +
>>>> +    val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>> +    val &= clk->mux_mask;
>>>> +
>>>> +    return val;
>>>> +}
>>>> +
>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +    u32 val;
>>>> +
>>>> +    val = tegra_pmc_readl(pmc, clk->offs);
>>>> +    val &= ~(clk->mux_mask << clk->mux_shift);
>>>> +    val |= index << clk->mux_shift;
>>>> +    tegra_pmc_writel(pmc, val, clk->offs);
>>>> +    pmc_clk_fence_udelay(clk->offs);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +
>>>> +    return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift) 
>>>> ? 1 : 0;
>>>> +}
>>>> +
>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int 
>>>> state)
>>>> +{
>>>> +    u32 val;
>>>> +
>>>> +    val = tegra_pmc_readl(pmc, offs);
>>>> +    val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>> +    tegra_pmc_writel(pmc, val, offs);
>>>> +    pmc_clk_fence_udelay(offs);
>>>> +}
>>>> +
>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +
>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +
>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>> +}
>>>> +
>>>> +static const struct clk_ops pmc_clk_ops = {
>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>> +    .enable = pmc_clk_enable,
>>>> +    .disable = pmc_clk_disable,
>>>> +};
>>>> +
>>>> +static struct clk *
>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>> +               unsigned long offset)
>>>> +{
>>>> +    struct clk_init_data init;
>>>> +    struct pmc_clk *pmc_clk;
>>>> +
>>>> +    pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>> +    if (!pmc_clk)
>>>> +        return ERR_PTR(-ENOMEM);
>>>> +
>>>> +    init.name = data->name;
>>>> +    init.ops = &pmc_clk_ops;
>>>> +    init.parent_names = data->parents;
>>>> +    init.num_parents = data->num_parents;
>>>> +    init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>> +             CLK_SET_PARENT_GATE;
>>>> +
>>>> +    pmc_clk->hw.init = &init;
>>>> +    pmc_clk->offs = offset;
>>>> +    pmc_clk->mux_mask = 3;
>>> If mux_mask is a constant value, perhaps will be better to replace the
>>> variable with a literal?
>>>
>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>> Maybe even:
>>
>> #define PMC_CLK_OUT_MUX_MASK(c)    GENMASK(c->shift + 1, c->shift)
>>
>>>> +    pmc_clk->mux_shift = data->mux_shift;
>>>> +    pmc_clk->gate_shift = data->gate_shift;
>>>> +
>>>> +    return clk_register(NULL, &pmc_clk->hw);
>>>> +}
>>>> +
>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>> +                     struct device_node *np)
>>>> +{
>>>> +    struct clk *clk;
>>>> +    struct clk_onecell_data *clk_data;
>>>> +    unsigned int num_clks;
>>>> +    int i, err = -ENOMEM;
>>>> +
>>>> +    num_clks = pmc->soc->num_pmc_clks;
>>>> +
>>>> +    if (!num_clks)
>>>> +        return;
>>>> +
>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>> +    if (!clk_data)
>>>> +        goto err_clk;
>>> What about devm_kmalloc, devm_kcalloc?
>>>
>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX, 
>>>> sizeof(*clk_data->clks),
>>>> +                 GFP_KERNEL);
>>>> +    if (!clk_data->clks)
>>>> +        goto free_clkdata;
>>>> +
>>>> +    clk_data->clk_num = TEGRA_PMC_CLK_MAX;
>>>> +
>>>> +    for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
>>>> +        clk_data->clks[i] = ERR_PTR(-ENOENT);
>>>> +
>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>> +        const struct pmc_clk_init_data *data;
>>>> +
>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>> +
>>>> +        clk = tegra_pmc_clk_out_register(data, 
>>>> PMC_CLK_OUT_CNTRL);> +        if (IS_ERR(clk)) {
>>>> +            dev_err(pmc->dev,
>>>> +                "unable to register %s\n", data->name);
>>>> +            err = PTR_ERR(clk);
>>> Error codes in a message could be useful.
>
> Added error code at end of clock register along with WARN message to 
> have it common to show warning with error code for all errors 
> including kmalloc and kcalloc.
>
Sure, With devm_kmalloc and devm_kcalloc, will move error code along 
with message and do return right at point of errors.
>>>
>>>         err = PTR_ERR_OR_ZERO(clk);
>>>         if (err)
>>>             dev_err(pmc->dev, "unable to register %s: %d\n",
>>>                 data->name, err);
>>>
>>>> +            goto free_clks;
>>>> +        }
>>> -        clk_data->clks[data->clk_id] = clk;
>>>
>>>> +        err = clk_register_clkdev(clk, data->name, NULL);
>>>> +        if (err) {
>>>> +            dev_err(pmc->dev,
>>>> +                "unable to register %s clock lookup\n",
>>>> +                data->name);
>>>             dev_err(pmc->dev,
>>>                 "unable to register %s clock lookup: %d\n",
>>>                 data->name, err);
>>>
>>>> +            goto free_clks;
>>>> +        }
>>> I'd move the assignment here for a bit more consistency.
>>>
>>> +        clk_data->clks[data->clk_id] = clk;
>>>
>>>> +    }
>>>> +
>>>> +    err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
>>>> +    if (err) {
>>>> +        dev_err(pmc->dev, "failed to add pmc clk provider\n");
>>>> +        goto free_clks;
>>>> +    }
>>> [snip]
>>>
>

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-18 15:43             ` Sowjanya Komatineni
@ 2019-12-18 16:29               ` Dmitry Osipenko
  2019-12-18 16:32                 ` Sowjanya Komatineni
  0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18 16:29 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

18.12.2019 18:43, Sowjanya Komatineni пишет:
> 
> On 12/17/19 11:31 PM, Dmitry Osipenko wrote:
>> 18.12.2019 10:22, Dmitry Osipenko пишет:
>>> 18.12.2019 10:14, Sowjanya Komatineni пишет:
>>>> On 12/17/19 11:01 PM, Dmitry Osipenko wrote:
>>>>> 18.12.2019 09:59, Dmitry Osipenko пишет:
>>>>>> 17.12.2019 23:04, Sowjanya Komatineni пишет:
>>>>>>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc
>>>>>>> clocks
>>>>>>> are moved to Tegra PMC driver with pmc as clock provider and
>>>>>>> using pmc
>>>>>>> clock ids.
>>>>>>>
>>>>>>> New device tree uses clk_out_1 from pmc clock provider.
>>>>>>>
>>>>>>> So, this patch adds implementation for mclk fallback to extern1 when
>>>>>>> retrieving mclk returns -ENOENT to be backward compatible of new
>>>>>>> device
>>>>>>> tree with older kernels.
>>>>>>>
>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>> ---
>>>>>>>    sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
>>>>>>>    1 file changed, 10 insertions(+), 1 deletion(-)
>>>>>>>
>>>>>>> diff --git a/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>> b/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>> index fe9ca8acd0fb..1b88c6043082 100644
>>>>>>> --- a/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>> +++ b/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>> @@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct
>>>>>>> tegra_asoc_utils_data *data,
>>>>>>>        data->clk_cdev1 = devm_clk_get(dev, "mclk");
>>>>>>>        if (IS_ERR(data->clk_cdev1)) {
>>>>>>>            dev_err(data->dev, "Can't retrieve clk cdev1\n");
>>>>>>> -        return PTR_ERR(data->clk_cdev1);
>>>>>>> +        if (PTR_ERR(data->clk_cdev1) != -ENOENT)
>>>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>>>> +        /* Fall back to extern1 */
>>>>>>> +        data->clk_cdev1 = devm_clk_get(dev, "extern1");
>>>>>>> +        if (IS_ERR(data->clk_cdev1)) {
>>>>>>> +            dev_err(data->dev, "Can't retrieve clk extern1\n");
>>>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>>>> +        }
>>>>>>> +
>>>>>>> +        dev_err(data->dev, "Falling back to extern1\n");
>>>>>>>        }
>>>>>>>          /*
>>>>>>>
>>>>>> [    1.769091] ------------[ cut here ]------------
>>>>>> [    1.769249] WARNING: CPU: 2 PID: 1 at drivers/clk/clk.c:954
>>>>>> clk_core_disable+0xa5/0x1d4
>>>>>> [    1.769330] clk_out_1 already disabled
>>>>>> [    1.769459] Modules linked in:
>>>>>> [    1.769541] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
>>>>>> 5.5.0-rc1-next-20191213-00167-g6b9fbcdac8f3-dirty #266
>>>>>> [    1.769676] Hardware name: NVIDIA Tegra SoC (Flattened Device
>>>>>> Tree)
>>>>>> [    1.769775] [<c010e4bd>] (unwind_backtrace) from [<c010a0fd>]
>>>>>> (show_stack+0x11/0x14)
>>>>>> [    1.769918] [<c010a0fd>] (show_stack) from [<c09a37b1>]
>>>>>> (dump_stack+0x85/0x94)
>>>>>> [    1.770061] [<c09a37b1>] (dump_stack) from [<c011f3d1>]
>>>>>> (__warn+0xc1/0xc4)
>>>>>> [    1.770144] [<c011f3d1>] (__warn) from [<c011f691>]
>>>>>> (warn_slowpath_fmt+0x61/0x78)
>>>>>> [    1.770285] [<c011f691>] (warn_slowpath_fmt) from [<c04a0e7d>]
>>>>>> (clk_core_disable+0xa5/0x1d4)
>>>>>> [    1.770427] [<c04a0e7d>] (clk_core_disable) from [<c04a0fc3>]
>>>>>> (clk_core_disable_lock+0x17/0x20)
>>>>>> [    1.770516] [<c04a0fc3>] (clk_core_disable_lock) from [<c07792bb>]
>>>>>> (tegra_asoc_utils_set_rate+0x53/0x208)
>>>>>> [    1.770662] [<c07792bb>] (tegra_asoc_utils_set_rate) from
>>>>>> [<c077b8c5>] (tegra_rt5640_probe+0xd5/0x128)
>>>>>> [    1.770808] [<c077b8c5>] (tegra_rt5640_probe) from [<c0555eb7>]
>>>>>> (platform_drv_probe+0x33/0x68)
>>>>>> [    1.770958] [<c0555eb7>] (platform_drv_probe) from [<c055471d>]
>>>>>> (really_probe+0x14d/0x240)
>>>>>> [    1.771099] [<c055471d>] (really_probe) from [<c055493f>]
>>>>>> (driver_probe_device+0x43/0x11c)
>>>>>> [    1.771187] [<c055493f>] (driver_probe_device) from [<c0554b25>]
>>>>>> (device_driver_attach+0x3d/0x40)
>>>>>> [    1.771328] [<c0554b25>] (device_driver_attach) from [<c0554b5f>]
>>>>>> (__driver_attach+0x37/0x78)
>>>>>> [    1.771469] [<c0554b5f>] (__driver_attach) from [<c05532fb>]
>>>>>> (bus_for_each_dev+0x43/0x6c)
>>>>>> [    1.771609] [<c05532fb>] (bus_for_each_dev) from [<c0553e0f>]
>>>>>> (bus_add_driver+0xe3/0x148)
>>>>>> [    1.771692] [<c0553e0f>] (bus_add_driver) from [<c055531d>]
>>>>>> (driver_register+0x39/0xa0)
>>>>>> [    1.771833] [<c055531d>] (driver_register) from [<c0102c2f>]
>>>>>> (do_one_initcall+0x43/0x1bc)
>>>>>> [    1.771979] [<c0102c2f>] (do_one_initcall) from [<c1000ce5>]
>>>>>> (kernel_init_freeable+0x121/0x194)
>>>>>> [    1.772129] [<c1000ce5>] (kernel_init_freeable) from [<c09b40e9>]
>>>>>> (kernel_init+0xd/0xd0)
>>>>>> [    1.772215] [<c09b40e9>] (kernel_init) from [<c01010bd>]
>>>>>> (ret_from_fork+0x11/0x34)
>>>>>> [    1.772349] Exception stack(0xde907fb0 to 0xde907ff8)
>>>>>>
>>>>> Although, that's probably related to the "ASoC: tegra: Add initial
>>>>> parent configuration for audio mclk".
>>>>>
>>>> Actually I see these warnings of already unprepared and already
>>>> disabled
>>>> for pll_a, pll_a_out0, and clk_out_1 even without this whole patch
>>>> series as well.
>>>>
>>>> I think its from tegra_asoc_utils_set_rate() doing
>>>> clk_disable_unprepare
>>>> and these clocks are already unprepared and disabled so its just
>>>> warning
>>>> from clk_core_unprepare and clk_core_disable.
>>> Doesn't happen for me without this series.
> 
> I looked at wrong log, right earlier clock driver keeps them enabled so
> asoc_utils_set_rate() disables the clock fine but now enabling audio
> clock should be done in asoc_utils_init() to let the
> clk_disable_unprepare from asoc_utils_set_rate not to show this warning.
> 
> But actually we don't need to have clock enabled in asoc_utils_init
> prior to invoking asoc_utils_set_rate from utils_init and its just warns
> during sound driver probe because clock is already in disabled state. At
> same time it doesn't harm to have it kept enabled in utils_init. So will
> keep it enabled in asoc_utils_init to prevent this warning to show up.
> 
>> But sound works with both old/new device-trees.

The rule of thumb: don't enable anything when it shouldn't be enabled.
If clocks are disabled at the time of drivers probe, then drivers
shouldn't disable the clocks.

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-18 16:29               ` Dmitry Osipenko
@ 2019-12-18 16:32                 ` Sowjanya Komatineni
  2019-12-18 16:34                   ` Dmitry Osipenko
  0 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-18 16:32 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/18/19 8:29 AM, Dmitry Osipenko wrote:
> 18.12.2019 18:43, Sowjanya Komatineni пишет:
>> On 12/17/19 11:31 PM, Dmitry Osipenko wrote:
>>> 18.12.2019 10:22, Dmitry Osipenko пишет:
>>>> 18.12.2019 10:14, Sowjanya Komatineni пишет:
>>>>> On 12/17/19 11:01 PM, Dmitry Osipenko wrote:
>>>>>> 18.12.2019 09:59, Dmitry Osipenko пишет:
>>>>>>> 17.12.2019 23:04, Sowjanya Komatineni пишет:
>>>>>>>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc
>>>>>>>> clocks
>>>>>>>> are moved to Tegra PMC driver with pmc as clock provider and
>>>>>>>> using pmc
>>>>>>>> clock ids.
>>>>>>>>
>>>>>>>> New device tree uses clk_out_1 from pmc clock provider.
>>>>>>>>
>>>>>>>> So, this patch adds implementation for mclk fallback to extern1 when
>>>>>>>> retrieving mclk returns -ENOENT to be backward compatible of new
>>>>>>>> device
>>>>>>>> tree with older kernels.
>>>>>>>>
>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>> ---
>>>>>>>>     sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
>>>>>>>>     1 file changed, 10 insertions(+), 1 deletion(-)
>>>>>>>>
>>>>>>>> diff --git a/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>>> b/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>>> index fe9ca8acd0fb..1b88c6043082 100644
>>>>>>>> --- a/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>>> +++ b/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>>> @@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct
>>>>>>>> tegra_asoc_utils_data *data,
>>>>>>>>         data->clk_cdev1 = devm_clk_get(dev, "mclk");
>>>>>>>>         if (IS_ERR(data->clk_cdev1)) {
>>>>>>>>             dev_err(data->dev, "Can't retrieve clk cdev1\n");
>>>>>>>> -        return PTR_ERR(data->clk_cdev1);
>>>>>>>> +        if (PTR_ERR(data->clk_cdev1) != -ENOENT)
>>>>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>>>>> +        /* Fall back to extern1 */
>>>>>>>> +        data->clk_cdev1 = devm_clk_get(dev, "extern1");
>>>>>>>> +        if (IS_ERR(data->clk_cdev1)) {
>>>>>>>> +            dev_err(data->dev, "Can't retrieve clk extern1\n");
>>>>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>>>>> +        }
>>>>>>>> +
>>>>>>>> +        dev_err(data->dev, "Falling back to extern1\n");
>>>>>>>>         }
>>>>>>>>           /*
>>>>>>>>
>>>>>>> [    1.769091] ------------[ cut here ]------------
>>>>>>> [    1.769249] WARNING: CPU: 2 PID: 1 at drivers/clk/clk.c:954
>>>>>>> clk_core_disable+0xa5/0x1d4
>>>>>>> [    1.769330] clk_out_1 already disabled
>>>>>>> [    1.769459] Modules linked in:
>>>>>>> [    1.769541] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
>>>>>>> 5.5.0-rc1-next-20191213-00167-g6b9fbcdac8f3-dirty #266
>>>>>>> [    1.769676] Hardware name: NVIDIA Tegra SoC (Flattened Device
>>>>>>> Tree)
>>>>>>> [    1.769775] [<c010e4bd>] (unwind_backtrace) from [<c010a0fd>]
>>>>>>> (show_stack+0x11/0x14)
>>>>>>> [    1.769918] [<c010a0fd>] (show_stack) from [<c09a37b1>]
>>>>>>> (dump_stack+0x85/0x94)
>>>>>>> [    1.770061] [<c09a37b1>] (dump_stack) from [<c011f3d1>]
>>>>>>> (__warn+0xc1/0xc4)
>>>>>>> [    1.770144] [<c011f3d1>] (__warn) from [<c011f691>]
>>>>>>> (warn_slowpath_fmt+0x61/0x78)
>>>>>>> [    1.770285] [<c011f691>] (warn_slowpath_fmt) from [<c04a0e7d>]
>>>>>>> (clk_core_disable+0xa5/0x1d4)
>>>>>>> [    1.770427] [<c04a0e7d>] (clk_core_disable) from [<c04a0fc3>]
>>>>>>> (clk_core_disable_lock+0x17/0x20)
>>>>>>> [    1.770516] [<c04a0fc3>] (clk_core_disable_lock) from [<c07792bb>]
>>>>>>> (tegra_asoc_utils_set_rate+0x53/0x208)
>>>>>>> [    1.770662] [<c07792bb>] (tegra_asoc_utils_set_rate) from
>>>>>>> [<c077b8c5>] (tegra_rt5640_probe+0xd5/0x128)
>>>>>>> [    1.770808] [<c077b8c5>] (tegra_rt5640_probe) from [<c0555eb7>]
>>>>>>> (platform_drv_probe+0x33/0x68)
>>>>>>> [    1.770958] [<c0555eb7>] (platform_drv_probe) from [<c055471d>]
>>>>>>> (really_probe+0x14d/0x240)
>>>>>>> [    1.771099] [<c055471d>] (really_probe) from [<c055493f>]
>>>>>>> (driver_probe_device+0x43/0x11c)
>>>>>>> [    1.771187] [<c055493f>] (driver_probe_device) from [<c0554b25>]
>>>>>>> (device_driver_attach+0x3d/0x40)
>>>>>>> [    1.771328] [<c0554b25>] (device_driver_attach) from [<c0554b5f>]
>>>>>>> (__driver_attach+0x37/0x78)
>>>>>>> [    1.771469] [<c0554b5f>] (__driver_attach) from [<c05532fb>]
>>>>>>> (bus_for_each_dev+0x43/0x6c)
>>>>>>> [    1.771609] [<c05532fb>] (bus_for_each_dev) from [<c0553e0f>]
>>>>>>> (bus_add_driver+0xe3/0x148)
>>>>>>> [    1.771692] [<c0553e0f>] (bus_add_driver) from [<c055531d>]
>>>>>>> (driver_register+0x39/0xa0)
>>>>>>> [    1.771833] [<c055531d>] (driver_register) from [<c0102c2f>]
>>>>>>> (do_one_initcall+0x43/0x1bc)
>>>>>>> [    1.771979] [<c0102c2f>] (do_one_initcall) from [<c1000ce5>]
>>>>>>> (kernel_init_freeable+0x121/0x194)
>>>>>>> [    1.772129] [<c1000ce5>] (kernel_init_freeable) from [<c09b40e9>]
>>>>>>> (kernel_init+0xd/0xd0)
>>>>>>> [    1.772215] [<c09b40e9>] (kernel_init) from [<c01010bd>]
>>>>>>> (ret_from_fork+0x11/0x34)
>>>>>>> [    1.772349] Exception stack(0xde907fb0 to 0xde907ff8)
>>>>>>>
>>>>>> Although, that's probably related to the "ASoC: tegra: Add initial
>>>>>> parent configuration for audio mclk".
>>>>>>
>>>>> Actually I see these warnings of already unprepared and already
>>>>> disabled
>>>>> for pll_a, pll_a_out0, and clk_out_1 even without this whole patch
>>>>> series as well.
>>>>>
>>>>> I think its from tegra_asoc_utils_set_rate() doing
>>>>> clk_disable_unprepare
>>>>> and these clocks are already unprepared and disabled so its just
>>>>> warning
>>>>> from clk_core_unprepare and clk_core_disable.
>>>> Doesn't happen for me without this series.
>> I looked at wrong log, right earlier clock driver keeps them enabled so
>> asoc_utils_set_rate() disables the clock fine but now enabling audio
>> clock should be done in asoc_utils_init() to let the
>> clk_disable_unprepare from asoc_utils_set_rate not to show this warning.
>>
>> But actually we don't need to have clock enabled in asoc_utils_init
>> prior to invoking asoc_utils_set_rate from utils_init and its just warns
>> during sound driver probe because clock is already in disabled state. At
>> same time it doesn't harm to have it kept enabled in utils_init. So will
>> keep it enabled in asoc_utils_init to prevent this warning to show up.
>>
>>> But sound works with both old/new device-trees.
> The rule of thumb: don't enable anything when it shouldn't be enabled.
> If clocks are disabled at the time of drivers probe, then drivers
> shouldn't disable the clocks.
Will fix asoc_utils_set_rate to disable only when its enabled.

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 13/19] ASoC: tegra: Add fallback implementation for audio mclk
  2019-12-18 16:32                 ` Sowjanya Komatineni
@ 2019-12-18 16:34                   ` Dmitry Osipenko
  0 siblings, 0 replies; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18 16:34 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

18.12.2019 19:32, Sowjanya Komatineni пишет:
> 
> On 12/18/19 8:29 AM, Dmitry Osipenko wrote:
>> 18.12.2019 18:43, Sowjanya Komatineni пишет:
>>> On 12/17/19 11:31 PM, Dmitry Osipenko wrote:
>>>> 18.12.2019 10:22, Dmitry Osipenko пишет:
>>>>> 18.12.2019 10:14, Sowjanya Komatineni пишет:
>>>>>> On 12/17/19 11:01 PM, Dmitry Osipenko wrote:
>>>>>>> 18.12.2019 09:59, Dmitry Osipenko пишет:
>>>>>>>> 17.12.2019 23:04, Sowjanya Komatineni пишет:
>>>>>>>>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc
>>>>>>>>> clocks
>>>>>>>>> are moved to Tegra PMC driver with pmc as clock provider and
>>>>>>>>> using pmc
>>>>>>>>> clock ids.
>>>>>>>>>
>>>>>>>>> New device tree uses clk_out_1 from pmc clock provider.
>>>>>>>>>
>>>>>>>>> So, this patch adds implementation for mclk fallback to extern1
>>>>>>>>> when
>>>>>>>>> retrieving mclk returns -ENOENT to be backward compatible of new
>>>>>>>>> device
>>>>>>>>> tree with older kernels.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>> ---
>>>>>>>>>     sound/soc/tegra/tegra_asoc_utils.c | 11 ++++++++++-
>>>>>>>>>     1 file changed, 10 insertions(+), 1 deletion(-)
>>>>>>>>>
>>>>>>>>> diff --git a/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>>>> b/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>>>> index fe9ca8acd0fb..1b88c6043082 100644
>>>>>>>>> --- a/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>>>> +++ b/sound/soc/tegra/tegra_asoc_utils.c
>>>>>>>>> @@ -191,7 +191,16 @@ int tegra_asoc_utils_init(struct
>>>>>>>>> tegra_asoc_utils_data *data,
>>>>>>>>>         data->clk_cdev1 = devm_clk_get(dev, "mclk");
>>>>>>>>>         if (IS_ERR(data->clk_cdev1)) {
>>>>>>>>>             dev_err(data->dev, "Can't retrieve clk cdev1\n");
>>>>>>>>> -        return PTR_ERR(data->clk_cdev1);
>>>>>>>>> +        if (PTR_ERR(data->clk_cdev1) != -ENOENT)
>>>>>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>>>>>> +        /* Fall back to extern1 */
>>>>>>>>> +        data->clk_cdev1 = devm_clk_get(dev, "extern1");
>>>>>>>>> +        if (IS_ERR(data->clk_cdev1)) {
>>>>>>>>> +            dev_err(data->dev, "Can't retrieve clk extern1\n");
>>>>>>>>> +            return PTR_ERR(data->clk_cdev1);
>>>>>>>>> +        }
>>>>>>>>> +
>>>>>>>>> +        dev_err(data->dev, "Falling back to extern1\n");
>>>>>>>>>         }
>>>>>>>>>           /*
>>>>>>>>>
>>>>>>>> [    1.769091] ------------[ cut here ]------------
>>>>>>>> [    1.769249] WARNING: CPU: 2 PID: 1 at drivers/clk/clk.c:954
>>>>>>>> clk_core_disable+0xa5/0x1d4
>>>>>>>> [    1.769330] clk_out_1 already disabled
>>>>>>>> [    1.769459] Modules linked in:
>>>>>>>> [    1.769541] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
>>>>>>>> 5.5.0-rc1-next-20191213-00167-g6b9fbcdac8f3-dirty #266
>>>>>>>> [    1.769676] Hardware name: NVIDIA Tegra SoC (Flattened Device
>>>>>>>> Tree)
>>>>>>>> [    1.769775] [<c010e4bd>] (unwind_backtrace) from [<c010a0fd>]
>>>>>>>> (show_stack+0x11/0x14)
>>>>>>>> [    1.769918] [<c010a0fd>] (show_stack) from [<c09a37b1>]
>>>>>>>> (dump_stack+0x85/0x94)
>>>>>>>> [    1.770061] [<c09a37b1>] (dump_stack) from [<c011f3d1>]
>>>>>>>> (__warn+0xc1/0xc4)
>>>>>>>> [    1.770144] [<c011f3d1>] (__warn) from [<c011f691>]
>>>>>>>> (warn_slowpath_fmt+0x61/0x78)
>>>>>>>> [    1.770285] [<c011f691>] (warn_slowpath_fmt) from [<c04a0e7d>]
>>>>>>>> (clk_core_disable+0xa5/0x1d4)
>>>>>>>> [    1.770427] [<c04a0e7d>] (clk_core_disable) from [<c04a0fc3>]
>>>>>>>> (clk_core_disable_lock+0x17/0x20)
>>>>>>>> [    1.770516] [<c04a0fc3>] (clk_core_disable_lock) from
>>>>>>>> [<c07792bb>]
>>>>>>>> (tegra_asoc_utils_set_rate+0x53/0x208)
>>>>>>>> [    1.770662] [<c07792bb>] (tegra_asoc_utils_set_rate) from
>>>>>>>> [<c077b8c5>] (tegra_rt5640_probe+0xd5/0x128)
>>>>>>>> [    1.770808] [<c077b8c5>] (tegra_rt5640_probe) from [<c0555eb7>]
>>>>>>>> (platform_drv_probe+0x33/0x68)
>>>>>>>> [    1.770958] [<c0555eb7>] (platform_drv_probe) from [<c055471d>]
>>>>>>>> (really_probe+0x14d/0x240)
>>>>>>>> [    1.771099] [<c055471d>] (really_probe) from [<c055493f>]
>>>>>>>> (driver_probe_device+0x43/0x11c)
>>>>>>>> [    1.771187] [<c055493f>] (driver_probe_device) from [<c0554b25>]
>>>>>>>> (device_driver_attach+0x3d/0x40)
>>>>>>>> [    1.771328] [<c0554b25>] (device_driver_attach) from
>>>>>>>> [<c0554b5f>]
>>>>>>>> (__driver_attach+0x37/0x78)
>>>>>>>> [    1.771469] [<c0554b5f>] (__driver_attach) from [<c05532fb>]
>>>>>>>> (bus_for_each_dev+0x43/0x6c)
>>>>>>>> [    1.771609] [<c05532fb>] (bus_for_each_dev) from [<c0553e0f>]
>>>>>>>> (bus_add_driver+0xe3/0x148)
>>>>>>>> [    1.771692] [<c0553e0f>] (bus_add_driver) from [<c055531d>]
>>>>>>>> (driver_register+0x39/0xa0)
>>>>>>>> [    1.771833] [<c055531d>] (driver_register) from [<c0102c2f>]
>>>>>>>> (do_one_initcall+0x43/0x1bc)
>>>>>>>> [    1.771979] [<c0102c2f>] (do_one_initcall) from [<c1000ce5>]
>>>>>>>> (kernel_init_freeable+0x121/0x194)
>>>>>>>> [    1.772129] [<c1000ce5>] (kernel_init_freeable) from
>>>>>>>> [<c09b40e9>]
>>>>>>>> (kernel_init+0xd/0xd0)
>>>>>>>> [    1.772215] [<c09b40e9>] (kernel_init) from [<c01010bd>]
>>>>>>>> (ret_from_fork+0x11/0x34)
>>>>>>>> [    1.772349] Exception stack(0xde907fb0 to 0xde907ff8)
>>>>>>>>
>>>>>>> Although, that's probably related to the "ASoC: tegra: Add initial
>>>>>>> parent configuration for audio mclk".
>>>>>>>
>>>>>> Actually I see these warnings of already unprepared and already
>>>>>> disabled
>>>>>> for pll_a, pll_a_out0, and clk_out_1 even without this whole patch
>>>>>> series as well.
>>>>>>
>>>>>> I think its from tegra_asoc_utils_set_rate() doing
>>>>>> clk_disable_unprepare
>>>>>> and these clocks are already unprepared and disabled so its just
>>>>>> warning
>>>>>> from clk_core_unprepare and clk_core_disable.
>>>>> Doesn't happen for me without this series.
>>> I looked at wrong log, right earlier clock driver keeps them enabled so
>>> asoc_utils_set_rate() disables the clock fine but now enabling audio
>>> clock should be done in asoc_utils_init() to let the
>>> clk_disable_unprepare from asoc_utils_set_rate not to show this warning.
>>>
>>> But actually we don't need to have clock enabled in asoc_utils_init
>>> prior to invoking asoc_utils_set_rate from utils_init and its just warns
>>> during sound driver probe because clock is already in disabled state. At
>>> same time it doesn't harm to have it kept enabled in utils_init. So will
>>> keep it enabled in asoc_utils_init to prevent this warning to show up.
>>>
>>>> But sound works with both old/new device-trees.
>> The rule of thumb: don't enable anything when it shouldn't be enabled.
>> If clocks are disabled at the time of drivers probe, then drivers
>> shouldn't disable the clocks.
> Will fix asoc_utils_set_rate to disable only when its enabled.

BTW, you should CC ALSA maintainers for the audio patches. Perhaps it's
not worth to CC ALSA's ML since it requires registration and spams on
every reply.

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-18 15:46       ` Sowjanya Komatineni
  2019-12-18 15:50         ` Sowjanya Komatineni
@ 2019-12-18 16:48         ` Dmitry Osipenko
  1 sibling, 0 replies; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18 16:48 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

18.12.2019 18:46, Sowjanya Komatineni пишет:
> 
> On 12/18/19 12:35 AM, Dmitry Osipenko wrote:
>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
>>>> these PMC clocks are registered by Tegra clock driver with each
>>>> clock as
>>>> separate mux and gate clocks using clk_register_mux and
>>>> clk_register_gate
>>>> by passing PMC base address and register offsets and PMC programming
>>>> for
>>>> these clocks happens through direct PMC access by the clock driver.
>>>>
>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>> non-secure world does not go through and these clocks will not be
>>>> functional.
>>>>
>>>> This patch adds these PMC clocks registration to pmc driver with PMC as
>>>> a clock provider and registers each clock as single clock.
>>>>
>>>> clk_ops callback implementations for these clocks uses
>>>> tegra_pmc_readl and
>>>> tegra_pmc_writel which supports PMC programming in both secure mode and
>>>> non-secure mode.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>>   drivers/soc/tegra/pmc.c | 248
>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>   1 file changed, 248 insertions(+)
>>>>
>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>> --- a/drivers/soc/tegra/pmc.c
>>>> +++ b/drivers/soc/tegra/pmc.c
>>>> @@ -13,6 +13,9 @@
>>>>     #include <linux/arm-smccc.h>
>>>>   #include <linux/clk.h>
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/clkdev.h>
>>>> +#include <linux/clk/clk-conf.h>
>>>>   #include <linux/clk/tegra.h>
>>>>   #include <linux/debugfs.h>
>>>>   #include <linux/delay.h>
>>>> @@ -48,6 +51,7 @@
>>>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>     #define PMC_CNTRL            0x0
>>>>   #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>> polarity */
>>>> @@ -100,6 +104,7 @@
>>>>   #define PMC_WAKE2_STATUS        0x168
>>>>   #define PMC_SW_WAKE2_STATUS        0x16c
>>>>   +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>   #define PMC_SENSOR_CTRL            0x1b0
>>>>   #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>   #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>> @@ -155,6 +160,64 @@
>>>>   #define  TEGRA_SMC_PMC_READ    0xaa
>>>>   #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>   +struct pmc_clk {
>>>> +    struct clk_hw    hw;
>>>> +    unsigned long    offs;
>>>> +    u32        mux_mask;
>>>> +    u32        mux_shift;
>>>> +    u32        gate_shift;
>>>> +};
>>>> +
>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>> +
>>>> +struct pmc_clk_init_data {
>>>> +    char *name;
>>>> +    const char *const *parents;
>>>> +    int num_parents;
>>>> +    int clk_id;
>>>> +    u8 mux_shift;
>>>> +    u8 gate_shift;
>>>> +};
>>>> +
>>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>>> +    "osc_div4", "extern1",
>>>> +};
>>>> +
>>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>>> +    "osc_div4", "extern2",
>>>> +};
>>>> +
>>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>>> +    "osc_div4", "extern3",
>>>> +};
>>>> +
>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>> +    {
>>>> +        .name = "clk_out_1",
>>>> +        .parents = clk_out1_parents,
>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_1,
>>>> +        .mux_shift = 6,
>>>> +        .gate_shift = 2,
>>> I'd replace these with a single .shift, given that mux_shift =
>>> gate_shift + 4 for all clocks.
>>>
>>>> +    },
>>>> +    {
>>>> +        .name = "clk_out_2",
>>>> +        .parents = clk_out2_parents,
>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_2,
>>>> +        .mux_shift = 14,
>>>> +        .gate_shift = 10,
>>>> +    },
>>>> +    {
>>>> +        .name = "clk_out_3",
>>>> +        .parents = clk_out3_parents,
>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_3,
>>>> +        .mux_shift = 22,
>>>> +        .gate_shift = 18,
>>>> +    },
>>>> +};
>>>> +
>>>>   struct tegra_powergate {
>>>>       struct generic_pm_domain genpd;
>>>>       struct tegra_pmc *pmc;
>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>        */
>>>>       const struct tegra_wake_event *wake_events;
>>>>       unsigned int num_wake_events;
>>>> +
>>>> +    const struct pmc_clk_init_data *pmc_clks_data;
>>>> +    unsigned int num_pmc_clks;
>>>>   };
>>>>     static const char * const tegra186_reset_sources[] = {
>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct
>>>> notifier_block *nb,
>>>>       return NOTIFY_OK;
>>>>   }
>>>>   +static void pmc_clk_fence_udelay(u32 offset)
>>>> +{
>>>> +    tegra_pmc_readl(pmc, offset);
>>>> +    /* pmc clk propagation delay 2 us */
>>>> +    udelay(2);
>>>> +}
>>>> +
>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +    u32 val;
>>>> +
>>>> +    val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>> +    val &= clk->mux_mask;
>>>> +
>>>> +    return val;
>>>> +}
>>>> +
>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +    u32 val;
>>>> +
>>>> +    val = tegra_pmc_readl(pmc, clk->offs);
>>>> +    val &= ~(clk->mux_mask << clk->mux_shift);
>>>> +    val |= index << clk->mux_shift;
>>>> +    tegra_pmc_writel(pmc, val, clk->offs);
>>>> +    pmc_clk_fence_udelay(clk->offs);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +
>>>> +    return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift) ?
>>>> 1 : 0;
>>>> +}
>>>> +
>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int
>>>> state)
>>>> +{
>>>> +    u32 val;
>>>> +
>>>> +    val = tegra_pmc_readl(pmc, offs);
>>>> +    val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>> +    tegra_pmc_writel(pmc, val, offs);
>>>> +    pmc_clk_fence_udelay(offs);
>>>> +}
>>>> +
>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +
>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>> +{
>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +
>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>> +}
>>>> +
>>>> +static const struct clk_ops pmc_clk_ops = {
>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>> +    .enable = pmc_clk_enable,
>>>> +    .disable = pmc_clk_disable,
>>>> +};
>>>> +
>>>> +static struct clk *
>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>> +               unsigned long offset)
>>>> +{
>>>> +    struct clk_init_data init;
>>>> +    struct pmc_clk *pmc_clk;
>>>> +
>>>> +    pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>> +    if (!pmc_clk)
>>>> +        return ERR_PTR(-ENOMEM);
>>>> +
>>>> +    init.name = data->name;
>>>> +    init.ops = &pmc_clk_ops;
>>>> +    init.parent_names = data->parents;
>>>> +    init.num_parents = data->num_parents;
>>>> +    init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>> +             CLK_SET_PARENT_GATE;
>>>> +
>>>> +    pmc_clk->hw.init = &init;
>>>> +    pmc_clk->offs = offset;
>>>> +    pmc_clk->mux_mask = 3;
>>> If mux_mask is a constant value, perhaps will be better to replace the
>>> variable with a literal?
>>>
>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>> Maybe even:
>>
>> #define PMC_CLK_OUT_MUX_MASK(c)    GENMASK(c->shift + 1, c->shift)
>>
>>>> +    pmc_clk->mux_shift = data->mux_shift;
>>>> +    pmc_clk->gate_shift = data->gate_shift;
>>>> +
>>>> +    return clk_register(NULL, &pmc_clk->hw);
>>>> +}
>>>> +
>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>> +                     struct device_node *np)
>>>> +{
>>>> +    struct clk *clk;
>>>> +    struct clk_onecell_data *clk_data;
>>>> +    unsigned int num_clks;
>>>> +    int i, err = -ENOMEM;
>>>> +
>>>> +    num_clks = pmc->soc->num_pmc_clks;
>>>> +
>>>> +    if (!num_clks)
>>>> +        return;
>>>> +
>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>> +    if (!clk_data)
>>>> +        goto err_clk;
>>> What about devm_kmalloc, devm_kcalloc?
>>>
>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>> sizeof(*clk_data->clks),
>>>> +                 GFP_KERNEL);
>>>> +    if (!clk_data->clks)
>>>> +        goto free_clkdata;
>>>> +
>>>> +    clk_data->clk_num = TEGRA_PMC_CLK_MAX;
>>>> +
>>>> +    for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
>>>> +        clk_data->clks[i] = ERR_PTR(-ENOENT);
>>>> +
>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>> +        const struct pmc_clk_init_data *data;
>>>> +
>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>> +
>>>> +        clk = tegra_pmc_clk_out_register(data, PMC_CLK_OUT_CNTRL);>
>>>> +        if (IS_ERR(clk)) {
>>>> +            dev_err(pmc->dev,
>>>> +                "unable to register %s\n", data->name);
>>>> +            err = PTR_ERR(clk);
>>> Error codes in a message could be useful.
> 
> Added error code at end of clock register along with WARN message to
> have it common to show warning with error code for all errors including
> kmalloc and kcalloc.

What about dev_WARN()?

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-18 15:50         ` Sowjanya Komatineni
@ 2019-12-18 16:52           ` Dmitry Osipenko
  2019-12-18 17:00             ` Sowjanya Komatineni
  0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18 16:52 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

18.12.2019 18:50, Sowjanya Komatineni пишет:
> 
> On 12/18/19 7:46 AM, Sowjanya Komatineni wrote:
>>
>> On 12/18/19 12:35 AM, Dmitry Osipenko wrote:
>>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
>>>>> these PMC clocks are registered by Tegra clock driver with each
>>>>> clock as
>>>>> separate mux and gate clocks using clk_register_mux and
>>>>> clk_register_gate
>>>>> by passing PMC base address and register offsets and PMC
>>>>> programming for
>>>>> these clocks happens through direct PMC access by the clock driver.
>>>>>
>>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>>> non-secure world does not go through and these clocks will not be
>>>>> functional.
>>>>>
>>>>> This patch adds these PMC clocks registration to pmc driver with
>>>>> PMC as
>>>>> a clock provider and registers each clock as single clock.
>>>>>
>>>>> clk_ops callback implementations for these clocks uses
>>>>> tegra_pmc_readl and
>>>>> tegra_pmc_writel which supports PMC programming in both secure mode
>>>>> and
>>>>> non-secure mode.
>>>>>
>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>> ---
>>>>>   drivers/soc/tegra/pmc.c | 248
>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>   1 file changed, 248 insertions(+)
>>>>>
>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>> @@ -13,6 +13,9 @@
>>>>>     #include <linux/arm-smccc.h>
>>>>>   #include <linux/clk.h>
>>>>> +#include <linux/clk-provider.h>
>>>>> +#include <linux/clkdev.h>
>>>>> +#include <linux/clk/clk-conf.h>
>>>>>   #include <linux/clk/tegra.h>
>>>>>   #include <linux/debugfs.h>
>>>>>   #include <linux/delay.h>
>>>>> @@ -48,6 +51,7 @@
>>>>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>     #define PMC_CNTRL            0x0
>>>>>   #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>> polarity */
>>>>> @@ -100,6 +104,7 @@
>>>>>   #define PMC_WAKE2_STATUS        0x168
>>>>>   #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>   +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>   #define PMC_SENSOR_CTRL            0x1b0
>>>>>   #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>   #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>> @@ -155,6 +160,64 @@
>>>>>   #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>   #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>   +struct pmc_clk {
>>>>> +    struct clk_hw    hw;
>>>>> +    unsigned long    offs;
>>>>> +    u32        mux_mask;
>>>>> +    u32        mux_shift;
>>>>> +    u32        gate_shift;
>>>>> +};
>>>>> +
>>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>>> +
>>>>> +struct pmc_clk_init_data {
>>>>> +    char *name;
>>>>> +    const char *const *parents;
>>>>> +    int num_parents;
>>>>> +    int clk_id;
>>>>> +    u8 mux_shift;
>>>>> +    u8 gate_shift;
>>>>> +};
>>>>> +
>>>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>>>> +    "osc_div4", "extern1",
>>>>> +};
>>>>> +
>>>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>>>> +    "osc_div4", "extern2",
>>>>> +};
>>>>> +
>>>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>>>> +    "osc_div4", "extern3",
>>>>> +};
>>>>> +
>>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>> +    {
>>>>> +        .name = "clk_out_1",
>>>>> +        .parents = clk_out1_parents,
>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_1,
>>>>> +        .mux_shift = 6,
>>>>> +        .gate_shift = 2,
>>>> I'd replace these with a single .shift, given that mux_shift =
>>>> gate_shift + 4 for all clocks.
>>>>
>>>>> +    },
>>>>> +    {
>>>>> +        .name = "clk_out_2",
>>>>> +        .parents = clk_out2_parents,
>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_2,
>>>>> +        .mux_shift = 14,
>>>>> +        .gate_shift = 10,
>>>>> +    },
>>>>> +    {
>>>>> +        .name = "clk_out_3",
>>>>> +        .parents = clk_out3_parents,
>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_3,
>>>>> +        .mux_shift = 22,
>>>>> +        .gate_shift = 18,
>>>>> +    },
>>>>> +};
>>>>> +
>>>>>   struct tegra_powergate {
>>>>>       struct generic_pm_domain genpd;
>>>>>       struct tegra_pmc *pmc;
>>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>>        */
>>>>>       const struct tegra_wake_event *wake_events;
>>>>>       unsigned int num_wake_events;
>>>>> +
>>>>> +    const struct pmc_clk_init_data *pmc_clks_data;
>>>>> +    unsigned int num_pmc_clks;
>>>>>   };
>>>>>     static const char * const tegra186_reset_sources[] = {
>>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>> notifier_block *nb,
>>>>>       return NOTIFY_OK;
>>>>>   }
>>>>>   +static void pmc_clk_fence_udelay(u32 offset)
>>>>> +{
>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>> +    /* pmc clk propagation delay 2 us */
>>>>> +    udelay(2);
>>>>> +}
>>>>> +
>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +    u32 val;
>>>>> +
>>>>> +    val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>>> +    val &= clk->mux_mask;
>>>>> +
>>>>> +    return val;
>>>>> +}
>>>>> +
>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +    u32 val;
>>>>> +
>>>>> +    val = tegra_pmc_readl(pmc, clk->offs);
>>>>> +    val &= ~(clk->mux_mask << clk->mux_shift);
>>>>> +    val |= index << clk->mux_shift;
>>>>> +    tegra_pmc_writel(pmc, val, clk->offs);
>>>>> +    pmc_clk_fence_udelay(clk->offs);
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +
>>>>> +    return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift)
>>>>> ? 1 : 0;
>>>>> +}
>>>>> +
>>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int
>>>>> state)
>>>>> +{
>>>>> +    u32 val;
>>>>> +
>>>>> +    val = tegra_pmc_readl(pmc, offs);
>>>>> +    val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>>> +    tegra_pmc_writel(pmc, val, offs);
>>>>> +    pmc_clk_fence_udelay(offs);
>>>>> +}
>>>>> +
>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +
>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +
>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>>> +}
>>>>> +
>>>>> +static const struct clk_ops pmc_clk_ops = {
>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>> +    .enable = pmc_clk_enable,
>>>>> +    .disable = pmc_clk_disable,
>>>>> +};
>>>>> +
>>>>> +static struct clk *
>>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>>> +               unsigned long offset)
>>>>> +{
>>>>> +    struct clk_init_data init;
>>>>> +    struct pmc_clk *pmc_clk;
>>>>> +
>>>>> +    pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>>> +    if (!pmc_clk)
>>>>> +        return ERR_PTR(-ENOMEM);
>>>>> +
>>>>> +    init.name = data->name;
>>>>> +    init.ops = &pmc_clk_ops;
>>>>> +    init.parent_names = data->parents;
>>>>> +    init.num_parents = data->num_parents;
>>>>> +    init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>>> +             CLK_SET_PARENT_GATE;
>>>>> +
>>>>> +    pmc_clk->hw.init = &init;
>>>>> +    pmc_clk->offs = offset;
>>>>> +    pmc_clk->mux_mask = 3;
>>>> If mux_mask is a constant value, perhaps will be better to replace the
>>>> variable with a literal?
>>>>
>>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>> Maybe even:
>>>
>>> #define PMC_CLK_OUT_MUX_MASK(c)    GENMASK(c->shift + 1, c->shift)
>>>
>>>>> +    pmc_clk->mux_shift = data->mux_shift;
>>>>> +    pmc_clk->gate_shift = data->gate_shift;
>>>>> +
>>>>> +    return clk_register(NULL, &pmc_clk->hw);
>>>>> +}
>>>>> +
>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>> +                     struct device_node *np)
>>>>> +{
>>>>> +    struct clk *clk;
>>>>> +    struct clk_onecell_data *clk_data;
>>>>> +    unsigned int num_clks;
>>>>> +    int i, err = -ENOMEM;
>>>>> +
>>>>> +    num_clks = pmc->soc->num_pmc_clks;
>>>>> +
>>>>> +    if (!num_clks)
>>>>> +        return;
>>>>> +
>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>> +    if (!clk_data)
>>>>> +        goto err_clk;
>>>> What about devm_kmalloc, devm_kcalloc?
>>>>
>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>> sizeof(*clk_data->clks),
>>>>> +                 GFP_KERNEL);
>>>>> +    if (!clk_data->clks)
>>>>> +        goto free_clkdata;
>>>>> +
>>>>> +    clk_data->clk_num = TEGRA_PMC_CLK_MAX;
>>>>> +
>>>>> +    for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
>>>>> +        clk_data->clks[i] = ERR_PTR(-ENOENT);
>>>>> +
>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>> +        const struct pmc_clk_init_data *data;
>>>>> +
>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>> +
>>>>> +        clk = tegra_pmc_clk_out_register(data,
>>>>> PMC_CLK_OUT_CNTRL);> +        if (IS_ERR(clk)) {
>>>>> +            dev_err(pmc->dev,
>>>>> +                "unable to register %s\n", data->name);
>>>>> +            err = PTR_ERR(clk);
>>>> Error codes in a message could be useful.
>>
>> Added error code at end of clock register along with WARN message to
>> have it common to show warning with error code for all errors
>> including kmalloc and kcalloc.
>>
> Sure, With devm_kmalloc and devm_kcalloc, will move error code along
> with message and do return right at point of errors.

There is no need to warn about memory allocations because there will be
warning anyway, unless __GFP_NOWARN is used.

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-18 16:52           ` Dmitry Osipenko
@ 2019-12-18 17:00             ` Sowjanya Komatineni
  0 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-18 17:00 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/18/19 8:52 AM, Dmitry Osipenko wrote:
> 18.12.2019 18:50, Sowjanya Komatineni пишет:
>> On 12/18/19 7:46 AM, Sowjanya Komatineni wrote:
>>> On 12/18/19 12:35 AM, Dmitry Osipenko wrote:
>>>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
>>>>>> these PMC clocks are registered by Tegra clock driver with each
>>>>>> clock as
>>>>>> separate mux and gate clocks using clk_register_mux and
>>>>>> clk_register_gate
>>>>>> by passing PMC base address and register offsets and PMC
>>>>>> programming for
>>>>>> these clocks happens through direct PMC access by the clock driver.
>>>>>>
>>>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>>>> non-secure world does not go through and these clocks will not be
>>>>>> functional.
>>>>>>
>>>>>> This patch adds these PMC clocks registration to pmc driver with
>>>>>> PMC as
>>>>>> a clock provider and registers each clock as single clock.
>>>>>>
>>>>>> clk_ops callback implementations for these clocks uses
>>>>>> tegra_pmc_readl and
>>>>>> tegra_pmc_writel which supports PMC programming in both secure mode
>>>>>> and
>>>>>> non-secure mode.
>>>>>>
>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>> ---
>>>>>>    drivers/soc/tegra/pmc.c | 248
>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>    1 file changed, 248 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>> @@ -13,6 +13,9 @@
>>>>>>      #include <linux/arm-smccc.h>
>>>>>>    #include <linux/clk.h>
>>>>>> +#include <linux/clk-provider.h>
>>>>>> +#include <linux/clkdev.h>
>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>    #include <linux/clk/tegra.h>
>>>>>>    #include <linux/debugfs.h>
>>>>>>    #include <linux/delay.h>
>>>>>> @@ -48,6 +51,7 @@
>>>>>>    #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>    #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>    #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>      #define PMC_CNTRL            0x0
>>>>>>    #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>> polarity */
>>>>>> @@ -100,6 +104,7 @@
>>>>>>    #define PMC_WAKE2_STATUS        0x168
>>>>>>    #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>    +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>    #define PMC_SENSOR_CTRL            0x1b0
>>>>>>    #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>>    #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>>> @@ -155,6 +160,64 @@
>>>>>>    #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>    #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>    +struct pmc_clk {
>>>>>> +    struct clk_hw    hw;
>>>>>> +    unsigned long    offs;
>>>>>> +    u32        mux_mask;
>>>>>> +    u32        mux_shift;
>>>>>> +    u32        gate_shift;
>>>>>> +};
>>>>>> +
>>>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>>>> +
>>>>>> +struct pmc_clk_init_data {
>>>>>> +    char *name;
>>>>>> +    const char *const *parents;
>>>>>> +    int num_parents;
>>>>>> +    int clk_id;
>>>>>> +    u8 mux_shift;
>>>>>> +    u8 gate_shift;
>>>>>> +};
>>>>>> +
>>>>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>>>>> +    "osc_div4", "extern1",
>>>>>> +};
>>>>>> +
>>>>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>>>>> +    "osc_div4", "extern2",
>>>>>> +};
>>>>>> +
>>>>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>>>>> +    "osc_div4", "extern3",
>>>>>> +};
>>>>>> +
>>>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>> +    {
>>>>>> +        .name = "clk_out_1",
>>>>>> +        .parents = clk_out1_parents,
>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_1,
>>>>>> +        .mux_shift = 6,
>>>>>> +        .gate_shift = 2,
>>>>> I'd replace these with a single .shift, given that mux_shift =
>>>>> gate_shift + 4 for all clocks.
>>>>>
>>>>>> +    },
>>>>>> +    {
>>>>>> +        .name = "clk_out_2",
>>>>>> +        .parents = clk_out2_parents,
>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_2,
>>>>>> +        .mux_shift = 14,
>>>>>> +        .gate_shift = 10,
>>>>>> +    },
>>>>>> +    {
>>>>>> +        .name = "clk_out_3",
>>>>>> +        .parents = clk_out3_parents,
>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_3,
>>>>>> +        .mux_shift = 22,
>>>>>> +        .gate_shift = 18,
>>>>>> +    },
>>>>>> +};
>>>>>> +
>>>>>>    struct tegra_powergate {
>>>>>>        struct generic_pm_domain genpd;
>>>>>>        struct tegra_pmc *pmc;
>>>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>>>         */
>>>>>>        const struct tegra_wake_event *wake_events;
>>>>>>        unsigned int num_wake_events;
>>>>>> +
>>>>>> +    const struct pmc_clk_init_data *pmc_clks_data;
>>>>>> +    unsigned int num_pmc_clks;
>>>>>>    };
>>>>>>      static const char * const tegra186_reset_sources[] = {
>>>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>>> notifier_block *nb,
>>>>>>        return NOTIFY_OK;
>>>>>>    }
>>>>>>    +static void pmc_clk_fence_udelay(u32 offset)
>>>>>> +{
>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>> +    udelay(2);
>>>>>> +}
>>>>>> +
>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +    u32 val;
>>>>>> +
>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>>>> +    val &= clk->mux_mask;
>>>>>> +
>>>>>> +    return val;
>>>>>> +}
>>>>>> +
>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +    u32 val;
>>>>>> +
>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs);
>>>>>> +    val &= ~(clk->mux_mask << clk->mux_shift);
>>>>>> +    val |= index << clk->mux_shift;
>>>>>> +    tegra_pmc_writel(pmc, val, clk->offs);
>>>>>> +    pmc_clk_fence_udelay(clk->offs);
>>>>>> +
>>>>>> +    return 0;
>>>>>> +}
>>>>>> +
>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +
>>>>>> +    return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift)
>>>>>> ? 1 : 0;
>>>>>> +}
>>>>>> +
>>>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int
>>>>>> state)
>>>>>> +{
>>>>>> +    u32 val;
>>>>>> +
>>>>>> +    val = tegra_pmc_readl(pmc, offs);
>>>>>> +    val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>>>> +    tegra_pmc_writel(pmc, val, offs);
>>>>>> +    pmc_clk_fence_udelay(offs);
>>>>>> +}
>>>>>> +
>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +
>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>>>> +
>>>>>> +    return 0;
>>>>>> +}
>>>>>> +
>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +
>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>>>> +}
>>>>>> +
>>>>>> +static const struct clk_ops pmc_clk_ops = {
>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>> +    .enable = pmc_clk_enable,
>>>>>> +    .disable = pmc_clk_disable,
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk *
>>>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>>>> +               unsigned long offset)
>>>>>> +{
>>>>>> +    struct clk_init_data init;
>>>>>> +    struct pmc_clk *pmc_clk;
>>>>>> +
>>>>>> +    pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>>>> +    if (!pmc_clk)
>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>> +
>>>>>> +    init.name = data->name;
>>>>>> +    init.ops = &pmc_clk_ops;
>>>>>> +    init.parent_names = data->parents;
>>>>>> +    init.num_parents = data->num_parents;
>>>>>> +    init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>>>> +             CLK_SET_PARENT_GATE;
>>>>>> +
>>>>>> +    pmc_clk->hw.init = &init;
>>>>>> +    pmc_clk->offs = offset;
>>>>>> +    pmc_clk->mux_mask = 3;
>>>>> If mux_mask is a constant value, perhaps will be better to replace the
>>>>> variable with a literal?
>>>>>
>>>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>>> Maybe even:
>>>>
>>>> #define PMC_CLK_OUT_MUX_MASK(c)    GENMASK(c->shift + 1, c->shift)
>>>>
>>>>>> +    pmc_clk->mux_shift = data->mux_shift;
>>>>>> +    pmc_clk->gate_shift = data->gate_shift;
>>>>>> +
>>>>>> +    return clk_register(NULL, &pmc_clk->hw);
>>>>>> +}
>>>>>> +
>>>>>> +static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
>>>>>> +                     struct device_node *np)
>>>>>> +{
>>>>>> +    struct clk *clk;
>>>>>> +    struct clk_onecell_data *clk_data;
>>>>>> +    unsigned int num_clks;
>>>>>> +    int i, err = -ENOMEM;
>>>>>> +
>>>>>> +    num_clks = pmc->soc->num_pmc_clks;
>>>>>> +
>>>>>> +    if (!num_clks)
>>>>>> +        return;
>>>>>> +
>>>>>> +    clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
>>>>>> +    if (!clk_data)
>>>>>> +        goto err_clk;
>>>>> What about devm_kmalloc, devm_kcalloc?
>>>>>
>>>>>> +    clk_data->clks = kcalloc(TEGRA_PMC_CLK_MAX,
>>>>>> sizeof(*clk_data->clks),
>>>>>> +                 GFP_KERNEL);
>>>>>> +    if (!clk_data->clks)
>>>>>> +        goto free_clkdata;
>>>>>> +
>>>>>> +    clk_data->clk_num = TEGRA_PMC_CLK_MAX;
>>>>>> +
>>>>>> +    for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
>>>>>> +        clk_data->clks[i] = ERR_PTR(-ENOENT);
>>>>>> +
>>>>>> +    for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
>>>>>> +        const struct pmc_clk_init_data *data;
>>>>>> +
>>>>>> +        data = pmc->soc->pmc_clks_data + i;
>>>>>> +
>>>>>> +        clk = tegra_pmc_clk_out_register(data,
>>>>>> PMC_CLK_OUT_CNTRL);> +        if (IS_ERR(clk)) {
>>>>>> +            dev_err(pmc->dev,
>>>>>> +                "unable to register %s\n", data->name);
>>>>>> +            err = PTR_ERR(clk);
>>>>> Error codes in a message could be useful.
>>> Added error code at end of clock register along with WARN message to
>>> have it common to show warning with error code for all errors
>>> including kmalloc and kcalloc.
>>>
>> Sure, With devm_kmalloc and devm_kcalloc, will move error code along
>> with message and do return right at point of errors.
> There is no need to warn about memory allocations because there will be
> warning anyway, unless __GFP_NOWARN is used.

Earlier I had WARN message at each of errors during clock registers 
except during malloc/calloc.

When you suggested to add additional WARN message at the end of clock 
register in earlier feedback, thought you were suggesting to warn about 
kmalloc/kcalloc failures.

Probably I misunderstood your suggestion.

Anyways now with moving to devm malloc/calloc, will use dev_warn to show 
warning along with error code right at the point of error.


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 01/19] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks
  2019-12-17 20:03 ` [PATCH v4 01/19] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks Sowjanya Komatineni
@ 2019-12-18 21:19   ` Rob Herring
  0 siblings, 0 replies; 54+ messages in thread
From: Rob Herring @ 2019-12-18 21:19 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad,
	spujar, josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
	linux-clk, linux-tegra, linux-kernel

On Tue, 17 Dec 2019 12:03:48 -0800, Sowjanya Komatineni wrote:
> Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has
> OSC_DIV2 and OSC_DIV4 clocks from OSC pads.
> 
> This patch changes CLK_M_DIV2 and CLK_M_DIV4 clock ids to OSC_DIV2
> and OSC_DIV4 clock ids for Tegra30 through Tegra210.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  include/dt-bindings/clock/tegra114-car.h        | 4 ++--
>  include/dt-bindings/clock/tegra124-car-common.h | 4 ++--
>  include/dt-bindings/clock/tegra210-car.h        | 4 ++--
>  include/dt-bindings/clock/tegra30-car.h         | 4 ++--
>  4 files changed, 8 insertions(+), 8 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 04/19] dt-bindings: tegra: Convert Tegra PMC bindings to YAML
  2019-12-17 20:03 ` [PATCH v4 04/19] dt-bindings: tegra: Convert Tegra PMC bindings to YAML Sowjanya Komatineni
@ 2019-12-18 21:29   ` Rob Herring
  2019-12-18 22:31     ` Sowjanya Komatineni
  0 siblings, 1 reply; 54+ messages in thread
From: Rob Herring @ 2019-12-18 21:29 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: thierry.reding, jonathanh, digetx, mperttunen, gregkh, sboyd,
	mark.rutland, pdeschrijver, pgaikwad, spujar, josephl,
	daniel.lezcano, mmaddireddy, markz, devicetree, linux-clk,
	linux-tegra, linux-kernel

On Tue, Dec 17, 2019 at 12:03:51PM -0800, Sowjanya Komatineni wrote:
> This patch adds YAML schema for Tegra PMC bindings.

$subject says convert. Where's removing the old file?

> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml     | 291 +++++++++++++++++++++
>  1 file changed, 291 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> new file mode 100644
> index 000000000000..ab614f1be177
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> @@ -0,0 +1,291 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tegra Power Management Controller (PMC)
> +
> +maintainers:
> +  - Thierry Reding <thierry.reding@gmail.com>
> +  - Jonathan Hunter <jonathanh@nvidia.com>
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: nvidia,tegra20-pmc
> +          - const: nvidia,tegra20-pmc
> +          - const: nvidia,tegra30-pmc
> +          - const: nvidia,tegra114-pmc
> +          - const: nvidia,tegra124-pmc
> +          - const: nvidia,tegra210-pmc

So compatible is supposed to be all 6 strings? You want an 'enum' here.

> +
> +  reg:
> +    maxItems: 1
> +
> +  clock-names:
> +    items:
> +      - const: pclk, clk32k_in
> +    description:
> +      pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
> +      input to Tegra.
> +
> +  clocks:
> +    maxItems: 2
> +
> +  '#clock-cells':
> +    const: 1
> +    description:
> +      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
> +      Consumer of PMC clock should specify the desired clock by having
> +      the clock ID in its "clocks" phandle cell with pmc clock provider.
> +      See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
> +      clock IDs.
> +
> +  nvidia,invert-interrupt:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: Inverts the PMU interrupt signal.
> +      The PMU is an external Power Management Unit, whose interrupt output
> +      signal is fed into the PMC. This signal is optionally inverted, and
> +      then fed into the ARM GIC. The PMC is not involved in the detection
> +      or handling of this interrupt signal, merely its inversion.
> +
> +  nvidia,core-power-req-active-high:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: Core power request active-high.
> +
> +  nvidia,sys-clock-req-active-high:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: System clock request active-high.
> +
> +  nvidia,combined-power-req:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: combined power request for CPU and Core.
> +
> +  nvidia,cpu-pwr-good-en:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description:
> +      CPU power good signal from external PMIC to PMC is enabled.
> +
> +  nvidia,suspend-mode:
> +    allOf:
> +      - $ref: /schemas/types.yaml#/definitions/uint32
> +      - enum: [0, 1, 2]
> +    description:
> +      The suspend mode that the platform should use.
> +      Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
> +      Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
> +      Mode 2 is for LP2, CPU voltage off
> +
> +  nvidia,cpu-pwr-good-time:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: CPU power good time in uSec.
> +
> +  nvidia,cpu-pwr-off-time:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: CPU power off time in uSec.
> +
> +  nvidia,core-pwr-good-time:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description:
> +      <Oscillator-stable-time Power-stable-time>
> +      Core power good time in uSec.
> +
> +  nvidia,core-pwr-off-time:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: Core power off time in uSec.
> +
> +  nvidia,lp0-vec:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description:
> +      <start length> Starting address and length of LP0 vector.
> +      The LP0 vector contains the warm boot code that is executed
> +      by AVP when resuming from the LP0 state.
> +      The AVP (Audio-Video Processor) is an ARM7 processor and
> +      always being the first boot processor when chip is power on
> +      or resume from deep sleep mode. When the system is resumed
> +      from the deep sleep mode, the warm boot code will restore
> +      some PLLs, clocks and then brings up CPU0 for resuming the
> +      system.
> +
> +  i2c-thermtrip:
> +    type: object
> +    description:
> +      On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
> +      hardware-triggered thermal reset will be enabled.
> +
> +    properties:
> +      nvidia,i2c-controller-id:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        description:
> +          ID of I2C controller to send poweroff command to PMU.
> +          Valid values are described in section 9.2.148
> +          "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
> +          Manual.
> +
> +      nvidia,bus-addr:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        description: Bus address of the PMU on the I2C bus.
> +
> +      nvidia,reg-addr:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        description: PMU I2C register address to issue poweroff command.
> +
> +      nvidia,reg-data:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        description: Poweroff command to write to PMU.
> +
> +      nvidia,pinmux-id:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        description:
> +          Pinmux used by the hardware when issuing Poweroff command.
> +          Defaults to 0. Valid values are described in section 12.5.2
> +          "Pinmux Support" of the Tegra4 Technical Reference Manual.
> +
> +    required:
> +      - nvidia,i2c-controller-id
> +      - nvidia,bus-addr
> +      - nvidia,reg-addr
> +      - nvidia,reg-data

       additionalProperties: false

> +
> +  powergates:
> +    type: object
> +    description:
> +      This node contains a hierarchy of power domain nodes, which should
> +      match the powergates on the Tegra SoC. Each powergate node
> +      represents a power-domain on the Tegra SoC that can be power-gated
> +      by the Tegra PMC.
> +      Hardware blocks belonging to a power domain should contain
> +      "power-domains" property that is a phandle pointing to corresponding
> +      powergate node.
> +      Please refer to Tegra TRM for mode details on the powergate nodes to
> +      use for each power-gate block inside Tegra.
> +
> +    patternProperties:
> +      "^[a-z0-9]+$":
> +        if:
> +          type: object

It's better if you have node name patterns to match on than have to do 
this if/then.

> +        then:
> +          patternProperties:
> +            clocks:
> +              description:
> +                Must contain an entry for each clock required by the PMC
> +                for controlling a power-gate.
> +                See ../clocks/clock-bindings.txt document for more details.
> +
> +            resets:
> +              description:
> +                Must contain an entry for each reset required by the PMC
> +                for controlling a power-gate.
> +                See ../reset/reset.txt for more details.
> +
> +            '#power-domain-cells':
> +              description: Must be 0.
> +
> +    required:
> +      - clocks
> +      - resets
> +      - '#power-domain-cells'

These need property definitions.

> +
> +patternProperties:
> +  "^.*@[0-9a-f]+$":
> +    type: object
> +
> +    properties:
> +      pins:
> +        $ref: /schemas/types.yaml#/definitions/string
> +        description: Must contain name of the pad(s) to be configured.
> +
> +      low-power-enable:
> +        $ref: /schemas/types.yaml#/definitions/flag
> +        description: Configure the pad into power down mode.
> +
> +      low-power-disable:
> +        $ref: /schemas/types.yaml#/definitions/flag
> +        description: Configure the pad into active mode.
> +
> +      power-source:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        description:
> +          Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
> +          TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
> +          The values are defined in
> +          include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
> +          Power state can be configured on all Tegra124 and Tegra132
> +          pads. None of the Tegra124 or Tegra132 pads support signaling
> +          voltage switching.
> +          All of the listed Tegra210 pads except pex-cntrl support power
> +          state configuration. Signaling voltage switching is supported
> +          on below Tegra210 pads.
> +          audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
> +          sdmmc3, spi, spi-hv, and uart.
> +
> +    required:
> +      - pins
> +
> +required:
> +  - compatible
> +  - reg
> +  - clock-names
> +  - clocks
> +  - '#clock-cells'
> +
> +if:
> +  properties:
> +    nvidia,suspend-mode:
> +      contains:
> +        const: 2
> +
> +then:
> +  required:
> +    - nvidia,cpu-pwr-good-time
> +    - nvidia,cpu-pwr-off-time
> +    - nvidia,core-pwr-good-time
> +    - nvidia,core-pwr-off-time
> +
> +examples:
> +  - |
> +    #include <dt-bindings/soc/tegra-pmc.h>
> +
> +    pmc: pmc@7000e400 {
> +              compatible = "nvidia,tegra210-pmc";
> +              reg = <0x0 0x7000e400 0x0 0x400>;
> +              clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
> +              clock-names = "pclk", "clk32k_in";
> +              #clock-cells = <1>;
> +
> +              powergates {
> +                    pd_audio: aud {
> +                            clocks = <&tegra_car TEGRA210_CLK_APE>,
> +                                     <&tegra_car TEGRA210_CLK_APB2APE>;
> +                            resets = <&tegra_car 198>;
> +                            #power-domain-cells = <0>;
> +                    };
> +
> +                    pd_xusbss: xusba {
> +                            clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
> +                            resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
> +                            #power-domain-cells = <0>;
> +                    };
> +              };
> +
> +              sdmmc1_3v3: sdmmc1-3v3 {
> +                      pins = "sdmmc1";
> +                      power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
> +              };
> +
> +              sdmmc1_1v8: sdmmc1-1v8 {
> +                      pins = "sdmmc1";
> +                      power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
> +              };
> +
> +              nvidia,invert-interrupt;
> +              nvidia,suspend-mode = <0>;
> +              nvidia,cpu-pwr-good-time = <0>;
> +              nvidia,cpu-pwr-off-time = <0>;
> +              nvidia,core-pwr-good-time = <4587 3876>;
> +              nvidia,core-pwr-off-time = <39065>;
> +              nvidia,core-power-req-active-high;
> +              nvidia,sys-clock-req-active-high;
> +    };
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 07/19] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock
  2019-12-17 20:03 ` [PATCH v4 07/19] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock Sowjanya Komatineni
@ 2019-12-18 21:30   ` Rob Herring
  0 siblings, 0 replies; 54+ messages in thread
From: Rob Herring @ 2019-12-18 21:30 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad,
	spujar, josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
	linux-clk, linux-tegra, linux-kernel

On Tue, 17 Dec 2019 12:03:54 -0800, Sowjanya Komatineni wrote:
> Tegra PMC has blink functionality that allows 32KHz clock out to
> blink pin of the Tegra.
> 
> This patch adds id for this blink clock to use for enabling or
> disabling blink output through device tree.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  include/dt-bindings/soc/tegra-pmc.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 10/19] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
  2019-12-17 20:03 ` [PATCH v4 10/19] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings Sowjanya Komatineni
@ 2019-12-18 21:32   ` Rob Herring
  0 siblings, 0 replies; 54+ messages in thread
From: Rob Herring @ 2019-12-18 21:32 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad,
	spujar, josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
	linux-clk, linux-tegra, linux-kernel

On Tue, 17 Dec 2019 12:03:57 -0800, Sowjanya Komatineni wrote:
> clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block and
> these clocks are moved to Tegra PMC driver with pmc as clock provider
> and uses clock ids from dt-bindings/soc/tegra-pmc.h
> 
> So, this patch removes ids for these clocks from Tegra clock dt-bindings.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  include/dt-bindings/clock/tegra114-car.h        | 14 +++++++-------
>  include/dt-bindings/clock/tegra124-car-common.h | 14 +++++++-------
>  include/dt-bindings/clock/tegra20-car.h         |  2 +-
>  include/dt-bindings/clock/tegra210-car.h        | 14 +++++++-------
>  include/dt-bindings/clock/tegra30-car.h         | 14 +++++++-------
>  5 files changed, 29 insertions(+), 29 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 19/19] ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car to pmc
  2019-12-17 20:04 ` [PATCH v4 19/19] ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car " Sowjanya Komatineni
@ 2019-12-18 21:32   ` Rob Herring
  0 siblings, 0 replies; 54+ messages in thread
From: Rob Herring @ 2019-12-18 21:32 UTC (permalink / raw)
  To: Sowjanya Komatineni
  Cc: skomatineni, thierry.reding, jonathanh, digetx, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad,
	spujar, josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
	linux-clk, linux-tegra, linux-kernel

On Tue, 17 Dec 2019 12:04:06 -0800, Sowjanya Komatineni wrote:
> Tegra clk_out_1, clk_out_2, and clk_out_3 are part of PMC block and
> these clocks are moved from clock drvier to pmc driver with pmc as
> a provider for these clocks.
> 
> Update bindings document to use pmc as clock provider for clk_out_2 and
> change id to pmc clock id.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  Documentation/devicetree/bindings/sound/nau8825.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 15/19] ARM: dts: tegra: Add clock-cells property to pmc
  2019-12-17 20:04 ` [PATCH v4 15/19] ARM: dts: tegra: Add clock-cells property to pmc Sowjanya Komatineni
@ 2019-12-18 21:36   ` Dmitry Osipenko
  0 siblings, 0 replies; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18 21:36 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

17.12.2019 23:04, Sowjanya Komatineni пишет:
> Tegra PMC has clk_out_1, clk_out_2, clk_out_3, and blink clock.
> 
> These clocks are moved from clock driver to pmc driver with pmc
> as the clock provider for these clocks.
> 
> This patch adds #clock-cells property with 1 clock specifier to
> the Tegra PMC node in device tree.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  arch/arm/boot/dts/tegra114.dtsi | 4 +++-
>  arch/arm/boot/dts/tegra124.dtsi | 4 +++-
>  arch/arm/boot/dts/tegra20.dtsi  | 4 +++-
>  arch/arm/boot/dts/tegra30.dtsi  | 4 +++-
>  4 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
> index 0d7a6327e404..b8f12f24f314 100644
> --- a/arch/arm/boot/dts/tegra114.dtsi
> +++ b/arch/arm/boot/dts/tegra114.dtsi
> @@ -4,6 +4,7 @@
>  #include <dt-bindings/memory/tegra114-mc.h>
>  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/tegra-pmc.h>
>  
>  / {
>  	compatible = "nvidia,tegra114";
> @@ -514,11 +515,12 @@
>  		status = "disabled";
>  	};
>  
> -	pmc@7000e400 {
> +	pmc: pmc@7000e400 {
>  		compatible = "nvidia,tegra114-pmc";
>  		reg = <0x7000e400 0x400>;
>  		clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
>  		clock-names = "pclk", "clk32k_in";
> +		#clock-cells = <1>;
>  	};
>  
>  	fuse@7000f800 {
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 413bfb981de8..d0802c4ae3bf 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -6,6 +6,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/reset/tegra124-car.h>
>  #include <dt-bindings/thermal/tegra124-soctherm.h>
> +#include <dt-bindings/soc/tegra-pmc.h>
>  
>  / {
>  	compatible = "nvidia,tegra124";
> @@ -595,11 +596,12 @@
>  		clocks = <&tegra_car TEGRA124_CLK_RTC>;
>  	};
>  
> -	pmc@7000e400 {
> +	pmc: pmc@7000e400 {
>  		compatible = "nvidia,tegra124-pmc";
>  		reg = <0x0 0x7000e400 0x0 0x400>;
>  		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
>  		clock-names = "pclk", "clk32k_in";
> +		#clock-cells = <1>;
>  	};
>  
>  	fuse@7000f800 {
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index 9c58e7fcf5c0..85a64747bec6 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -4,6 +4,7 @@
>  #include <dt-bindings/memory/tegra20-mc.h>
>  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/tegra-pmc.h>
>  
>  / {
>  	compatible = "nvidia,tegra20";
> @@ -608,11 +609,12 @@
>  		status = "disabled";
>  	};
>  
> -	pmc@7000e400 {
> +	pmc: pmc@7000e400 {
>  		compatible = "nvidia,tegra20-pmc";
>  		reg = <0x7000e400 0x400>;
>  		clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
>  		clock-names = "pclk", "clk32k_in";
> +		#clock-cells = <1>;
>  	};
>  
>  	mc: memory-controller@7000f000 {
> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> index 55ae050042ce..4d5e9d0001d3 100644
> --- a/arch/arm/boot/dts/tegra30.dtsi
> +++ b/arch/arm/boot/dts/tegra30.dtsi
> @@ -4,6 +4,7 @@
>  #include <dt-bindings/memory/tegra30-mc.h>
>  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/tegra-pmc.h>
>  
>  / {
>  	compatible = "nvidia,tegra30";
> @@ -714,11 +715,12 @@
>  		status = "disabled";
>  	};
>  
> -	pmc@7000e400 {
> +	pmc: pmc@7000e400 {

I think will be a bit better to name the phandle as "tegra_pmc", it has
the same vibe as the "tegra_car".

>  		compatible = "nvidia,tegra30-pmc";
>  		reg = <0x7000e400 0x400>;
>  		clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
>  		clock-names = "pclk", "clk32k_in";
> +		#clock-cells = <1>;
>  	};
>  
>  	mc: memory-controller@7000f000 {
> 


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-18  8:35     ` Dmitry Osipenko
  2019-12-18 15:46       ` Sowjanya Komatineni
@ 2019-12-18 21:44       ` Dmitry Osipenko
  2019-12-19  0:41         ` Sowjanya Komatineni
  1 sibling, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-18 21:44 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

18.12.2019 11:35, Dmitry Osipenko пишет:
> 18.12.2019 11:30, Dmitry Osipenko пишет:
>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
>>> these PMC clocks are registered by Tegra clock driver with each clock as
>>> separate mux and gate clocks using clk_register_mux and clk_register_gate
>>> by passing PMC base address and register offsets and PMC programming for
>>> these clocks happens through direct PMC access by the clock driver.
>>>
>>> With this, when PMC is in secure mode any direct PMC access from the
>>> non-secure world does not go through and these clocks will not be
>>> functional.
>>>
>>> This patch adds these PMC clocks registration to pmc driver with PMC as
>>> a clock provider and registers each clock as single clock.
>>>
>>> clk_ops callback implementations for these clocks uses tegra_pmc_readl and
>>> tegra_pmc_writel which supports PMC programming in both secure mode and
>>> non-secure mode.
>>>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>>  drivers/soc/tegra/pmc.c | 248 ++++++++++++++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 248 insertions(+)
>>>
>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>> index ea0e11a09c12..6d65194a6e71 100644
>>> --- a/drivers/soc/tegra/pmc.c
>>> +++ b/drivers/soc/tegra/pmc.c
>>> @@ -13,6 +13,9 @@
>>>  
>>>  #include <linux/arm-smccc.h>
>>>  #include <linux/clk.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/clkdev.h>
>>> +#include <linux/clk/clk-conf.h>
>>>  #include <linux/clk/tegra.h>
>>>  #include <linux/debugfs.h>
>>>  #include <linux/delay.h>
>>> @@ -48,6 +51,7 @@
>>>  #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>  #include <dt-bindings/gpio/tegra186-gpio.h>
>>>  #include <dt-bindings/gpio/tegra194-gpio.h>
>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>  
>>>  #define PMC_CNTRL			0x0
>>>  #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
>>> @@ -100,6 +104,7 @@
>>>  #define PMC_WAKE2_STATUS		0x168
>>>  #define PMC_SW_WAKE2_STATUS		0x16c
>>>  
>>> +#define PMC_CLK_OUT_CNTRL		0x1a8
>>>  #define PMC_SENSOR_CTRL			0x1b0
>>>  #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>>>  #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
>>> @@ -155,6 +160,64 @@
>>>  #define  TEGRA_SMC_PMC_READ	0xaa
>>>  #define  TEGRA_SMC_PMC_WRITE	0xbb
>>>  
>>> +struct pmc_clk {
>>> +	struct clk_hw	hw;
>>> +	unsigned long	offs;
>>> +	u32		mux_mask;
>>> +	u32		mux_shift;
>>> +	u32		gate_shift;
>>> +};
>>> +
>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>> +
>>> +struct pmc_clk_init_data {
>>> +	char *name;
>>> +	const char *const *parents;
>>> +	int num_parents;
>>> +	int clk_id;
>>> +	u8 mux_shift;
>>> +	u8 gate_shift;
>>> +};
>>> +
>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>> +	"osc_div4", "extern1",
>>> +};
>>> +
>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>> +	"osc_div4", "extern2",
>>> +};
>>> +
>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>> +	"osc_div4", "extern3",
>>> +};
>>> +
>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>> +	{
>>> +		.name = "clk_out_1",
>>> +		.parents = clk_out1_parents,
>>> +		.num_parents = ARRAY_SIZE(clk_out1_parents),
>>> +		.clk_id = TEGRA_PMC_CLK_OUT_1,
>>
>>> +		.mux_shift = 6,
>>> +		.gate_shift = 2,
>>
>> I'd replace these with a single .shift, given that mux_shift =
>> gate_shift + 4 for all clocks.
>>
>>> +	},
>>> +	{
>>> +		.name = "clk_out_2",
>>> +		.parents = clk_out2_parents,
>>> +		.num_parents = ARRAY_SIZE(clk_out2_parents),
>>> +		.clk_id = TEGRA_PMC_CLK_OUT_2,
>>> +		.mux_shift = 14,
>>> +		.gate_shift = 10,
>>> +	},
>>> +	{
>>> +		.name = "clk_out_3",
>>> +		.parents = clk_out3_parents,
>>> +		.num_parents = ARRAY_SIZE(clk_out3_parents),
>>> +		.clk_id = TEGRA_PMC_CLK_OUT_3,
>>> +		.mux_shift = 22,
>>> +		.gate_shift = 18,
>>> +	},
>>> +};
>>> +
>>>  struct tegra_powergate {
>>>  	struct generic_pm_domain genpd;
>>>  	struct tegra_pmc *pmc;
>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>  	 */
>>>  	const struct tegra_wake_event *wake_events;
>>>  	unsigned int num_wake_events;
>>> +
>>> +	const struct pmc_clk_init_data *pmc_clks_data;
>>> +	unsigned int num_pmc_clks;
>>>  };
>>>  
>>>  static const char * const tegra186_reset_sources[] = {
>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
>>>  	return NOTIFY_OK;
>>>  }
>>>  
>>> +static void pmc_clk_fence_udelay(u32 offset)
>>> +{
>>> +	tegra_pmc_readl(pmc, offset);
>>> +	/* pmc clk propagation delay 2 us */
>>> +	udelay(2);
>>> +}
>>> +
>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +	u32 val;
>>> +
>>> +	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>> +	val &= clk->mux_mask;
>>> +
>>> +	return val;
>>> +}
>>> +
>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +	u32 val;
>>> +
>>> +	val = tegra_pmc_readl(pmc, clk->offs);
>>> +	val &= ~(clk->mux_mask << clk->mux_shift);
>>> +	val |= index << clk->mux_shift;
>>> +	tegra_pmc_writel(pmc, val, clk->offs);
>>> +	pmc_clk_fence_udelay(clk->offs);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +
>>> +	return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift) ? 1 : 0;
>>> +}
>>> +
>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
>>> +{
>>> +	u32 val;
>>> +
>>> +	val = tegra_pmc_readl(pmc, offs);
>>> +	val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>> +	tegra_pmc_writel(pmc, val, offs);
>>> +	pmc_clk_fence_udelay(offs);
>>> +}
>>> +
>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +
>>> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>> +{
>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>> +
>>> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>> +}
>>> +
>>> +static const struct clk_ops pmc_clk_ops = {
>>> +	.get_parent = pmc_clk_mux_get_parent,
>>> +	.set_parent = pmc_clk_mux_set_parent,
>>> +	.determine_rate = __clk_mux_determine_rate,
>>> +	.is_enabled = pmc_clk_is_enabled,
>>> +	.enable = pmc_clk_enable,
>>> +	.disable = pmc_clk_disable,
>>> +};
>>> +
>>> +static struct clk *
>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>> +			   unsigned long offset)
>>> +{
>>> +	struct clk_init_data init;
>>> +	struct pmc_clk *pmc_clk;
>>> +
>>> +	pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>> +	if (!pmc_clk)
>>> +		return ERR_PTR(-ENOMEM);
>>> +
>>> +	init.name = data->name;
>>> +	init.ops = &pmc_clk_ops;
>>> +	init.parent_names = data->parents;
>>> +	init.num_parents = data->num_parents;
>>> +	init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>> +		     CLK_SET_PARENT_GATE;
>>> +
>>> +	pmc_clk->hw.init = &init;
>>> +	pmc_clk->offs = offset;
>>> +	pmc_clk->mux_mask = 3;
>>
>> If mux_mask is a constant value, perhaps will be better to replace the
>> variable with a literal?
>>
>> #define PMC_CLK_OUT_MUX_MASK	GENMASK(1, 0)
> 
> Maybe even:
> 
> #define PMC_CLK_OUT_MUX_MASK(c)	GENMASK(c->shift + 1, c->shift)

I want to point out that may be a separated gate/mux shifts is a fine
variant, you should try and see whether another variants produce more
concise result.

[snip]

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 04/19] dt-bindings: tegra: Convert Tegra PMC bindings to YAML
  2019-12-18 21:29   ` Rob Herring
@ 2019-12-18 22:31     ` Sowjanya Komatineni
  0 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-18 22:31 UTC (permalink / raw)
  To: Rob Herring
  Cc: thierry.reding, jonathanh, digetx, mperttunen, gregkh, sboyd,
	mark.rutland, pdeschrijver, pgaikwad, spujar, josephl,
	daniel.lezcano, mmaddireddy, markz, devicetree, linux-clk,
	linux-tegra, linux-kernel


On 12/18/19 1:29 PM, Rob Herring wrote:
> On Tue, Dec 17, 2019 at 12:03:51PM -0800, Sowjanya Komatineni wrote:
>> This patch adds YAML schema for Tegra PMC bindings.
> $subject says convert. Where's removing the old file?
>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>>   .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml     | 291 +++++++++++++++++++++
>>   1 file changed, 291 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
>> new file mode 100644
>> index 000000000000..ab614f1be177
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
>> @@ -0,0 +1,291 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Tegra Power Management Controller (PMC)
>> +
>> +maintainers:
>> +  - Thierry Reding <thierry.reding@gmail.com>
>> +  - Jonathan Hunter <jonathanh@nvidia.com>
>> +
>> +properties:
>> +  compatible:
>> +    oneOf:
>> +      - items:
>> +          - const: nvidia,tegra20-pmc
>> +          - const: nvidia,tegra20-pmc
>> +          - const: nvidia,tegra30-pmc
>> +          - const: nvidia,tegra114-pmc
>> +          - const: nvidia,tegra124-pmc
>> +          - const: nvidia,tegra210-pmc
> So compatible is supposed to be all 6 strings? You want an 'enum' here.
>
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  clock-names:
>> +    items:
>> +      - const: pclk, clk32k_in
>> +    description:
>> +      pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
>> +      input to Tegra.
>> +
>> +  clocks:
>> +    maxItems: 2
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +    description:
>> +      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
>> +      Consumer of PMC clock should specify the desired clock by having
>> +      the clock ID in its "clocks" phandle cell with pmc clock provider.
>> +      See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
>> +      clock IDs.
>> +
>> +  nvidia,invert-interrupt:
>> +    $ref: /schemas/types.yaml#/definitions/flag
>> +    description: Inverts the PMU interrupt signal.
>> +      The PMU is an external Power Management Unit, whose interrupt output
>> +      signal is fed into the PMC. This signal is optionally inverted, and
>> +      then fed into the ARM GIC. The PMC is not involved in the detection
>> +      or handling of this interrupt signal, merely its inversion.
>> +
>> +  nvidia,core-power-req-active-high:
>> +    $ref: /schemas/types.yaml#/definitions/flag
>> +    description: Core power request active-high.
>> +
>> +  nvidia,sys-clock-req-active-high:
>> +    $ref: /schemas/types.yaml#/definitions/flag
>> +    description: System clock request active-high.
>> +
>> +  nvidia,combined-power-req:
>> +    $ref: /schemas/types.yaml#/definitions/flag
>> +    description: combined power request for CPU and Core.
>> +
>> +  nvidia,cpu-pwr-good-en:
>> +    $ref: /schemas/types.yaml#/definitions/flag
>> +    description:
>> +      CPU power good signal from external PMIC to PMC is enabled.
>> +
>> +  nvidia,suspend-mode:
>> +    allOf:
>> +      - $ref: /schemas/types.yaml#/definitions/uint32
>> +      - enum: [0, 1, 2]
>> +    description:
>> +      The suspend mode that the platform should use.
>> +      Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
>> +      Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
>> +      Mode 2 is for LP2, CPU voltage off
>> +
>> +  nvidia,cpu-pwr-good-time:
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    description: CPU power good time in uSec.
>> +
>> +  nvidia,cpu-pwr-off-time:
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    description: CPU power off time in uSec.
>> +
>> +  nvidia,core-pwr-good-time:
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>> +    description:
>> +      <Oscillator-stable-time Power-stable-time>
>> +      Core power good time in uSec.
>> +
>> +  nvidia,core-pwr-off-time:
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    description: Core power off time in uSec.
>> +
>> +  nvidia,lp0-vec:
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>> +    description:
>> +      <start length> Starting address and length of LP0 vector.
>> +      The LP0 vector contains the warm boot code that is executed
>> +      by AVP when resuming from the LP0 state.
>> +      The AVP (Audio-Video Processor) is an ARM7 processor and
>> +      always being the first boot processor when chip is power on
>> +      or resume from deep sleep mode. When the system is resumed
>> +      from the deep sleep mode, the warm boot code will restore
>> +      some PLLs, clocks and then brings up CPU0 for resuming the
>> +      system.
>> +
>> +  i2c-thermtrip:
>> +    type: object
>> +    description:
>> +      On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
>> +      hardware-triggered thermal reset will be enabled.
>> +
>> +    properties:
>> +      nvidia,i2c-controller-id:
>> +        $ref: /schemas/types.yaml#/definitions/uint32
>> +        description:
>> +          ID of I2C controller to send poweroff command to PMU.
>> +          Valid values are described in section 9.2.148
>> +          "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
>> +          Manual.
>> +
>> +      nvidia,bus-addr:
>> +        $ref: /schemas/types.yaml#/definitions/uint32
>> +        description: Bus address of the PMU on the I2C bus.
>> +
>> +      nvidia,reg-addr:
>> +        $ref: /schemas/types.yaml#/definitions/uint32
>> +        description: PMU I2C register address to issue poweroff command.
>> +
>> +      nvidia,reg-data:
>> +        $ref: /schemas/types.yaml#/definitions/uint32
>> +        description: Poweroff command to write to PMU.
>> +
>> +      nvidia,pinmux-id:
>> +        $ref: /schemas/types.yaml#/definitions/uint32
>> +        description:
>> +          Pinmux used by the hardware when issuing Poweroff command.
>> +          Defaults to 0. Valid values are described in section 12.5.2
>> +          "Pinmux Support" of the Tegra4 Technical Reference Manual.
>> +
>> +    required:
>> +      - nvidia,i2c-controller-id
>> +      - nvidia,bus-addr
>> +      - nvidia,reg-addr
>> +      - nvidia,reg-data
>         additionalProperties: false
>
>> +
>> +  powergates:
>> +    type: object
>> +    description:
>> +      This node contains a hierarchy of power domain nodes, which should
>> +      match the powergates on the Tegra SoC. Each powergate node
>> +      represents a power-domain on the Tegra SoC that can be power-gated
>> +      by the Tegra PMC.
>> +      Hardware blocks belonging to a power domain should contain
>> +      "power-domains" property that is a phandle pointing to corresponding
>> +      powergate node.
>> +      Please refer to Tegra TRM for mode details on the powergate nodes to
>> +      use for each power-gate block inside Tegra.
>> +
>> +    patternProperties:
>> +      "^[a-z0-9]+$":
>> +        if:
>> +          type: object
> It's better if you have node name patterns to match on than have to do
> this if/then.

All existing device trees are using power-gate block name as node name 
and these block names are Tegra internal block names as specified in TRM.

So, there are no node name pattern as node name is same as tegra 
internal block name which is a combination of letters and numeric.

>> +        then:
>> +          patternProperties:
>> +            clocks:
>> +              description:
>> +                Must contain an entry for each clock required by the PMC
>> +                for controlling a power-gate.
>> +                See ../clocks/clock-bindings.txt document for more details.
>> +
>> +            resets:
>> +              description:
>> +                Must contain an entry for each reset required by the PMC
>> +                for controlling a power-gate.
>> +                See ../reset/reset.txt for more details.
>> +
>> +            '#power-domain-cells':
>> +              description: Must be 0.
>> +
>> +    required:
>> +      - clocks
>> +      - resets
>> +      - '#power-domain-cells'
> These need property definitions.
>
>> +
>> +patternProperties:
>> +  "^.*@[0-9a-f]+$":
>> +    type: object
>> +
>> +    properties:
>> +      pins:
>> +        $ref: /schemas/types.yaml#/definitions/string
>> +        description: Must contain name of the pad(s) to be configured.
>> +
>> +      low-power-enable:
>> +        $ref: /schemas/types.yaml#/definitions/flag
>> +        description: Configure the pad into power down mode.
>> +
>> +      low-power-disable:
>> +        $ref: /schemas/types.yaml#/definitions/flag
>> +        description: Configure the pad into active mode.
>> +
>> +      power-source:
>> +        $ref: /schemas/types.yaml#/definitions/uint32
>> +        description:
>> +          Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
>> +          TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
>> +          The values are defined in
>> +          include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
>> +          Power state can be configured on all Tegra124 and Tegra132
>> +          pads. None of the Tegra124 or Tegra132 pads support signaling
>> +          voltage switching.
>> +          All of the listed Tegra210 pads except pex-cntrl support power
>> +          state configuration. Signaling voltage switching is supported
>> +          on below Tegra210 pads.
>> +          audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
>> +          sdmmc3, spi, spi-hv, and uart.
>> +
>> +    required:
>> +      - pins
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - clock-names
>> +  - clocks
>> +  - '#clock-cells'
>> +
>> +if:
>> +  properties:
>> +    nvidia,suspend-mode:
>> +      contains:
>> +        const: 2
>> +
>> +then:
>> +  required:
>> +    - nvidia,cpu-pwr-good-time
>> +    - nvidia,cpu-pwr-off-time
>> +    - nvidia,core-pwr-good-time
>> +    - nvidia,core-pwr-off-time
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/soc/tegra-pmc.h>
>> +
>> +    pmc: pmc@7000e400 {
>> +              compatible = "nvidia,tegra210-pmc";
>> +              reg = <0x0 0x7000e400 0x0 0x400>;
>> +              clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
>> +              clock-names = "pclk", "clk32k_in";
>> +              #clock-cells = <1>;
>> +
>> +              powergates {
>> +                    pd_audio: aud {
>> +                            clocks = <&tegra_car TEGRA210_CLK_APE>,
>> +                                     <&tegra_car TEGRA210_CLK_APB2APE>;
>> +                            resets = <&tegra_car 198>;
>> +                            #power-domain-cells = <0>;
>> +                    };
>> +
>> +                    pd_xusbss: xusba {
>> +                            clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
>> +                            resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
>> +                            #power-domain-cells = <0>;
>> +                    };
>> +              };
>> +
>> +              sdmmc1_3v3: sdmmc1-3v3 {
>> +                      pins = "sdmmc1";
>> +                      power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
>> +              };
>> +
>> +              sdmmc1_1v8: sdmmc1-1v8 {
>> +                      pins = "sdmmc1";
>> +                      power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
>> +              };
>> +
>> +              nvidia,invert-interrupt;
>> +              nvidia,suspend-mode = <0>;
>> +              nvidia,cpu-pwr-good-time = <0>;
>> +              nvidia,cpu-pwr-off-time = <0>;
>> +              nvidia,core-pwr-good-time = <4587 3876>;
>> +              nvidia,core-pwr-off-time = <39065>;
>> +              nvidia,core-power-req-active-high;
>> +              nvidia,sys-clock-req-active-high;
>> +    };
>> -- 
>> 2.7.4
>>

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-18 21:44       ` Dmitry Osipenko
@ 2019-12-19  0:41         ` Sowjanya Komatineni
  2019-12-20  1:21           ` Sowjanya Komatineni
  0 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-19  0:41 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/18/19 1:44 PM, Dmitry Osipenko wrote:
> 18.12.2019 11:35, Dmitry Osipenko пишет:
>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
>>>> these PMC clocks are registered by Tegra clock driver with each clock as
>>>> separate mux and gate clocks using clk_register_mux and clk_register_gate
>>>> by passing PMC base address and register offsets and PMC programming for
>>>> these clocks happens through direct PMC access by the clock driver.
>>>>
>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>> non-secure world does not go through and these clocks will not be
>>>> functional.
>>>>
>>>> This patch adds these PMC clocks registration to pmc driver with PMC as
>>>> a clock provider and registers each clock as single clock.
>>>>
>>>> clk_ops callback implementations for these clocks uses tegra_pmc_readl and
>>>> tegra_pmc_writel which supports PMC programming in both secure mode and
>>>> non-secure mode.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>>   drivers/soc/tegra/pmc.c | 248 ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>   1 file changed, 248 insertions(+)
>>>>
>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>> --- a/drivers/soc/tegra/pmc.c
>>>> +++ b/drivers/soc/tegra/pmc.c
>>>> @@ -13,6 +13,9 @@
>>>>   
>>>>   #include <linux/arm-smccc.h>
>>>>   #include <linux/clk.h>
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/clkdev.h>
>>>> +#include <linux/clk/clk-conf.h>
>>>>   #include <linux/clk/tegra.h>
>>>>   #include <linux/debugfs.h>
>>>>   #include <linux/delay.h>
>>>> @@ -48,6 +51,7 @@
>>>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>   
>>>>   #define PMC_CNTRL			0x0
>>>>   #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
>>>> @@ -100,6 +104,7 @@
>>>>   #define PMC_WAKE2_STATUS		0x168
>>>>   #define PMC_SW_WAKE2_STATUS		0x16c
>>>>   
>>>> +#define PMC_CLK_OUT_CNTRL		0x1a8
>>>>   #define PMC_SENSOR_CTRL			0x1b0
>>>>   #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
>>>>   #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
>>>> @@ -155,6 +160,64 @@
>>>>   #define  TEGRA_SMC_PMC_READ	0xaa
>>>>   #define  TEGRA_SMC_PMC_WRITE	0xbb
>>>>   
>>>> +struct pmc_clk {
>>>> +	struct clk_hw	hw;
>>>> +	unsigned long	offs;
>>>> +	u32		mux_mask;
>>>> +	u32		mux_shift;
>>>> +	u32		gate_shift;
>>>> +};
>>>> +
>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>> +
>>>> +struct pmc_clk_init_data {
>>>> +	char *name;
>>>> +	const char *const *parents;
>>>> +	int num_parents;
>>>> +	int clk_id;
>>>> +	u8 mux_shift;
>>>> +	u8 gate_shift;
>>>> +};
>>>> +
>>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>>> +	"osc_div4", "extern1",
>>>> +};
>>>> +
>>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>>> +	"osc_div4", "extern2",
>>>> +};
>>>> +
>>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>>> +	"osc_div4", "extern3",
>>>> +};
>>>> +
>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>> +	{
>>>> +		.name = "clk_out_1",
>>>> +		.parents = clk_out1_parents,
>>>> +		.num_parents = ARRAY_SIZE(clk_out1_parents),
>>>> +		.clk_id = TEGRA_PMC_CLK_OUT_1,
>>>> +		.mux_shift = 6,
>>>> +		.gate_shift = 2,
>>> I'd replace these with a single .shift, given that mux_shift =
>>> gate_shift + 4 for all clocks.
>>>
>>>> +	},
>>>> +	{
>>>> +		.name = "clk_out_2",
>>>> +		.parents = clk_out2_parents,
>>>> +		.num_parents = ARRAY_SIZE(clk_out2_parents),
>>>> +		.clk_id = TEGRA_PMC_CLK_OUT_2,
>>>> +		.mux_shift = 14,
>>>> +		.gate_shift = 10,
>>>> +	},
>>>> +	{
>>>> +		.name = "clk_out_3",
>>>> +		.parents = clk_out3_parents,
>>>> +		.num_parents = ARRAY_SIZE(clk_out3_parents),
>>>> +		.clk_id = TEGRA_PMC_CLK_OUT_3,
>>>> +		.mux_shift = 22,
>>>> +		.gate_shift = 18,
>>>> +	},
>>>> +};
>>>> +
>>>>   struct tegra_powergate {
>>>>   	struct generic_pm_domain genpd;
>>>>   	struct tegra_pmc *pmc;
>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>   	 */
>>>>   	const struct tegra_wake_event *wake_events;
>>>>   	unsigned int num_wake_events;
>>>> +
>>>> +	const struct pmc_clk_init_data *pmc_clks_data;
>>>> +	unsigned int num_pmc_clks;
>>>>   };
>>>>   
>>>>   static const char * const tegra186_reset_sources[] = {
>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
>>>>   	return NOTIFY_OK;
>>>>   }
>>>>   
>>>> +static void pmc_clk_fence_udelay(u32 offset)
>>>> +{
>>>> +	tegra_pmc_readl(pmc, offset);
>>>> +	/* pmc clk propagation delay 2 us */
>>>> +	udelay(2);
>>>> +}
>>>> +
>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>> +{
>>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +	u32 val;
>>>> +
>>>> +	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>> +	val &= clk->mux_mask;
>>>> +
>>>> +	return val;
>>>> +}
>>>> +
>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>> +{
>>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +	u32 val;
>>>> +
>>>> +	val = tegra_pmc_readl(pmc, clk->offs);
>>>> +	val &= ~(clk->mux_mask << clk->mux_shift);
>>>> +	val |= index << clk->mux_shift;
>>>> +	tegra_pmc_writel(pmc, val, clk->offs);
>>>> +	pmc_clk_fence_udelay(clk->offs);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>> +{
>>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +
>>>> +	return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift) ? 1 : 0;
>>>> +}
>>>> +
>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
>>>> +{
>>>> +	u32 val;
>>>> +
>>>> +	val = tegra_pmc_readl(pmc, offs);
>>>> +	val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>> +	tegra_pmc_writel(pmc, val, offs);
>>>> +	pmc_clk_fence_udelay(offs);
>>>> +}
>>>> +
>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>> +{
>>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +
>>>> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>> +{
>>>> +	struct pmc_clk *clk = to_pmc_clk(hw);
>>>> +
>>>> +	pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>> +}
>>>> +
>>>> +static const struct clk_ops pmc_clk_ops = {
>>>> +	.get_parent = pmc_clk_mux_get_parent,
>>>> +	.set_parent = pmc_clk_mux_set_parent,
>>>> +	.determine_rate = __clk_mux_determine_rate,
>>>> +	.is_enabled = pmc_clk_is_enabled,
>>>> +	.enable = pmc_clk_enable,
>>>> +	.disable = pmc_clk_disable,
>>>> +};
>>>> +
>>>> +static struct clk *
>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>> +			   unsigned long offset)
>>>> +{
>>>> +	struct clk_init_data init;
>>>> +	struct pmc_clk *pmc_clk;
>>>> +
>>>> +	pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>> +	if (!pmc_clk)
>>>> +		return ERR_PTR(-ENOMEM);
>>>> +
>>>> +	init.name = data->name;
>>>> +	init.ops = &pmc_clk_ops;
>>>> +	init.parent_names = data->parents;
>>>> +	init.num_parents = data->num_parents;
>>>> +	init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>> +		     CLK_SET_PARENT_GATE;
>>>> +
>>>> +	pmc_clk->hw.init = &init;
>>>> +	pmc_clk->offs = offset;
>>>> +	pmc_clk->mux_mask = 3;
>>> If mux_mask is a constant value, perhaps will be better to replace the
>>> variable with a literal?
>>>
>>> #define PMC_CLK_OUT_MUX_MASK	GENMASK(1, 0)
>> Maybe even:
>>
>> #define PMC_CLK_OUT_MUX_MASK(c)	GENMASK(c->shift + 1, c->shift)

MUX Mask is used only here for PMC clock out and is same for all clk_out 
mux so will use

#define PMC_CLK_OUT_MUX_MASK	GENMASK(1, 0)

> I want to point out that may be a separated gate/mux shifts is a fine
> variant, you should try and see whether another variants produce more
> concise result.
>
> [snip]

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-19  0:41         ` Sowjanya Komatineni
@ 2019-12-20  1:21           ` Sowjanya Komatineni
  2019-12-20  1:39             ` Dmitry Osipenko
  0 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-20  1:21 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/18/19 4:41 PM, Sowjanya Komatineni wrote:
>
> On 12/18/19 1:44 PM, Dmitry Osipenko wrote:
>> 18.12.2019 11:35, Dmitry Osipenko пишет:
>>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and 
>>>>> currently
>>>>> these PMC clocks are registered by Tegra clock driver with each 
>>>>> clock as
>>>>> separate mux and gate clocks using clk_register_mux and 
>>>>> clk_register_gate
>>>>> by passing PMC base address and register offsets and PMC 
>>>>> programming for
>>>>> these clocks happens through direct PMC access by the clock driver.
>>>>>
>>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>>> non-secure world does not go through and these clocks will not be
>>>>> functional.
>>>>>
>>>>> This patch adds these PMC clocks registration to pmc driver with 
>>>>> PMC as
>>>>> a clock provider and registers each clock as single clock.
>>>>>
>>>>> clk_ops callback implementations for these clocks uses 
>>>>> tegra_pmc_readl and
>>>>> tegra_pmc_writel which supports PMC programming in both secure 
>>>>> mode and
>>>>> non-secure mode.
>>>>>
>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>> ---
>>>>>   drivers/soc/tegra/pmc.c | 248 
>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>   1 file changed, 248 insertions(+)
>>>>>
>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>> @@ -13,6 +13,9 @@
>>>>>     #include <linux/arm-smccc.h>
>>>>>   #include <linux/clk.h>
>>>>> +#include <linux/clk-provider.h>
>>>>> +#include <linux/clkdev.h>
>>>>> +#include <linux/clk/clk-conf.h>
>>>>>   #include <linux/clk/tegra.h>
>>>>>   #include <linux/debugfs.h>
>>>>>   #include <linux/delay.h>
>>>>> @@ -48,6 +51,7 @@
>>>>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>     #define PMC_CNTRL            0x0
>>>>>   #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR 
>>>>> polarity */
>>>>> @@ -100,6 +104,7 @@
>>>>>   #define PMC_WAKE2_STATUS        0x168
>>>>>   #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>   +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>   #define PMC_SENSOR_CTRL            0x1b0
>>>>>   #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>   #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>> @@ -155,6 +160,64 @@
>>>>>   #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>   #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>   +struct pmc_clk {
>>>>> +    struct clk_hw    hw;
>>>>> +    unsigned long    offs;
>>>>> +    u32        mux_mask;
>>>>> +    u32        mux_shift;
>>>>> +    u32        gate_shift;
>>>>> +};
>>>>> +
>>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>>> +
>>>>> +struct pmc_clk_init_data {
>>>>> +    char *name;
>>>>> +    const char *const *parents;
>>>>> +    int num_parents;
>>>>> +    int clk_id;
>>>>> +    u8 mux_shift;
>>>>> +    u8 gate_shift;
>>>>> +};
>>>>> +
>>>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>>>> +    "osc_div4", "extern1",
>>>>> +};
>>>>> +
>>>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>>>> +    "osc_div4", "extern2",
>>>>> +};
>>>>> +
>>>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>>>> +    "osc_div4", "extern3",
>>>>> +};
>>>>> +
>>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>> +    {
>>>>> +        .name = "clk_out_1",
>>>>> +        .parents = clk_out1_parents,
>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_1,
>>>>> +        .mux_shift = 6,
>>>>> +        .gate_shift = 2,
>>>> I'd replace these with a single .shift, given that mux_shift =
>>>> gate_shift + 4 for all clocks.
>>>>
>>>>> +    },
>>>>> +    {
>>>>> +        .name = "clk_out_2",
>>>>> +        .parents = clk_out2_parents,
>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_2,
>>>>> +        .mux_shift = 14,
>>>>> +        .gate_shift = 10,
>>>>> +    },
>>>>> +    {
>>>>> +        .name = "clk_out_3",
>>>>> +        .parents = clk_out3_parents,
>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_3,
>>>>> +        .mux_shift = 22,
>>>>> +        .gate_shift = 18,
>>>>> +    },
>>>>> +};
>>>>> +
>>>>>   struct tegra_powergate {
>>>>>       struct generic_pm_domain genpd;
>>>>>       struct tegra_pmc *pmc;
>>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>>        */
>>>>>       const struct tegra_wake_event *wake_events;
>>>>>       unsigned int num_wake_events;
>>>>> +
>>>>> +    const struct pmc_clk_init_data *pmc_clks_data;
>>>>> +    unsigned int num_pmc_clks;
>>>>>   };
>>>>>     static const char * const tegra186_reset_sources[] = {
>>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct 
>>>>> notifier_block *nb,
>>>>>       return NOTIFY_OK;
>>>>>   }
>>>>>   +static void pmc_clk_fence_udelay(u32 offset)
>>>>> +{
>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>> +    /* pmc clk propagation delay 2 us */
>>>>> +    udelay(2);
>>>>> +}
>>>>> +
>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +    u32 val;
>>>>> +
>>>>> +    val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>>> +    val &= clk->mux_mask;
>>>>> +
>>>>> +    return val;
>>>>> +}
>>>>> +
>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +    u32 val;
>>>>> +
>>>>> +    val = tegra_pmc_readl(pmc, clk->offs);
>>>>> +    val &= ~(clk->mux_mask << clk->mux_shift);
>>>>> +    val |= index << clk->mux_shift;
>>>>> +    tegra_pmc_writel(pmc, val, clk->offs);
>>>>> +    pmc_clk_fence_udelay(clk->offs);
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +
>>>>> +    return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift) 
>>>>> ? 1 : 0;
>>>>> +}
>>>>> +
>>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int 
>>>>> state)
>>>>> +{
>>>>> +    u32 val;
>>>>> +
>>>>> +    val = tegra_pmc_readl(pmc, offs);
>>>>> +    val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>>> +    tegra_pmc_writel(pmc, val, offs);
>>>>> +    pmc_clk_fence_udelay(offs);
>>>>> +}
>>>>> +
>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +
>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>> +{
>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>> +
>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>>> +}
>>>>> +
>>>>> +static const struct clk_ops pmc_clk_ops = {
>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>> +    .enable = pmc_clk_enable,
>>>>> +    .disable = pmc_clk_disable,
>>>>> +};
>>>>> +
>>>>> +static struct clk *
>>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>>> +               unsigned long offset)
>>>>> +{
>>>>> +    struct clk_init_data init;
>>>>> +    struct pmc_clk *pmc_clk;
>>>>> +
>>>>> +    pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>>> +    if (!pmc_clk)
>>>>> +        return ERR_PTR(-ENOMEM);
>>>>> +
>>>>> +    init.name = data->name;
>>>>> +    init.ops = &pmc_clk_ops;
>>>>> +    init.parent_names = data->parents;
>>>>> +    init.num_parents = data->num_parents;
>>>>> +    init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>>> +             CLK_SET_PARENT_GATE;
>>>>> +
>>>>> +    pmc_clk->hw.init = &init;
>>>>> +    pmc_clk->offs = offset;
>>>>> +    pmc_clk->mux_mask = 3;
>>>> If mux_mask is a constant value, perhaps will be better to replace the
>>>> variable with a literal?
>>>>
>>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>> Maybe even:
>>>
>>> #define PMC_CLK_OUT_MUX_MASK(c)    GENMASK(c->shift + 1, c->shift)
>
> MUX Mask is used only here for PMC clock out and is same for all 
> clk_out mux so will use
>
> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>
>> I want to point out that may be a separated gate/mux shifts is a fine
>> variant, you should try and see whether another variants produce more
>> concise result.
>>
>> [snip]

We can do mux_shift as gate_shift + 4 and that restricts this clk 
register only for clk1/2/3 as well and there are no other clocks in pmc 
anyway.

How about using bit shift define for CLK1, CLK2, and CLK3?

.mux_shift = PMC_CLK1_SRC_SEL_SHIFT,

.gate_shift = PMC_CLK1_FORCE_EN_SHIFT,



^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-20  1:21           ` Sowjanya Komatineni
@ 2019-12-20  1:39             ` Dmitry Osipenko
  2019-12-20  4:13               ` Sowjanya Komatineni
  0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-20  1:39 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

20.12.2019 04:21, Sowjanya Komatineni пишет:
> 
> On 12/18/19 4:41 PM, Sowjanya Komatineni wrote:
>>
>> On 12/18/19 1:44 PM, Dmitry Osipenko wrote:
>>> 18.12.2019 11:35, Dmitry Osipenko пишет:
>>>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and
>>>>>> currently
>>>>>> these PMC clocks are registered by Tegra clock driver with each
>>>>>> clock as
>>>>>> separate mux and gate clocks using clk_register_mux and
>>>>>> clk_register_gate
>>>>>> by passing PMC base address and register offsets and PMC
>>>>>> programming for
>>>>>> these clocks happens through direct PMC access by the clock driver.
>>>>>>
>>>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>>>> non-secure world does not go through and these clocks will not be
>>>>>> functional.
>>>>>>
>>>>>> This patch adds these PMC clocks registration to pmc driver with
>>>>>> PMC as
>>>>>> a clock provider and registers each clock as single clock.
>>>>>>
>>>>>> clk_ops callback implementations for these clocks uses
>>>>>> tegra_pmc_readl and
>>>>>> tegra_pmc_writel which supports PMC programming in both secure
>>>>>> mode and
>>>>>> non-secure mode.
>>>>>>
>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>> ---
>>>>>>   drivers/soc/tegra/pmc.c | 248
>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>   1 file changed, 248 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>> @@ -13,6 +13,9 @@
>>>>>>     #include <linux/arm-smccc.h>
>>>>>>   #include <linux/clk.h>
>>>>>> +#include <linux/clk-provider.h>
>>>>>> +#include <linux/clkdev.h>
>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>   #include <linux/clk/tegra.h>
>>>>>>   #include <linux/debugfs.h>
>>>>>>   #include <linux/delay.h>
>>>>>> @@ -48,6 +51,7 @@
>>>>>>   #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>   #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>   #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>     #define PMC_CNTRL            0x0
>>>>>>   #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>> polarity */
>>>>>> @@ -100,6 +104,7 @@
>>>>>>   #define PMC_WAKE2_STATUS        0x168
>>>>>>   #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>   +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>   #define PMC_SENSOR_CTRL            0x1b0
>>>>>>   #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>>   #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>>> @@ -155,6 +160,64 @@
>>>>>>   #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>   #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>   +struct pmc_clk {
>>>>>> +    struct clk_hw    hw;
>>>>>> +    unsigned long    offs;
>>>>>> +    u32        mux_mask;
>>>>>> +    u32        mux_shift;
>>>>>> +    u32        gate_shift;
>>>>>> +};
>>>>>> +
>>>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>>>> +
>>>>>> +struct pmc_clk_init_data {
>>>>>> +    char *name;
>>>>>> +    const char *const *parents;
>>>>>> +    int num_parents;
>>>>>> +    int clk_id;
>>>>>> +    u8 mux_shift;
>>>>>> +    u8 gate_shift;
>>>>>> +};
>>>>>> +
>>>>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>>>>> +    "osc_div4", "extern1",
>>>>>> +};
>>>>>> +
>>>>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>>>>> +    "osc_div4", "extern2",
>>>>>> +};
>>>>>> +
>>>>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>>>>> +    "osc_div4", "extern3",
>>>>>> +};
>>>>>> +
>>>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>> +    {
>>>>>> +        .name = "clk_out_1",
>>>>>> +        .parents = clk_out1_parents,
>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_1,
>>>>>> +        .mux_shift = 6,
>>>>>> +        .gate_shift = 2,
>>>>> I'd replace these with a single .shift, given that mux_shift =
>>>>> gate_shift + 4 for all clocks.
>>>>>
>>>>>> +    },
>>>>>> +    {
>>>>>> +        .name = "clk_out_2",
>>>>>> +        .parents = clk_out2_parents,
>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_2,
>>>>>> +        .mux_shift = 14,
>>>>>> +        .gate_shift = 10,
>>>>>> +    },
>>>>>> +    {
>>>>>> +        .name = "clk_out_3",
>>>>>> +        .parents = clk_out3_parents,
>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_3,
>>>>>> +        .mux_shift = 22,
>>>>>> +        .gate_shift = 18,
>>>>>> +    },
>>>>>> +};
>>>>>> +
>>>>>>   struct tegra_powergate {
>>>>>>       struct generic_pm_domain genpd;
>>>>>>       struct tegra_pmc *pmc;
>>>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>>>        */
>>>>>>       const struct tegra_wake_event *wake_events;
>>>>>>       unsigned int num_wake_events;
>>>>>> +
>>>>>> +    const struct pmc_clk_init_data *pmc_clks_data;
>>>>>> +    unsigned int num_pmc_clks;
>>>>>>   };
>>>>>>     static const char * const tegra186_reset_sources[] = {
>>>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>>> notifier_block *nb,
>>>>>>       return NOTIFY_OK;
>>>>>>   }
>>>>>>   +static void pmc_clk_fence_udelay(u32 offset)
>>>>>> +{
>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>> +    udelay(2);
>>>>>> +}
>>>>>> +
>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +    u32 val;
>>>>>> +
>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>>>> +    val &= clk->mux_mask;
>>>>>> +
>>>>>> +    return val;
>>>>>> +}
>>>>>> +
>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +    u32 val;
>>>>>> +
>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs);
>>>>>> +    val &= ~(clk->mux_mask << clk->mux_shift);
>>>>>> +    val |= index << clk->mux_shift;
>>>>>> +    tegra_pmc_writel(pmc, val, clk->offs);
>>>>>> +    pmc_clk_fence_udelay(clk->offs);

Is this fencing applies only to clock changes or maybe it won't hurt to
move it into tegra_pmc_writel()?

>>>>>> +    return 0;
>>>>>> +}
>>>>>> +
>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +
>>>>>> +    return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift)
>>>>>> ? 1 : 0;
>>>>>> +}
>>>>>> +
>>>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int
>>>>>> state)
>>>>>> +{
>>>>>> +    u32 val;
>>>>>> +
>>>>>> +    val = tegra_pmc_readl(pmc, offs);
>>>>>> +    val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>>>> +    tegra_pmc_writel(pmc, val, offs);
>>>>>> +    pmc_clk_fence_udelay(offs);
>>>>>> +}
>>>>>> +
>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +
>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>>>> +
>>>>>> +    return 0;
>>>>>> +}
>>>>>> +
>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>> +{
>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>> +
>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>>>> +}
>>>>>> +
>>>>>> +static const struct clk_ops pmc_clk_ops = {
>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>> +    .enable = pmc_clk_enable,
>>>>>> +    .disable = pmc_clk_disable,
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk *
>>>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>>>> +               unsigned long offset)
>>>>>> +{
>>>>>> +    struct clk_init_data init;
>>>>>> +    struct pmc_clk *pmc_clk;
>>>>>> +
>>>>>> +    pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>>>> +    if (!pmc_clk)
>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>> +
>>>>>> +    init.name = data->name;
>>>>>> +    init.ops = &pmc_clk_ops;
>>>>>> +    init.parent_names = data->parents;
>>>>>> +    init.num_parents = data->num_parents;
>>>>>> +    init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>>>> +             CLK_SET_PARENT_GATE;
>>>>>> +
>>>>>> +    pmc_clk->hw.init = &init;
>>>>>> +    pmc_clk->offs = offset;
>>>>>> +    pmc_clk->mux_mask = 3;
>>>>> If mux_mask is a constant value, perhaps will be better to replace the
>>>>> variable with a literal?
>>>>>
>>>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>>> Maybe even:
>>>>
>>>> #define PMC_CLK_OUT_MUX_MASK(c)    GENMASK(c->shift + 1, c->shift)
>>
>> MUX Mask is used only here for PMC clock out and is same for all
>> clk_out mux so will use
>>
>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>
>>> I want to point out that may be a separated gate/mux shifts is a fine
>>> variant, you should try and see whether another variants produce more
>>> concise result.
>>>
>>> [snip]
> 
> We can do mux_shift as gate_shift + 4 and that restricts this clk
> register only for clk1/2/3 as well and there are no other clocks in pmc
> anyway.
> 
> How about using bit shift define for CLK1, CLK2, and CLK3?
> 
> .mux_shift = PMC_CLK1_SRC_SEL_SHIFT,
> 
> .gate_shift = PMC_CLK1_FORCE_EN_SHIFT,
> 
> 

I think that just renaming ".gate_shift" -> ".force_en_shift" should be
good enough.

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-20  1:39             ` Dmitry Osipenko
@ 2019-12-20  4:13               ` Sowjanya Komatineni
  2019-12-20  4:34                 ` Dmitry Osipenko
  0 siblings, 1 reply; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-20  4:13 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/19/19 5:39 PM, Dmitry Osipenko wrote:
> 20.12.2019 04:21, Sowjanya Komatineni пишет:
>> On 12/18/19 4:41 PM, Sowjanya Komatineni wrote:
>>> On 12/18/19 1:44 PM, Dmitry Osipenko wrote:
>>>> 18.12.2019 11:35, Dmitry Osipenko пишет:
>>>>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>>>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and
>>>>>>> currently
>>>>>>> these PMC clocks are registered by Tegra clock driver with each
>>>>>>> clock as
>>>>>>> separate mux and gate clocks using clk_register_mux and
>>>>>>> clk_register_gate
>>>>>>> by passing PMC base address and register offsets and PMC
>>>>>>> programming for
>>>>>>> these clocks happens through direct PMC access by the clock driver.
>>>>>>>
>>>>>>> With this, when PMC is in secure mode any direct PMC access from the
>>>>>>> non-secure world does not go through and these clocks will not be
>>>>>>> functional.
>>>>>>>
>>>>>>> This patch adds these PMC clocks registration to pmc driver with
>>>>>>> PMC as
>>>>>>> a clock provider and registers each clock as single clock.
>>>>>>>
>>>>>>> clk_ops callback implementations for these clocks uses
>>>>>>> tegra_pmc_readl and
>>>>>>> tegra_pmc_writel which supports PMC programming in both secure
>>>>>>> mode and
>>>>>>> non-secure mode.
>>>>>>>
>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>> ---
>>>>>>>    drivers/soc/tegra/pmc.c | 248
>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>    1 file changed, 248 insertions(+)
>>>>>>>
>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>      #include <linux/arm-smccc.h>
>>>>>>>    #include <linux/clk.h>
>>>>>>> +#include <linux/clk-provider.h>
>>>>>>> +#include <linux/clkdev.h>
>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>    #include <linux/clk/tegra.h>
>>>>>>>    #include <linux/debugfs.h>
>>>>>>>    #include <linux/delay.h>
>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>    #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>    #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>    #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>      #define PMC_CNTRL            0x0
>>>>>>>    #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>>> polarity */
>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>    #define PMC_WAKE2_STATUS        0x168
>>>>>>>    #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>>    +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>>    #define PMC_SENSOR_CTRL            0x1b0
>>>>>>>    #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>>>    #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>>>> @@ -155,6 +160,64 @@
>>>>>>>    #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>    #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>    +struct pmc_clk {
>>>>>>> +    struct clk_hw    hw;
>>>>>>> +    unsigned long    offs;
>>>>>>> +    u32        mux_mask;
>>>>>>> +    u32        mux_shift;
>>>>>>> +    u32        gate_shift;
>>>>>>> +};
>>>>>>> +
>>>>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>>>>> +
>>>>>>> +struct pmc_clk_init_data {
>>>>>>> +    char *name;
>>>>>>> +    const char *const *parents;
>>>>>>> +    int num_parents;
>>>>>>> +    int clk_id;
>>>>>>> +    u8 mux_shift;
>>>>>>> +    u8 gate_shift;
>>>>>>> +};
>>>>>>> +
>>>>>>> +static const char * const clk_out1_parents[] = { "osc", "osc_div2",
>>>>>>> +    "osc_div4", "extern1",
>>>>>>> +};
>>>>>>> +
>>>>>>> +static const char * const clk_out2_parents[] = { "osc", "osc_div2",
>>>>>>> +    "osc_div4", "extern2",
>>>>>>> +};
>>>>>>> +
>>>>>>> +static const char * const clk_out3_parents[] = { "osc", "osc_div2",
>>>>>>> +    "osc_div4", "extern3",
>>>>>>> +};
>>>>>>> +
>>>>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>> +    {
>>>>>>> +        .name = "clk_out_1",
>>>>>>> +        .parents = clk_out1_parents,
>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>> +        .mux_shift = 6,
>>>>>>> +        .gate_shift = 2,
>>>>>> I'd replace these with a single .shift, given that mux_shift =
>>>>>> gate_shift + 4 for all clocks.
>>>>>>
>>>>>>> +    },
>>>>>>> +    {
>>>>>>> +        .name = "clk_out_2",
>>>>>>> +        .parents = clk_out2_parents,
>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>> +        .mux_shift = 14,
>>>>>>> +        .gate_shift = 10,
>>>>>>> +    },
>>>>>>> +    {
>>>>>>> +        .name = "clk_out_3",
>>>>>>> +        .parents = clk_out3_parents,
>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>> +        .mux_shift = 22,
>>>>>>> +        .gate_shift = 18,
>>>>>>> +    },
>>>>>>> +};
>>>>>>> +
>>>>>>>    struct tegra_powergate {
>>>>>>>        struct generic_pm_domain genpd;
>>>>>>>        struct tegra_pmc *pmc;
>>>>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>>>>         */
>>>>>>>        const struct tegra_wake_event *wake_events;
>>>>>>>        unsigned int num_wake_events;
>>>>>>> +
>>>>>>> +    const struct pmc_clk_init_data *pmc_clks_data;
>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>    };
>>>>>>>      static const char * const tegra186_reset_sources[] = {
>>>>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>>>> notifier_block *nb,
>>>>>>>        return NOTIFY_OK;
>>>>>>>    }
>>>>>>>    +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>> +{
>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>> +    udelay(2);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>> +{
>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>> +    u32 val;
>>>>>>> +
>>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>>>>> +    val &= clk->mux_mask;
>>>>>>> +
>>>>>>> +    return val;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>>> +{
>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>> +    u32 val;
>>>>>>> +
>>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs);
>>>>>>> +    val &= ~(clk->mux_mask << clk->mux_shift);
>>>>>>> +    val |= index << clk->mux_shift;
>>>>>>> +    tegra_pmc_writel(pmc, val, clk->offs);
>>>>>>> +    pmc_clk_fence_udelay(clk->offs);
> Is this fencing applies only to clock changes or maybe it won't hurt to
> move it into tegra_pmc_writel()?
>
>>>>>>> +    return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>> +{
>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>> +
>>>>>>> +    return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift)
>>>>>>> ? 1 : 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int
>>>>>>> state)
>>>>>>> +{
>>>>>>> +    u32 val;
>>>>>>> +
>>>>>>> +    val = tegra_pmc_readl(pmc, offs);
>>>>>>> +    val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>>>>> +    tegra_pmc_writel(pmc, val, offs);
>>>>>>> +    pmc_clk_fence_udelay(offs);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>> +{
>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>> +
>>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>>>>> +
>>>>>>> +    return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>> +{
>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>> +
>>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct clk_ops pmc_clk_ops = {
>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>> +};
>>>>>>> +
>>>>>>> +static struct clk *
>>>>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>>>>> +               unsigned long offset)
>>>>>>> +{
>>>>>>> +    struct clk_init_data init;
>>>>>>> +    struct pmc_clk *pmc_clk;
>>>>>>> +
>>>>>>> +    pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>>>>> +    if (!pmc_clk)
>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>> +
>>>>>>> +    init.name = data->name;
>>>>>>> +    init.ops = &pmc_clk_ops;
>>>>>>> +    init.parent_names = data->parents;
>>>>>>> +    init.num_parents = data->num_parents;
>>>>>>> +    init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>>>>> +             CLK_SET_PARENT_GATE;
>>>>>>> +
>>>>>>> +    pmc_clk->hw.init = &init;
>>>>>>> +    pmc_clk->offs = offset;
>>>>>>> +    pmc_clk->mux_mask = 3;
>>>>>> If mux_mask is a constant value, perhaps will be better to replace the
>>>>>> variable with a literal?
>>>>>>
>>>>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>>>> Maybe even:
>>>>>
>>>>> #define PMC_CLK_OUT_MUX_MASK(c)    GENMASK(c->shift + 1, c->shift)
>>> MUX Mask is used only here for PMC clock out and is same for all
>>> clk_out mux so will use
>>>
>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>>
>>>> I want to point out that may be a separated gate/mux shifts is a fine
>>>> variant, you should try and see whether another variants produce more
>>>> concise result.
>>>>
>>>> [snip]
>> We can do mux_shift as gate_shift + 4 and that restricts this clk
>> register only for clk1/2/3 as well and there are no other clocks in pmc
>> anyway.
>>
>> How about using bit shift define for CLK1, CLK2, and CLK3?
>>
>> .mux_shift = PMC_CLK1_SRC_SEL_SHIFT,
>>
>> .gate_shift = PMC_CLK1_FORCE_EN_SHIFT,
>>
>>
> I think that just renaming ".gate_shift" -> ".force_en_shift" should be
> good enough.
You meant to assign bit position directly instead of defines like what I 
have now in v4 and use force_en_shift instead of gate_shift?

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-20  4:13               ` Sowjanya Komatineni
@ 2019-12-20  4:34                 ` Dmitry Osipenko
  2019-12-20 19:06                   ` Sowjanya Komatineni
  0 siblings, 1 reply; 54+ messages in thread
From: Dmitry Osipenko @ 2019-12-20  4:34 UTC (permalink / raw)
  To: Sowjanya Komatineni, thierry.reding, jonathanh, mperttunen,
	gregkh, sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel

20.12.2019 07:13, Sowjanya Komatineni пишет:
> 
> On 12/19/19 5:39 PM, Dmitry Osipenko wrote:
>> 20.12.2019 04:21, Sowjanya Komatineni пишет:
>>> On 12/18/19 4:41 PM, Sowjanya Komatineni wrote:
>>>> On 12/18/19 1:44 PM, Dmitry Osipenko wrote:
>>>>> 18.12.2019 11:35, Dmitry Osipenko пишет:
>>>>>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>>>>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>>>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and
>>>>>>>> currently
>>>>>>>> these PMC clocks are registered by Tegra clock driver with each
>>>>>>>> clock as
>>>>>>>> separate mux and gate clocks using clk_register_mux and
>>>>>>>> clk_register_gate
>>>>>>>> by passing PMC base address and register offsets and PMC
>>>>>>>> programming for
>>>>>>>> these clocks happens through direct PMC access by the clock driver.
>>>>>>>>
>>>>>>>> With this, when PMC is in secure mode any direct PMC access from
>>>>>>>> the
>>>>>>>> non-secure world does not go through and these clocks will not be
>>>>>>>> functional.
>>>>>>>>
>>>>>>>> This patch adds these PMC clocks registration to pmc driver with
>>>>>>>> PMC as
>>>>>>>> a clock provider and registers each clock as single clock.
>>>>>>>>
>>>>>>>> clk_ops callback implementations for these clocks uses
>>>>>>>> tegra_pmc_readl and
>>>>>>>> tegra_pmc_writel which supports PMC programming in both secure
>>>>>>>> mode and
>>>>>>>> non-secure mode.
>>>>>>>>
>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>> ---
>>>>>>>>    drivers/soc/tegra/pmc.c | 248
>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>    1 file changed, 248 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>      #include <linux/arm-smccc.h>
>>>>>>>>    #include <linux/clk.h>
>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>    #include <linux/clk/tegra.h>
>>>>>>>>    #include <linux/debugfs.h>
>>>>>>>>    #include <linux/delay.h>
>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>    #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>    #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>    #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>      #define PMC_CNTRL            0x0
>>>>>>>>    #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>>>> polarity */
>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>    #define PMC_WAKE2_STATUS        0x168
>>>>>>>>    #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>>>    +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>>>    #define PMC_SENSOR_CTRL            0x1b0
>>>>>>>>    #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>>>>    #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>>>>> @@ -155,6 +160,64 @@
>>>>>>>>    #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>    #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>    +struct pmc_clk {
>>>>>>>> +    struct clk_hw    hw;
>>>>>>>> +    unsigned long    offs;
>>>>>>>> +    u32        mux_mask;
>>>>>>>> +    u32        mux_shift;
>>>>>>>> +    u32        gate_shift;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>>>>>> +
>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>> +    char *name;
>>>>>>>> +    const char *const *parents;
>>>>>>>> +    int num_parents;
>>>>>>>> +    int clk_id;
>>>>>>>> +    u8 mux_shift;
>>>>>>>> +    u8 gate_shift;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static const char * const clk_out1_parents[] = { "osc",
>>>>>>>> "osc_div2",
>>>>>>>> +    "osc_div4", "extern1",
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static const char * const clk_out2_parents[] = { "osc",
>>>>>>>> "osc_div2",
>>>>>>>> +    "osc_div4", "extern2",
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static const char * const clk_out3_parents[] = { "osc",
>>>>>>>> "osc_div2",
>>>>>>>> +    "osc_div4", "extern3",
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>> +    {
>>>>>>>> +        .name = "clk_out_1",
>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>> +        .mux_shift = 6,
>>>>>>>> +        .gate_shift = 2,
>>>>>>> I'd replace these with a single .shift, given that mux_shift =
>>>>>>> gate_shift + 4 for all clocks.
>>>>>>>
>>>>>>>> +    },
>>>>>>>> +    {
>>>>>>>> +        .name = "clk_out_2",
>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>> +        .mux_shift = 14,
>>>>>>>> +        .gate_shift = 10,
>>>>>>>> +    },
>>>>>>>> +    {
>>>>>>>> +        .name = "clk_out_3",
>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>> +        .mux_shift = 22,
>>>>>>>> +        .gate_shift = 18,
>>>>>>>> +    },
>>>>>>>> +};
>>>>>>>> +
>>>>>>>>    struct tegra_powergate {
>>>>>>>>        struct generic_pm_domain genpd;
>>>>>>>>        struct tegra_pmc *pmc;
>>>>>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>>>>>         */
>>>>>>>>        const struct tegra_wake_event *wake_events;
>>>>>>>>        unsigned int num_wake_events;
>>>>>>>> +
>>>>>>>> +    const struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>    };
>>>>>>>>      static const char * const tegra186_reset_sources[] = {
>>>>>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>>>>> notifier_block *nb,
>>>>>>>>        return NOTIFY_OK;
>>>>>>>>    }
>>>>>>>>    +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>> +{
>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>> +    udelay(2);
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>> +{
>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>> +    u32 val;
>>>>>>>> +
>>>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>>>>>> +    val &= clk->mux_mask;
>>>>>>>> +
>>>>>>>> +    return val;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>>>> +{
>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>> +    u32 val;
>>>>>>>> +
>>>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs);
>>>>>>>> +    val &= ~(clk->mux_mask << clk->mux_shift);
>>>>>>>> +    val |= index << clk->mux_shift;
>>>>>>>> +    tegra_pmc_writel(pmc, val, clk->offs);
>>>>>>>> +    pmc_clk_fence_udelay(clk->offs);
>> Is this fencing applies only to clock changes or maybe it won't hurt to
>> move it into tegra_pmc_writel()?
>>
>>>>>>>> +    return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>> +{
>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>> +
>>>>>>>> +    return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift)
>>>>>>>> ? 1 : 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int
>>>>>>>> state)
>>>>>>>> +{
>>>>>>>> +    u32 val;
>>>>>>>> +
>>>>>>>> +    val = tegra_pmc_readl(pmc, offs);
>>>>>>>> +    val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>>>>>> +    tegra_pmc_writel(pmc, val, offs);
>>>>>>>> +    pmc_clk_fence_udelay(offs);
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>> +{
>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>> +
>>>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>>>>>> +
>>>>>>>> +    return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>> +{
>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>> +
>>>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static const struct clk_ops pmc_clk_ops = {
>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static struct clk *
>>>>>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>>>>>> +               unsigned long offset)
>>>>>>>> +{
>>>>>>>> +    struct clk_init_data init;
>>>>>>>> +    struct pmc_clk *pmc_clk;
>>>>>>>> +
>>>>>>>> +    pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>>>>>> +    if (!pmc_clk)
>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>> +
>>>>>>>> +    init.name = data->name;
>>>>>>>> +    init.ops = &pmc_clk_ops;
>>>>>>>> +    init.parent_names = data->parents;
>>>>>>>> +    init.num_parents = data->num_parents;
>>>>>>>> +    init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>>>>>> +             CLK_SET_PARENT_GATE;
>>>>>>>> +
>>>>>>>> +    pmc_clk->hw.init = &init;
>>>>>>>> +    pmc_clk->offs = offset;
>>>>>>>> +    pmc_clk->mux_mask = 3;
>>>>>>> If mux_mask is a constant value, perhaps will be better to
>>>>>>> replace the
>>>>>>> variable with a literal?
>>>>>>>
>>>>>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>>>>> Maybe even:
>>>>>>
>>>>>> #define PMC_CLK_OUT_MUX_MASK(c)    GENMASK(c->shift + 1, c->shift)
>>>> MUX Mask is used only here for PMC clock out and is same for all
>>>> clk_out mux so will use
>>>>
>>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>>>
>>>>> I want to point out that may be a separated gate/mux shifts is a fine
>>>>> variant, you should try and see whether another variants produce more
>>>>> concise result.
>>>>>
>>>>> [snip]
>>> We can do mux_shift as gate_shift + 4 and that restricts this clk
>>> register only for clk1/2/3 as well and there are no other clocks in pmc
>>> anyway.
>>>
>>> How about using bit shift define for CLK1, CLK2, and CLK3?
>>>
>>> .mux_shift = PMC_CLK1_SRC_SEL_SHIFT,
>>>
>>> .gate_shift = PMC_CLK1_FORCE_EN_SHIFT,
>>>
>>>
>> I think that just renaming ".gate_shift" -> ".force_en_shift" should be
>> good enough.
> You meant to assign bit position directly instead of defines like what I
> have now in v4 and use force_en_shift instead of gate_shift?

Yes

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver
  2019-12-20  4:34                 ` Dmitry Osipenko
@ 2019-12-20 19:06                   ` Sowjanya Komatineni
  0 siblings, 0 replies; 54+ messages in thread
From: Sowjanya Komatineni @ 2019-12-20 19:06 UTC (permalink / raw)
  To: Dmitry Osipenko, thierry.reding, jonathanh, mperttunen, gregkh,
	sboyd, robh+dt, mark.rutland
  Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
	mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
	linux-kernel


On 12/19/19 8:34 PM, Dmitry Osipenko wrote:
> 20.12.2019 07:13, Sowjanya Komatineni пишет:
>> On 12/19/19 5:39 PM, Dmitry Osipenko wrote:
>>> 20.12.2019 04:21, Sowjanya Komatineni пишет:
>>>> On 12/18/19 4:41 PM, Sowjanya Komatineni wrote:
>>>>> On 12/18/19 1:44 PM, Dmitry Osipenko wrote:
>>>>>> 18.12.2019 11:35, Dmitry Osipenko пишет:
>>>>>>> 18.12.2019 11:30, Dmitry Osipenko пишет:
>>>>>>>> 17.12.2019 23:03, Sowjanya Komatineni пишет:
>>>>>>>>> Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and
>>>>>>>>> currently
>>>>>>>>> these PMC clocks are registered by Tegra clock driver with each
>>>>>>>>> clock as
>>>>>>>>> separate mux and gate clocks using clk_register_mux and
>>>>>>>>> clk_register_gate
>>>>>>>>> by passing PMC base address and register offsets and PMC
>>>>>>>>> programming for
>>>>>>>>> these clocks happens through direct PMC access by the clock driver.
>>>>>>>>>
>>>>>>>>> With this, when PMC is in secure mode any direct PMC access from
>>>>>>>>> the
>>>>>>>>> non-secure world does not go through and these clocks will not be
>>>>>>>>> functional.
>>>>>>>>>
>>>>>>>>> This patch adds these PMC clocks registration to pmc driver with
>>>>>>>>> PMC as
>>>>>>>>> a clock provider and registers each clock as single clock.
>>>>>>>>>
>>>>>>>>> clk_ops callback implementations for these clocks uses
>>>>>>>>> tegra_pmc_readl and
>>>>>>>>> tegra_pmc_writel which supports PMC programming in both secure
>>>>>>>>> mode and
>>>>>>>>> non-secure mode.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>> ---
>>>>>>>>>     drivers/soc/tegra/pmc.c | 248
>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>     1 file changed, 248 insertions(+)
>>>>>>>>>
>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>>> index ea0e11a09c12..6d65194a6e71 100644
>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>> @@ -13,6 +13,9 @@
>>>>>>>>>       #include <linux/arm-smccc.h>
>>>>>>>>>     #include <linux/clk.h>
>>>>>>>>> +#include <linux/clk-provider.h>
>>>>>>>>> +#include <linux/clkdev.h>
>>>>>>>>> +#include <linux/clk/clk-conf.h>
>>>>>>>>>     #include <linux/clk/tegra.h>
>>>>>>>>>     #include <linux/debugfs.h>
>>>>>>>>>     #include <linux/delay.h>
>>>>>>>>> @@ -48,6 +51,7 @@
>>>>>>>>>     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
>>>>>>>>>     #include <dt-bindings/gpio/tegra186-gpio.h>
>>>>>>>>>     #include <dt-bindings/gpio/tegra194-gpio.h>
>>>>>>>>> +#include <dt-bindings/soc/tegra-pmc.h>
>>>>>>>>>       #define PMC_CNTRL            0x0
>>>>>>>>>     #define  PMC_CNTRL_INTR_POLARITY    BIT(17) /* inverts INTR
>>>>>>>>> polarity */
>>>>>>>>> @@ -100,6 +104,7 @@
>>>>>>>>>     #define PMC_WAKE2_STATUS        0x168
>>>>>>>>>     #define PMC_SW_WAKE2_STATUS        0x16c
>>>>>>>>>     +#define PMC_CLK_OUT_CNTRL        0x1a8
>>>>>>>>>     #define PMC_SENSOR_CTRL            0x1b0
>>>>>>>>>     #define  PMC_SENSOR_CTRL_SCRATCH_WRITE    BIT(2)
>>>>>>>>>     #define  PMC_SENSOR_CTRL_ENABLE_RST    BIT(1)
>>>>>>>>> @@ -155,6 +160,64 @@
>>>>>>>>>     #define  TEGRA_SMC_PMC_READ    0xaa
>>>>>>>>>     #define  TEGRA_SMC_PMC_WRITE    0xbb
>>>>>>>>>     +struct pmc_clk {
>>>>>>>>> +    struct clk_hw    hw;
>>>>>>>>> +    unsigned long    offs;
>>>>>>>>> +    u32        mux_mask;
>>>>>>>>> +    u32        mux_shift;
>>>>>>>>> +    u32        gate_shift;
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
>>>>>>>>> +
>>>>>>>>> +struct pmc_clk_init_data {
>>>>>>>>> +    char *name;
>>>>>>>>> +    const char *const *parents;
>>>>>>>>> +    int num_parents;
>>>>>>>>> +    int clk_id;
>>>>>>>>> +    u8 mux_shift;
>>>>>>>>> +    u8 gate_shift;
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static const char * const clk_out1_parents[] = { "osc",
>>>>>>>>> "osc_div2",
>>>>>>>>> +    "osc_div4", "extern1",
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static const char * const clk_out2_parents[] = { "osc",
>>>>>>>>> "osc_div2",
>>>>>>>>> +    "osc_div4", "extern2",
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static const char * const clk_out3_parents[] = { "osc",
>>>>>>>>> "osc_div2",
>>>>>>>>> +    "osc_div4", "extern3",
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
>>>>>>>>> +    {
>>>>>>>>> +        .name = "clk_out_1",
>>>>>>>>> +        .parents = clk_out1_parents,
>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out1_parents),
>>>>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_1,
>>>>>>>>> +        .mux_shift = 6,
>>>>>>>>> +        .gate_shift = 2,
>>>>>>>> I'd replace these with a single .shift, given that mux_shift =
>>>>>>>> gate_shift + 4 for all clocks.
>>>>>>>>
>>>>>>>>> +    },
>>>>>>>>> +    {
>>>>>>>>> +        .name = "clk_out_2",
>>>>>>>>> +        .parents = clk_out2_parents,
>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out2_parents),
>>>>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_2,
>>>>>>>>> +        .mux_shift = 14,
>>>>>>>>> +        .gate_shift = 10,
>>>>>>>>> +    },
>>>>>>>>> +    {
>>>>>>>>> +        .name = "clk_out_3",
>>>>>>>>> +        .parents = clk_out3_parents,
>>>>>>>>> +        .num_parents = ARRAY_SIZE(clk_out3_parents),
>>>>>>>>> +        .clk_id = TEGRA_PMC_CLK_OUT_3,
>>>>>>>>> +        .mux_shift = 22,
>>>>>>>>> +        .gate_shift = 18,
>>>>>>>>> +    },
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>>     struct tegra_powergate {
>>>>>>>>>         struct generic_pm_domain genpd;
>>>>>>>>>         struct tegra_pmc *pmc;
>>>>>>>>> @@ -254,6 +317,9 @@ struct tegra_pmc_soc {
>>>>>>>>>          */
>>>>>>>>>         const struct tegra_wake_event *wake_events;
>>>>>>>>>         unsigned int num_wake_events;
>>>>>>>>> +
>>>>>>>>> +    const struct pmc_clk_init_data *pmc_clks_data;
>>>>>>>>> +    unsigned int num_pmc_clks;
>>>>>>>>>     };
>>>>>>>>>       static const char * const tegra186_reset_sources[] = {
>>>>>>>>> @@ -2163,6 +2229,173 @@ static int tegra_pmc_clk_notify_cb(struct
>>>>>>>>> notifier_block *nb,
>>>>>>>>>         return NOTIFY_OK;
>>>>>>>>>     }
>>>>>>>>>     +static void pmc_clk_fence_udelay(u32 offset)
>>>>>>>>> +{
>>>>>>>>> +    tegra_pmc_readl(pmc, offset);
>>>>>>>>> +    /* pmc clk propagation delay 2 us */
>>>>>>>>> +    udelay(2);
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
>>>>>>>>> +{
>>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>>> +    u32 val;
>>>>>>>>> +
>>>>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
>>>>>>>>> +    val &= clk->mux_mask;
>>>>>>>>> +
>>>>>>>>> +    return val;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>>>>>>>>> +{
>>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>>> +    u32 val;
>>>>>>>>> +
>>>>>>>>> +    val = tegra_pmc_readl(pmc, clk->offs);
>>>>>>>>> +    val &= ~(clk->mux_mask << clk->mux_shift);
>>>>>>>>> +    val |= index << clk->mux_shift;
>>>>>>>>> +    tegra_pmc_writel(pmc, val, clk->offs);
>>>>>>>>> +    pmc_clk_fence_udelay(clk->offs);
>>> Is this fencing applies only to clock changes or maybe it won't hurt to
>>> move it into tegra_pmc_writel()?
Only for clock changes
>>>
>>>>>>>>> +    return 0;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static int pmc_clk_is_enabled(struct clk_hw *hw)
>>>>>>>>> +{
>>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>>> +
>>>>>>>>> +    return tegra_pmc_readl(pmc, clk->offs) & BIT(clk->gate_shift)
>>>>>>>>> ? 1 : 0;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static void pmc_clk_set_state(unsigned long offs, u32 shift, int
>>>>>>>>> state)
>>>>>>>>> +{
>>>>>>>>> +    u32 val;
>>>>>>>>> +
>>>>>>>>> +    val = tegra_pmc_readl(pmc, offs);
>>>>>>>>> +    val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
>>>>>>>>> +    tegra_pmc_writel(pmc, val, offs);
>>>>>>>>> +    pmc_clk_fence_udelay(offs);
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static int pmc_clk_enable(struct clk_hw *hw)
>>>>>>>>> +{
>>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>>> +
>>>>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 1);
>>>>>>>>> +
>>>>>>>>> +    return 0;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static void pmc_clk_disable(struct clk_hw *hw)
>>>>>>>>> +{
>>>>>>>>> +    struct pmc_clk *clk = to_pmc_clk(hw);
>>>>>>>>> +
>>>>>>>>> +    pmc_clk_set_state(clk->offs, clk->gate_shift, 0);
>>>>>>>>> +}
>>>>>>>>> +
>>>>>>>>> +static const struct clk_ops pmc_clk_ops = {
>>>>>>>>> +    .get_parent = pmc_clk_mux_get_parent,
>>>>>>>>> +    .set_parent = pmc_clk_mux_set_parent,
>>>>>>>>> +    .determine_rate = __clk_mux_determine_rate,
>>>>>>>>> +    .is_enabled = pmc_clk_is_enabled,
>>>>>>>>> +    .enable = pmc_clk_enable,
>>>>>>>>> +    .disable = pmc_clk_disable,
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +static struct clk *
>>>>>>>>> +tegra_pmc_clk_out_register(const struct pmc_clk_init_data *data,
>>>>>>>>> +               unsigned long offset)
>>>>>>>>> +{
>>>>>>>>> +    struct clk_init_data init;
>>>>>>>>> +    struct pmc_clk *pmc_clk;
>>>>>>>>> +
>>>>>>>>> +    pmc_clk = kzalloc(sizeof(*pmc_clk), GFP_KERNEL);
>>>>>>>>> +    if (!pmc_clk)
>>>>>>>>> +        return ERR_PTR(-ENOMEM);
>>>>>>>>> +
>>>>>>>>> +    init.name = data->name;
>>>>>>>>> +    init.ops = &pmc_clk_ops;
>>>>>>>>> +    init.parent_names = data->parents;
>>>>>>>>> +    init.num_parents = data->num_parents;
>>>>>>>>> +    init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
>>>>>>>>> +             CLK_SET_PARENT_GATE;
>>>>>>>>> +
>>>>>>>>> +    pmc_clk->hw.init = &init;
>>>>>>>>> +    pmc_clk->offs = offset;
>>>>>>>>> +    pmc_clk->mux_mask = 3;
>>>>>>>> If mux_mask is a constant value, perhaps will be better to
>>>>>>>> replace the
>>>>>>>> variable with a literal?
>>>>>>>>
>>>>>>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>>>>>> Maybe even:
>>>>>>>
>>>>>>> #define PMC_CLK_OUT_MUX_MASK(c)    GENMASK(c->shift + 1, c->shift)
>>>>> MUX Mask is used only here for PMC clock out and is same for all
>>>>> clk_out mux so will use
>>>>>
>>>>> #define PMC_CLK_OUT_MUX_MASK    GENMASK(1, 0)
>>>>>
>>>>>> I want to point out that may be a separated gate/mux shifts is a fine
>>>>>> variant, you should try and see whether another variants produce more
>>>>>> concise result.
>>>>>>
>>>>>> [snip]
>>>> We can do mux_shift as gate_shift + 4 and that restricts this clk
>>>> register only for clk1/2/3 as well and there are no other clocks in pmc
>>>> anyway.
>>>>
>>>> How about using bit shift define for CLK1, CLK2, and CLK3?
>>>>
>>>> .mux_shift = PMC_CLK1_SRC_SEL_SHIFT,
>>>>
>>>> .gate_shift = PMC_CLK1_FORCE_EN_SHIFT,
>>>>
>>>>
>>> I think that just renaming ".gate_shift" -> ".force_en_shift" should be
>>> good enough.
>> You meant to assign bit position directly instead of defines like what I
>> have now in v4 and use force_en_shift instead of gate_shift?
> Yes

^ permalink raw reply	[flat|nested] 54+ messages in thread

end of thread, other threads:[~2019-12-20 19:06 UTC | newest]

Thread overview: 54+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-17 20:03 [PATCH v4 00/19] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
2019-12-17 20:03 ` [PATCH v4 01/19] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks Sowjanya Komatineni
2019-12-18 21:19   ` Rob Herring
2019-12-17 20:03 ` [PATCH v4 02/19] clk: tegra: Change CLK_M_DIV clocks " Sowjanya Komatineni
2019-12-17 20:03 ` [PATCH v4 03/19] clk: tegra: Fix Tegra PMC clock out parents Sowjanya Komatineni
2019-12-17 20:03 ` [PATCH v4 04/19] dt-bindings: tegra: Convert Tegra PMC bindings to YAML Sowjanya Komatineni
2019-12-18 21:29   ` Rob Herring
2019-12-18 22:31     ` Sowjanya Komatineni
2019-12-17 20:03 ` [PATCH v4 05/19] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings Sowjanya Komatineni
2019-12-18  7:56   ` Dmitry Osipenko
2019-12-17 20:03 ` [PATCH v4 06/19] soc: tegra: Add Tegra PMC clock registrations into PMC driver Sowjanya Komatineni
2019-12-18  8:30   ` Dmitry Osipenko
2019-12-18  8:35     ` Dmitry Osipenko
2019-12-18 15:46       ` Sowjanya Komatineni
2019-12-18 15:50         ` Sowjanya Komatineni
2019-12-18 16:52           ` Dmitry Osipenko
2019-12-18 17:00             ` Sowjanya Komatineni
2019-12-18 16:48         ` Dmitry Osipenko
2019-12-18 21:44       ` Dmitry Osipenko
2019-12-19  0:41         ` Sowjanya Komatineni
2019-12-20  1:21           ` Sowjanya Komatineni
2019-12-20  1:39             ` Dmitry Osipenko
2019-12-20  4:13               ` Sowjanya Komatineni
2019-12-20  4:34                 ` Dmitry Osipenko
2019-12-20 19:06                   ` Sowjanya Komatineni
2019-12-17 20:03 ` [PATCH v4 07/19] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock Sowjanya Komatineni
2019-12-18 21:30   ` Rob Herring
2019-12-17 20:03 ` [PATCH v4 08/19] soc: tegra: Add support for " Sowjanya Komatineni
2019-12-18  5:08   ` Dmitry Osipenko
2019-12-17 20:03 ` [PATCH v4 09/19] clk: tegra: Remove tegra_pmc_clk_init along with clk ids Sowjanya Komatineni
2019-12-17 20:03 ` [PATCH v4 10/19] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings Sowjanya Komatineni
2019-12-18 21:32   ` Rob Herring
2019-12-17 20:03 ` [PATCH v4 11/19] ASoC: tegra: Use device managed resource APIs to get the clock Sowjanya Komatineni
2019-12-17 20:03 ` [PATCH v4 12/19] ASoC: tegra: Add initial parent configuration for audio mclk Sowjanya Komatineni
2019-12-17 20:04 ` [PATCH v4 13/19] ASoC: tegra: Add fallback implementation " Sowjanya Komatineni
2019-12-18  6:59   ` Dmitry Osipenko
2019-12-18  7:01     ` Dmitry Osipenko
2019-12-18  7:14       ` Sowjanya Komatineni
2019-12-18  7:22         ` Dmitry Osipenko
2019-12-18  7:31           ` Dmitry Osipenko
2019-12-18 15:43             ` Sowjanya Komatineni
2019-12-18 16:29               ` Dmitry Osipenko
2019-12-18 16:32                 ` Sowjanya Komatineni
2019-12-18 16:34                   ` Dmitry Osipenko
2019-12-17 20:04 ` [PATCH v4 14/19] clk: tegra: Remove audio related clock enables from clocks init_table Sowjanya Komatineni
2019-12-17 20:04 ` [PATCH v4 15/19] ARM: dts: tegra: Add clock-cells property to pmc Sowjanya Komatineni
2019-12-18 21:36   ` Dmitry Osipenko
2019-12-17 20:04 ` [PATCH v4 16/19] arm64: tegra: Add clock-cells property to Tegra PMC node Sowjanya Komatineni
2019-12-17 20:04 ` [PATCH v4 17/19] ARM: tegra: Update sound node clocks in device tree Sowjanya Komatineni
2019-12-18  6:39   ` Dmitry Osipenko
2019-12-18  7:47   ` Dmitry Osipenko
2019-12-17 20:04 ` [PATCH v4 18/19] arm64: tegra: smaug: Change clk_out_2 provider to pmc Sowjanya Komatineni
2019-12-17 20:04 ` [PATCH v4 19/19] ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car " Sowjanya Komatineni
2019-12-18 21:32   ` Rob Herring

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