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Tue, 14 Jan 2020 03:18:02 +0000 From: Peng Fan To: "sboyd@kernel.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "festevam@gmail.com" , Abel Vesa , Leonard Crestez CC: "kernel@pengutronix.de" , dl-linux-imx , Aisheng Dong , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anson Huang , Jacky Bai , "l.stach@pengutronix.de" , Peng Fan Subject: [PATCH 4/4] clk: imx: imx8mp: fix a53 cpu clock Thread-Topic: [PATCH 4/4] clk: imx: imx8mp: fix a53 cpu clock Thread-Index: AQHVyok9IoaFwrOhrEqVCCN442+qiA== Date: Tue, 14 Jan 2020 03:18:07 +0000 Message-ID: <1578971599-4277-5-git-send-email-peng.fan@nxp.com> References: <1578971599-4277-1-git-send-email-peng.fan@nxp.com> In-Reply-To: <1578971599-4277-1-git-send-email-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR0302CA0002.apcprd03.prod.outlook.com (2603:1096:202::12) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; 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x-microsoft-antispam-message-info: 1oiiEx4ZE0C60d2XVURyXMLquF4wCtdhcgGM7GdeTrvVUJEnDIawvNSlKhsvg/PKEozbNutlY2TyX81Vr7F7twfZMusx/aly6ZWTnkrg75MOeL3TomgtQJFxq+goyqCCEw3LmYgENUPEfwVAMc0I3tNgWqQKq8P+uy7xwRMIK6kCav4b3mYmavY11nnIzoMAp6lJVcrc946IB8osXjj0Klc9FLxF+TMu4X4XtFi77VmRHvVuN1X4FrjCCp/bw8ST14Vjw2mXjgbKGy5eMeGIYgxnOq/YxP1vIoOCg+KVI6U69UALNyZIrV9pjKOlEEJakeoeefvYUbpTB0hB8MKZ1xq7TpUJRzD36HQXIDrM7wWuisfi9QSYVB9Q7aLHAPa/O3mdAu3c9PpPG5OHkgaBeMaZEUkreQGCwFBQIPc/FAY59IeA3FPlhYLZue2Ag1JJPVL8OSs5sl2S7Uh7hMb7EWf36uApM1UiaQGA8JDxirm5NqcVMPU9RpCInLaHG72klzBIvxNxAqSS7yAs34tEOQ== Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7b76f586-45dd-47c4-1ed5-08d798a06005 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Jan 2020 03:18:07.1940 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: QQabR/ShQja2PVMRw/hagyBD9lheEiBYpBSt0wczbPqNoWizP58Tw5oFuMy+Y4yt7shvJaMTfQyasX6LX61Xzg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4402 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clk Reviewed-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mp.c | 16 ++++++++++++---- include/dt-bindings/clock/imx8mp-clock.h | 3 ++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index f6c120cca0d4..8a73aef845bb 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -34,6 +34,8 @@ static const char * const imx8mp_a53_sels[] =3D {"osc_24m= ", "arm_pll_out", "sys_pl "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; =20 +static const char * const imx8mp_a53_core_sels[] =3D {"arm_a53_div", "arm_= pll_out", }; + static const char * const imx8mp_m7_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_250m", "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; @@ -553,6 +555,9 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) hws[IMX8MP_CLK_HSIO_AXI_DIV] =3D imx_clk_hw_divider2("hsio_axi_div", "hsi= o_axi_cg", ccm_base + 0x8380, 0, 3); hws[IMX8MP_CLK_MEDIA_ISP_DIV] =3D imx_clk_hw_divider2("media_isp_div", "m= edia_isp_cg", ccm_base + 0x8400, 0, 3); =20 + /* CORE SEL */ + hws[IMX8MP_CLK_A53_CORE] =3D imx_clk_hw_mux2_flags("arm_a53_core", base += 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels), CLK= _IS_CRITICAL); + hws[IMX8MP_CLK_MAIN_AXI] =3D imx8m_clk_hw_composite_critical("main_axi", = imx8mp_main_axi_sels, ccm_base + 0x8800); hws[IMX8MP_CLK_ENET_AXI] =3D imx8m_clk_hw_composite("enet_axi", imx8mp_en= et_axi_sels, ccm_base + 0x8880); hws[IMX8MP_CLK_NAND_USDHC_BUS] =3D imx8m_clk_hw_composite_critical("nand_= usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900); @@ -722,11 +727,14 @@ static int imx8mp_clocks_probe(struct platform_device= *pdev) hws[IMX8MP_CLK_VPU_ROOT] =3D imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", = ccm_base + 0x4630, 0); hws[IMX8MP_CLK_AUDIO_ROOT] =3D imx_clk_hw_gate4("audio_root_clk", "ipg_ro= ot", ccm_base + 0x4650, 0); =20 - hws[IMX8MP_CLK_ARM] =3D imx_clk_hw_cpu("arm", "arm_a53_div", - hws[IMX8MP_CLK_A53_DIV]->clk, - hws[IMX8MP_CLK_A53_SRC]->clk, + clk_hw_set_parent(hws[IMX8MP_CLK_A53_SRC], clks[IMX8MP_SYS_PLL1_800M]); + clk_hw_set_parent(hws[IMX8MP_CLK_A53_CORE], clks[IMX8MP_ARM_PLL_OUT]); + + hws[IMX8MP_CLK_ARM] =3D imx_clk_hw_cpu("arm", "arm_a53_core", + hws[IMX8MP_CLK_A53_CORE]->clk, + hws[IMX8MP_CLK_A53_CORE]->clk, hws[IMX8MP_ARM_PLL_OUT]->clk, - hws[IMX8MP_SYS_PLL1_800M]->clk); + hws[IMX8MP_CLK_A53_DIV]->clk); =20 imx_check_clk_hws(hws, IMX8MP_CLK_END); =20 diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings= /clock/imx8mp-clock.h index 2fab63186bca..c92d1f4117eb 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -294,7 +294,8 @@ #define IMX8MP_CLK_DRAM_ALT_ROOT 285 #define IMX8MP_CLK_DRAM_CORE 286 #define IMX8MP_CLK_ARM 287 +#define IMX8MP_CLK_A53_CORE 288 =20 -#define IMX8MP_CLK_END 288 +#define IMX8MP_CLK_END 289 =20 #endif --=20 2.16.4