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* [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation
@ 2020-01-14 16:07 Dinh Nguyen
  2020-01-14 16:07 ` [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing Dinh Nguyen
  2020-02-12 23:42 ` [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation Stephen Boyd
  0 siblings, 2 replies; 7+ messages in thread
From: Dinh Nguyen @ 2020-01-14 16:07 UTC (permalink / raw)
  To: sboyd; +Cc: dinguyen, mturquette, linux-clk

do_div() macro to perform u64 division and guards against overflow if
the result is too large for the unsigned long return type.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 drivers/clk/socfpga/clk-pll-s10.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index 4705eb544f01..8d7b1d0c4664 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -39,7 +39,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
 	/* read VCO1 reg for numerator and denominator */
 	reg = readl(socfpgaclk->hw.reg);
 	refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
-	vco_freq = (unsigned long long)parent_rate / refdiv;
+
+	vco_freq = parent_rate;
+	do_div(vco_freq, refdiv);
 
 	/* Read mdiv and fdiv from the fdbck register */
 	reg = readl(socfpgaclk->hw.reg + 0x4);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing
  2020-01-14 16:07 [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation Dinh Nguyen
@ 2020-01-14 16:07 ` Dinh Nguyen
  2020-02-04 15:29   ` Dinh Nguyen
  2020-02-12 23:42   ` Stephen Boyd
  2020-02-12 23:42 ` [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation Stephen Boyd
  1 sibling, 2 replies; 7+ messages in thread
From: Dinh Nguyen @ 2020-01-14 16:07 UTC (permalink / raw)
  To: sboyd; +Cc: dinguyen, mturquette, linux-clk

Just pass the clock pointer structure to the various register functions.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 drivers/clk/socfpga/clk-gate-s10.c   | 40 +++++++++++---------------
 drivers/clk/socfpga/clk-periph-s10.c | 42 ++++++++++++++--------------
 drivers/clk/socfpga/clk-pll-s10.c    | 13 +++++----
 drivers/clk/socfpga/clk-s10.c        | 29 +++----------------
 drivers/clk/socfpga/stratix10-clk.h  | 25 ++++++-----------
 5 files changed, 57 insertions(+), 92 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
index 54a464fa63e0..8be4722f6064 100644
--- a/drivers/clk/socfpga/clk-gate-s10.c
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -65,54 +65,49 @@ static const struct clk_ops dbgclk_ops = {
 	.get_parent = socfpga_gate_get_parent,
 };
 
-struct clk *s10_register_gate(const char *name, const char *parent_name,
-			      const char * const *parent_names,
-			      u8 num_parents, unsigned long flags,
-			      void __iomem *regbase, unsigned long gate_reg,
-			      unsigned long gate_idx, unsigned long div_reg,
-			      unsigned long div_offset, u8 div_width,
-			      unsigned long bypass_reg, u8 bypass_shift,
-			      u8 fixed_div)
+struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
 {
 	struct clk *clk;
 	struct socfpga_gate_clk *socfpga_clk;
 	struct clk_init_data init;
+	const char * const *parent_names = clks->parent_names;
+	const char *parent_name = clks->parent_name;
 
 	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
 	if (!socfpga_clk)
 		return NULL;
 
-	socfpga_clk->hw.reg = regbase + gate_reg;
-	socfpga_clk->hw.bit_idx = gate_idx;
+	socfpga_clk->hw.reg = regbase + clks->gate_reg;
+	socfpga_clk->hw.bit_idx = clks->gate_idx;
 
 	gateclk_ops.enable = clk_gate_ops.enable;
 	gateclk_ops.disable = clk_gate_ops.disable;
 
-	socfpga_clk->fixed_div = fixed_div;
+	socfpga_clk->fixed_div = clks->fixed_div;
 
-	if (div_reg)
-		socfpga_clk->div_reg = regbase + div_reg;
+	if (clks->div_reg)
+		socfpga_clk->div_reg = regbase + clks->div_reg;
 	else
 		socfpga_clk->div_reg = NULL;
 
-	socfpga_clk->width = div_width;
-	socfpga_clk->shift = div_offset;
+	socfpga_clk->width = clks->div_width;
+	socfpga_clk->shift = clks->div_offset;
 
-	if (bypass_reg)
-		socfpga_clk->bypass_reg = regbase + bypass_reg;
+	if (clks->bypass_reg)
+		socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
 	else
 		socfpga_clk->bypass_reg = NULL;
-	socfpga_clk->bypass_shift = bypass_shift;
+	socfpga_clk->bypass_shift = clks->bypass_shift;
 
-	if (streq(name, "cs_pdbg_clk"))
+	if (streq(clks->name, "cs_pdbg_clk"))
 		init.ops = &dbgclk_ops;
 	else
 		init.ops = &gateclk_ops;
 
-	init.name = name;
-	init.flags = flags;
+	init.name = clks->name;
+	init.flags = clks->flags;
 
-	init.num_parents = num_parents;
+	init.num_parents = clks->num_parents;
 	init.parent_names = parent_names ? parent_names : &parent_name;
 	socfpga_clk->hw.hw.init = &init;
 
@@ -121,6 +116,5 @@ struct clk *s10_register_gate(const char *name, const char *parent_name,
 		kfree(socfpga_clk);
 		return NULL;
 	}
-
 	return clk;
 }
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
index 1a191eeeebba..dd6d4056e9de 100644
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -73,26 +73,27 @@ static const struct clk_ops peri_cnt_clk_ops = {
 	.get_parent = clk_periclk_get_parent,
 };
 
-struct clk *s10_register_periph(const char *name, const char *parent_name,
-				const char * const *parent_names,
-				u8 num_parents, unsigned long flags,
-				void __iomem *reg, unsigned long offset)
+struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
+				void __iomem *reg)
 {
 	struct clk *clk;
 	struct socfpga_periph_clk *periph_clk;
 	struct clk_init_data init;
+	const char *name = clks->name;
+	const char *parent_name = clks->parent_name;
+	const char * const *parent_names = clks->parent_names;
 
 	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
 	if (WARN_ON(!periph_clk))
 		return NULL;
 
-	periph_clk->hw.reg = reg + offset;
+	periph_clk->hw.reg = reg + clks->offset;
 
 	init.name = name;
 	init.ops = &peri_c_clk_ops;
-	init.flags = flags;
+	init.flags = clks->flags;
 
-	init.num_parents = num_parents;
+	init.num_parents = clks->num_parents;
 	init.parent_names = parent_names ? parent_names : &parent_name;
 
 	periph_clk->hw.hw.init = &init;
@@ -105,38 +106,37 @@ struct clk *s10_register_periph(const char *name, const char *parent_name,
 	return clk;
 }
 
-struct clk *s10_register_cnt_periph(const char *name, const char *parent_name,
-				    const char * const *parent_names,
-				    u8 num_parents, unsigned long flags,
-				    void __iomem *regbase, unsigned long offset,
-				    u8 fixed_divider, unsigned long bypass_reg,
-				    unsigned long bypass_shift)
+struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
+				    void __iomem *regbase)
 {
 	struct clk *clk;
 	struct socfpga_periph_clk *periph_clk;
 	struct clk_init_data init;
+	const char *name = clks->name;
+	const char *parent_name = clks->parent_name;
+	const char * const *parent_names = clks->parent_names;
 
 	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
 	if (WARN_ON(!periph_clk))
 		return NULL;
 
-	if (offset)
-		periph_clk->hw.reg = regbase + offset;
+	if (clks->offset)
+		periph_clk->hw.reg = regbase + clks->offset;
 	else
 		periph_clk->hw.reg = NULL;
 
-	if (bypass_reg)
-		periph_clk->bypass_reg = regbase + bypass_reg;
+	if (clks->bypass_reg)
+		periph_clk->bypass_reg = regbase + clks->bypass_reg;
 	else
 		periph_clk->bypass_reg = NULL;
-	periph_clk->bypass_shift = bypass_shift;
-	periph_clk->fixed_div = fixed_divider;
+	periph_clk->bypass_shift = clks->bypass_shift;
+	periph_clk->fixed_div = clks->fixed_divider;
 
 	init.name = name;
 	init.ops = &peri_cnt_clk_ops;
-	init.flags = flags;
+	init.flags = clks->flags;
 
-	init.num_parents = num_parents;
+	init.num_parents = clks->num_parents;
 	init.parent_names = parent_names ? parent_names : &parent_name;
 
 	periph_clk->hw.hw.init = &init;
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index 8d7b1d0c4664..a301bb22f36c 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -110,19 +110,20 @@ static struct clk_ops clk_boot_ops = {
 	.prepare = clk_pll_prepare,
 };
 
-struct clk *s10_register_pll(const char *name, const char * const *parent_names,
-				    u8 num_parents, unsigned long flags,
-				    void __iomem *reg, unsigned long offset)
+struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
+			     void __iomem *reg)
 {
 	struct clk *clk;
 	struct socfpga_pll *pll_clk;
 	struct clk_init_data init;
+	const char *name = clks->name;
+	const char * const *parent_names = clks->parent_names;
 
 	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
 	if (WARN_ON(!pll_clk))
 		return NULL;
 
-	pll_clk->hw.reg = reg + offset;
+	pll_clk->hw.reg = reg + clks->offset;
 
 	if (streq(name, SOCFPGA_BOOT_CLK))
 		init.ops = &clk_boot_ops;
@@ -130,9 +131,9 @@ struct clk *s10_register_pll(const char *name, const char * const *parent_names,
 		init.ops = &clk_pll_ops;
 
 	init.name = name;
-	init.flags = flags;
+	init.flags = clks->flags;
 
-	init.num_parents = num_parents;
+	init.num_parents = clks->num_parents;
 	init.parent_names = parent_names;
 	pll_clk->hw.hw.init = &init;
 
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index 993f3a73c71e..dea7c6c7d269 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -177,9 +177,7 @@ static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
 	int i;
 
 	for (i = 0; i < nums; i++) {
-		clk = s10_register_periph(clks[i].name, clks[i].parent_name,
-					  clks[i].parent_names, clks[i].num_parents,
-					  clks[i].flags, base, clks[i].offset);
+		clk = s10_register_periph(&clks[i], base);
 		if (IS_ERR(clk)) {
 			pr_err("%s: failed to register clock %s\n",
 			       __func__, clks[i].name);
@@ -198,14 +196,7 @@ static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *cl
 	int i;
 
 	for (i = 0; i < nums; i++) {
-		clk = s10_register_cnt_periph(clks[i].name, clks[i].parent_name,
-					      clks[i].parent_names,
-					      clks[i].num_parents,
-					      clks[i].flags, base,
-					      clks[i].offset,
-					      clks[i].fixed_divider,
-					      clks[i].bypass_reg,
-					      clks[i].bypass_shift);
+		clk = s10_register_cnt_periph(&clks[i], base);
 		if (IS_ERR(clk)) {
 			pr_err("%s: failed to register clock %s\n",
 			       __func__, clks[i].name);
@@ -225,16 +216,7 @@ static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
 	int i;
 
 	for (i = 0; i < nums; i++) {
-		clk = s10_register_gate(clks[i].name, clks[i].parent_name,
-					clks[i].parent_names,
-					clks[i].num_parents,
-					clks[i].flags, base,
-					clks[i].gate_reg,
-					clks[i].gate_idx, clks[i].div_reg,
-					clks[i].div_offset, clks[i].div_width,
-					clks[i].bypass_reg,
-					clks[i].bypass_shift,
-					clks[i].fixed_div);
+		clk = s10_register_gate(&clks[i], base);
 		if (IS_ERR(clk)) {
 			pr_err("%s: failed to register clock %s\n",
 			       __func__, clks[i].name);
@@ -254,10 +236,7 @@ static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
 	int i;
 
 	for (i = 0; i < nums; i++) {
-		clk = s10_register_pll(clks[i].name, clks[i].parent_names,
-				    clks[i].num_parents,
-				    clks[i].flags, base,
-				    clks[i].offset);
+		clk = s10_register_pll(&clks[i], base);
 		if (IS_ERR(clk)) {
 			pr_err("%s: failed to register clock %s\n",
 			       __func__, clks[i].name);
diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
index e8e121907952..fcabef42249c 100644
--- a/drivers/clk/socfpga/stratix10-clk.h
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -60,21 +60,12 @@ struct stratix10_gate_clock {
 	u8			fixed_div;
 };
 
-struct clk *s10_register_pll(const char *, const char *const *, u8,
-			     unsigned long, void __iomem *, unsigned long);
-
-struct clk *s10_register_periph(const char *, const char *,
-				const char * const *, u8, unsigned long,
-				void __iomem *, unsigned long);
-struct clk *s10_register_cnt_periph(const char *, const char *,
-				    const char * const *, u8,
-				    unsigned long, void __iomem *,
-				    unsigned long, u8, unsigned long,
-				    unsigned long);
-struct clk *s10_register_gate(const char *, const char *,
-			      const char * const *, u8,
-			      unsigned long, void __iomem *,
-			      unsigned long, unsigned long,
-			      unsigned long, unsigned long, u8,
-			      unsigned long, u8, u8);
+struct clk *s10_register_pll(const struct stratix10_pll_clock *,
+			     void __iomem *);
+struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
+				void __iomem *);
+struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
+				    void __iomem *);
+struct clk *s10_register_gate(const struct stratix10_gate_clock *,
+			      void __iomem *);
 #endif	/* __STRATIX10_CLK_H */
-- 
2.17.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing
  2020-01-14 16:07 ` [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing Dinh Nguyen
@ 2020-02-04 15:29   ` Dinh Nguyen
  2020-02-12 23:42     ` Stephen Boyd
  2020-02-12 23:42   ` Stephen Boyd
  1 sibling, 1 reply; 7+ messages in thread
From: Dinh Nguyen @ 2020-02-04 15:29 UTC (permalink / raw)
  To: sboyd; +Cc: mturquette, linux-clk

Ping? Hopefully, there aren't any issues with these patches?

On 1/14/20 10:07 AM, Dinh Nguyen wrote:
> Just pass the clock pointer structure to the various register functions.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
>  drivers/clk/socfpga/clk-gate-s10.c   | 40 +++++++++++---------------
>  drivers/clk/socfpga/clk-periph-s10.c | 42 ++++++++++++++--------------
>  drivers/clk/socfpga/clk-pll-s10.c    | 13 +++++----
>  drivers/clk/socfpga/clk-s10.c        | 29 +++----------------
>  drivers/clk/socfpga/stratix10-clk.h  | 25 ++++++-----------
>  5 files changed, 57 insertions(+), 92 deletions(-)
> 
> diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation
  2020-01-14 16:07 [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation Dinh Nguyen
  2020-01-14 16:07 ` [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing Dinh Nguyen
@ 2020-02-12 23:42 ` Stephen Boyd
  1 sibling, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-02-12 23:42 UTC (permalink / raw)
  To: Dinh Nguyen; +Cc: dinguyen, mturquette, linux-clk

Quoting Dinh Nguyen (2020-01-14 08:07:25)
> do_div() macro to perform u64 division and guards against overflow if
> the result is too large for the unsigned long return type.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---

Applied to clk-next

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing
  2020-01-14 16:07 ` [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing Dinh Nguyen
  2020-02-04 15:29   ` Dinh Nguyen
@ 2020-02-12 23:42   ` Stephen Boyd
  1 sibling, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-02-12 23:42 UTC (permalink / raw)
  To: Dinh Nguyen; +Cc: dinguyen, mturquette, linux-clk

Quoting Dinh Nguyen (2020-01-14 08:07:26)
> Just pass the clock pointer structure to the various register functions.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---

Applied to clk-next

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing
  2020-02-04 15:29   ` Dinh Nguyen
@ 2020-02-12 23:42     ` Stephen Boyd
  2020-02-13 15:04       ` Dinh Nguyen
  0 siblings, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2020-02-12 23:42 UTC (permalink / raw)
  To: Dinh Nguyen; +Cc: mturquette, linux-clk

Quoting Dinh Nguyen (2020-02-04 07:29:44)
> Ping? Hopefully, there aren't any issues with these patches?

Was there a cover letter? Will there be more patches? Seems like it's
mostly code shuffling in preparation for something else.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing
  2020-02-12 23:42     ` Stephen Boyd
@ 2020-02-13 15:04       ` Dinh Nguyen
  0 siblings, 0 replies; 7+ messages in thread
From: Dinh Nguyen @ 2020-02-13 15:04 UTC (permalink / raw)
  To: Stephen Boyd; +Cc: mturquette, linux-clk



On 2/12/20 5:42 PM, Stephen Boyd wrote:
> Quoting Dinh Nguyen (2020-02-04 07:29:44)
>> Ping? Hopefully, there aren't any issues with these patches?
> 
> Was there a cover letter? Will there be more patches? Seems like it's
> mostly code shuffling in preparation for something else.
> 

Sorry about that. There was no cover letter. These 2 patches are a
result of comments received from my v1 submission of a clock driver for
the Agilex platform. Figure it would be easier to split out the patches
rather than submitting it together in the Agilex series.

Thanks,
Dinh

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, back to index

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-14 16:07 [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation Dinh Nguyen
2020-01-14 16:07 ` [PATCH 2/2] clk: socfpga: stratix10: simplify paramter passing Dinh Nguyen
2020-02-04 15:29   ` Dinh Nguyen
2020-02-12 23:42     ` Stephen Boyd
2020-02-13 15:04       ` Dinh Nguyen
2020-02-12 23:42   ` Stephen Boyd
2020-02-12 23:42 ` [PATCH 1/2] clk: stratix10: use do_div() for 64-bit calculation Stephen Boyd

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