From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, tglx@linutronix.de,
ralf@linux-mips.org, paulburton@kernel.org,
jiaxun.yang@flygoat.com, chenhc@lemote.com, sboyd@kernel.org,
mturquette@baylibre.com, mark.rutland@arm.com,
robh+dt@kernel.org, daniel.lezcano@linaro.org,
paul@crapouillou.net, geert+renesas@glider.be, krzk@kernel.org,
ebiederm@xmission.com, miquel.raynal@bootlin.com,
keescook@chromium.org, sernia.zhou@foxmail.com,
zhenwenjin@gmail.com, dongsheng.qiu@ingenic.com
Subject: [PATCH v6 3/7] MIPS: CI20: Modify DTS to support high resolution timer for SMP.
Date: Fri, 21 Feb 2020 00:24:45 +0800 [thread overview]
Message-ID: <1582215889-113034-5-git-send-email-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com>
Modify DTS, change tcu channel from 2 to 3, channel #0 and #1 for
per core local timer, #2 for clocksource.
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
No change.
v2->v3:
No change.
v3->v4:
Rebase on top of kernel 5.6-rc1.
v4->v5:
Move [5/6] in v4 to this patch, to ensure that we can
git-bisect without ending up with a broken kernel.
v5->v6:
No change.
arch/mips/boot/dts/ingenic/ci20.dts | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 37b9316..29437aa 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -455,7 +455,14 @@
};
&tcu {
- /* 3 MHz for the system timer and clocksource */
- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
- assigned-clock-rates = <3000000>, <3000000>;
+ /* 3 MHz for the system timers, 750kHz for the clocksource */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>;
+ assigned-clock-rates = <3000000>, <3000000>, <750000>;
+
+ /*
+ * Use channel #0 and #1 for the per core system timer,
+ * and use channel #2 for the clocksource.
+ */
+ ingenic,pwm-channels-mask = <0xF8>;
};
--
2.7.4
next prev parent reply other threads:[~2020-02-20 16:25 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-20 16:24 Introduce SMP support for CI20 (based on JZ4780) v6 周琰杰 (Zhou Yanjie)
2020-02-20 16:24 ` [PATCH v6 0/7] Introduce SMP support for CI20 (based on JZ4780) 周琰杰 (Zhou Yanjie)
2020-02-20 16:24 ` [PATCH v6 1/7] clk: JZ4780: Add function for enable the second core 周琰杰 (Zhou Yanjie)
2020-03-21 0:02 ` Stephen Boyd
2020-02-20 16:24 ` [PATCH v6 2/7] MIPS: JZ4780: Introduce SMP support 周琰杰 (Zhou Yanjie)
2020-02-20 18:27 ` Paul Cercueil
2020-02-27 16:17 ` Zhou Yanjie
2020-02-20 16:24 ` 周琰杰 (Zhou Yanjie) [this message]
2020-02-20 16:24 ` [PATCH v6 4/7] clocksource: Ingenic: Add high resolution timer support for SMP 周琰杰 (Zhou Yanjie)
2020-02-20 18:33 ` Paul Cercueil
2020-02-27 16:18 ` Zhou Yanjie
2020-02-20 16:24 ` [PATCH v6 5/7] dt-bindings: MIPS: Document Ingenic SoCs binding 周琰杰 (Zhou Yanjie)
2020-02-26 16:29 ` Rob Herring
2020-02-27 13:48 ` Paul Cercueil
2020-02-27 17:44 ` Zhou Yanjie
2020-02-27 16:13 ` Zhou Yanjie
2020-02-20 16:24 ` [PATCH v6 6/7] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-02-20 16:24 ` [PATCH v6 7/7] MIPS: CI20: Update defconfig to support SMP 周琰杰 (Zhou Yanjie)
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