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Subject: Re: [PATCH v5 5/5] clk: qcom: Add modem clock controller driver for SC7180
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     David Brown <david.brown@linaro.org>,
        Rajendra Nayak <rnayak@codeaurora.org>,
        linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        Andy Gross <agross@kernel.org>, devicetree@vger.kernel.org,
        robh@kernel.org, robh+dt@kernel.org,
        Taniya Das <tdas@codeaurora.org>
To:     Michael Turquette <mturquette@baylibre.com>,
        Taniya Das <tdas@codeaurora.org>
Date:   Tue, 25 Feb 2020 16:28:56 -0800
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Quoting Taniya Das (2020-02-24 02:38:23)
> diff --git a/drivers/clk/qcom/mss-sc7180.c b/drivers/clk/qcom/mss-sc7180.c
> new file mode 100644
> index 0000000..993749e
> --- /dev/null
> +++ b/drivers/clk/qcom/mss-sc7180.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,mss-sc7180.h>
> +
> +#include "clk-regmap.h"
> +#include "clk-branch.h"
> +#include "common.h"
> +
> +static struct clk_branch mss_axi_nav_clk =3D {
> +       .halt_reg =3D 0x20bc,
> +       .halt_check =3D BRANCH_HALT,
> +       .clkr =3D {
> +               .enable_reg =3D 0x20bc,
> +               .enable_mask =3D BIT(0),
> +               .hw.init =3D &(struct clk_init_data){
> +                       .name =3D "mss_axi_nav_clk",
> +                       .parent_data =3D &(const struct clk_parent_data){
> +                               .fw_name =3D "gcc_mss_nav_axi_clk",

Drop _clk from here.

> +                       },
> +                       .num_parents =3D 1,
> +                       .ops =3D &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch mss_axi_crypto_clk =3D {
> +       .halt_reg =3D 0x20cc,
> +       .halt_check =3D BRANCH_HALT,
> +       .clkr =3D {
> +               .enable_reg =3D 0x20cc,
> +               .enable_mask =3D BIT(0),
> +               .hw.init =3D &(struct clk_init_data){
> +                       .name =3D "mss_axi_crypto_clk",
> +                       .parent_data =3D &(const struct clk_parent_data){
> +                               .fw_name =3D "gcc_mss_mfab_axis_clk",

And here, so that it matches the binding.

> +                       },
> +                       .num_parents =3D 1,
> +                       .ops =3D &clk_branch2_ops,
> +               },
> +       },
> +};
> +