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From: peng.fan@nxp.com
To: shawnguo@kernel.org, s.hauer@pengutronix.de,
	leonard.crestez@nxp.com, abel.vesa@nxp.com, aisheng.dong@nxp.com
Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
	Anson.Huang@nxp.com, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
Subject: [PATCH V3 08/10] clk: imx: add imx8m_clk_hw_composite_bus
Date: Thu,  7 May 2020 13:56:17 +0800	[thread overview]
Message-ID: <1588830979-11586-9-git-send-email-peng.fan@nxp.com> (raw)
In-Reply-To: <1588830979-11586-1-git-send-email-peng.fan@nxp.com>

From: Peng Fan <peng.fan@nxp.com>

Introduce imx8m_clk_hw_composite_bus api for bus clk root slice usage.
Because the mux switch sequence issue, we could not reuse Peripheral
Clock Slice code, need use composite specific mux operation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-8m.c | 5 +++++
 drivers/clk/imx/clk.h              | 7 +++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 8fa60f22d377..3ba6838ce3d4 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -205,6 +205,11 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 		div->width = PCG_CORE_DIV_WIDTH;
 		divider_ops = &clk_divider_ops;
 		mux_ops = &imx8m_clk_composite_mux_ops;
+	} else if (composite_flags & IMX_COMPOSITE_BUS) {
+		div->shift = PCG_PREDIV_SHIFT;
+		div->width = PCG_PREDIV_WIDTH;
+		divider_ops = &imx8m_clk_composite_divider_ops;
+		mux_ops = &imx8m_clk_composite_mux_ops;
 	} else {
 		div->shift = PCG_PREDIV_SHIFT;
 		div->width = PCG_PREDIV_WIDTH;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index b91b1b18a4a2..16adbc34e05f 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -527,6 +527,7 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
 		struct clk *step);
 
 #define IMX_COMPOSITE_CORE	BIT(0)
+#define IMX_COMPOSITE_BUS	BIT(1)
 
 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 					    const char * const *parent_names,
@@ -535,6 +536,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 					    u32 composite_flags,
 					    unsigned long flags);
 
+#define imx8m_clk_hw_composite_bus(name, parent_names, reg)	\
+	imx8m_clk_hw_composite_flags(name, parent_names, \
+			ARRAY_SIZE(parent_names), reg, \
+			IMX_COMPOSITE_BUS, \
+			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
 #define imx8m_clk_hw_composite_core(name, parent_names, reg)	\
 	imx8m_clk_hw_composite_flags(name, parent_names, \
 			ARRAY_SIZE(parent_names), reg, \
-- 
2.16.4


  parent reply	other threads:[~2020-05-07  6:06 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-07  5:56 [PATCH V3 00/10] clk: imx: fixes and improve for i.MX8M peng.fan
2020-05-07  5:56 ` [PATCH V3 01/10] arm64: dts: imx8m: assign clocks for A53 peng.fan
2020-05-07  5:56 ` [PATCH V3 02/10] clk: imx8m: drop clk_hw_set_parent " peng.fan
2020-05-07  5:56 ` [PATCH V3 03/10] clk: imx: imx8mp: fix pll mux bit peng.fan
2020-05-07  5:56 ` [PATCH V3 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers peng.fan
2020-05-07  5:56 ` [PATCH V3 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code peng.fan
2020-05-07  5:56 ` [PATCH V3 06/10] clk: imx8m: migrate A53 clk root to use composite core peng.fan
2020-05-07  5:56 ` [PATCH V3 07/10] clk: imx: add mux ops for i.MX8M composite clk peng.fan
2020-05-07  5:56 ` peng.fan [this message]
2020-05-07  5:56 ` [PATCH V3 09/10] clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice peng.fan
2020-05-07  5:56 ` [PATCH V3 10/10] clk: imx8mp: mark memrepair clock as critical peng.fan
2020-05-07  6:59   ` Aisheng Dong
2020-05-07  7:59     ` Peng Fan
2020-05-07  6:58 ` [PATCH V3 00/10] clk: imx: fixes and improve for i.MX8M Aisheng Dong
2020-05-20  1:27 ` Shawn Guo

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