[PATCH 0/3] clk: zynqmp: Add firmware specific clock flags

[PATCH 0/3] clk: zynqmp: Add firmware specific clock flags

[Amit Sunil Dhamne]

This series adds supports for firmware specific flags. These include
- Common Flags
- Divider Flags
- Mux Flags

The intent is to remove firmware's dependency on CCF flag values by
having firmware specific flags with independent values.

Rajan Vaja (3):
  clk: zynqmp: Use firmware specific common clock flags
  clk: zynqmp: Use firmware specific divider clock flags
  clk: zynqmp: Use firmware specific mux clock flags

 drivers/clk/zynqmp/clk-mux-zynqmp.c | 14 ++++++++++++-
 drivers/clk/zynqmp/clk-zynqmp.h     | 39 +++++++++++++++++++++++++++++++++++++
 drivers/clk/zynqmp/clkc.c           | 25 ++++++++++++++++++++++--
 drivers/clk/zynqmp/divider.c        | 16 ++++++++++++++-
 4 files changed, 90 insertions(+), 4 deletions(-)

--
2.7.4

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[PATCH 1/3] clk: zynqmp: Use firmware specific common clock flags

[Amit Sunil Dhamne]

From: Rajan Vaja <rajan.vaja@xilinx.com>

Currently firmware passes CCF specific flags to ZynqMP clock driver.
So firmware needs to be updated if CCF flags are changed. The firmware
should have its own 'flag number space' that is distinct from the
common clk framework's 'flag number space'. So define and use ZynqMP
specific common clock flags instead of using CCF flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
---
 drivers/clk/zynqmp/clk-zynqmp.h | 22 ++++++++++++++++++++++
 drivers/clk/zynqmp/clkc.c       | 25 +++++++++++++++++++++++--
 2 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index 5beeb41..d8e580b 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -10,6 +10,28 @@

 #include <linux/firmware/xlnx-zynqmp.h>

+/* Common Flags */
+/* must be gated across rate change */
+#define ZYNQMP_CLK_SET_RATE_GATE       BIT(0)
+/* must be gated across re-parent */
+#define ZYNQMP_CLK_SET_PARENT_GATE     BIT(1)
+/* propagate rate change up one level */
+#define ZYNQMP_CLK_SET_RATE_PARENT     BIT(2)
+/* do not gate even if unused */
+#define ZYNQMP_CLK_IGNORE_UNUSED       BIT(3)
+/* do not use the cached clk rate */
+#define ZYNQMP_CLK_GET_RATE_NOCACHE    BIT(6)
+/* don't re-parent on rate change */
+#define ZYNQMP_CLK_SET_RATE_NO_REPARENT        BIT(7)
+/* do not use the cached clk accuracy */
+#define ZYNQMP_CLK_GET_ACCURACY_NOCACHE        BIT(8)
+/* recalc rates after notifications */
+#define ZYNQMP_CLK_RECALC_NEW_RATES    BIT(9)
+/* clock needs to run to set rate */
+#define ZYNQMP_CLK_SET_RATE_UNGATE     BIT(10)
+/* do not gate, ever */
+#define ZYNQMP_CLK_IS_CRITICAL         BIT(11)
+
 enum topology_type {
        TYPE_INVALID,
        TYPE_MUX,
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index db8d0d7..8663587 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -385,14 +385,35 @@ static int __zynqmp_clock_get_topology(struct clock_topology *topology,
 {
        int i;
        u32 type;
+       u32 flag;

        for (i = 0; i < ARRAY_SIZE(response->topology); i++) {
                type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]);
                if (type == TYPE_INVALID)
                        return END_OF_TOPOLOGY_NODE;
                topology[*nnodes].type = type;
-               topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS,
-                                                  response->topology[i]);
+               flag = FIELD_GET(CLK_TOPOLOGY_FLAGS, response->topology[i]);
+               topology[*nnodes].flag = 0;
+               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_SET_RATE_GATE) ?
+                                          CLK_SET_RATE_GATE : 0;
+               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_SET_RATE_PARENT) ?
+                                          CLK_SET_RATE_PARENT : 0;
+               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_IGNORE_UNUSED) ?
+                                          CLK_IGNORE_UNUSED : 0;
+               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_GET_RATE_NOCACHE) ?
+                                          CLK_GET_RATE_NOCACHE : 0;
+               topology[*nnodes].flag |= (flag &
+                                          ZYNQMP_CLK_SET_RATE_NO_REPARENT) ?
+                                          CLK_SET_RATE_NO_REPARENT : 0;
+               topology[*nnodes].flag |= (flag &
+                                          ZYNQMP_CLK_GET_ACCURACY_NOCACHE) ?
+                                          CLK_GET_ACCURACY_NOCACHE : 0;
+               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_RECALC_NEW_RATES) ?
+                                          CLK_RECALC_NEW_RATES : 0;
+               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_SET_RATE_UNGATE) ?
+                                          CLK_SET_RATE_UNGATE : 0;
+               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_IS_CRITICAL) ?
+                                          CLK_IS_CRITICAL : 0;
                topology[*nnodes].type_flag =
                                FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
                                          response->topology[i]);
--
2.7.4

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Re: [PATCH 1/3] clk: zynqmp: Use firmware specific common clock flags

[Michael Tretter]

On Mon, 29 Jun 2020 17:30:12 -0700, Amit Sunil Dhamne wrote:
> From: Rajan Vaja <rajan.vaja@xilinx.com>
> 
> Currently firmware passes CCF specific flags to ZynqMP clock driver.
> So firmware needs to be updated if CCF flags are changed. The firmware
> should have its own 'flag number space' that is distinct from the
> common clk framework's 'flag number space'. So define and use ZynqMP
> specific common clock flags instead of using CCF flags.
> 
> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
> ---
>  drivers/clk/zynqmp/clk-zynqmp.h | 22 ++++++++++++++++++++++
>  drivers/clk/zynqmp/clkc.c       | 25 +++++++++++++++++++++++--
>  2 files changed, 45 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
> index 5beeb41..d8e580b 100644
> --- a/drivers/clk/zynqmp/clk-zynqmp.h
> +++ b/drivers/clk/zynqmp/clk-zynqmp.h
> @@ -10,6 +10,28 @@
> 
>  #include <linux/firmware/xlnx-zynqmp.h>
> 
> +/* Common Flags */
> +/* must be gated across rate change */
> +#define ZYNQMP_CLK_SET_RATE_GATE       BIT(0)
> +/* must be gated across re-parent */
> +#define ZYNQMP_CLK_SET_PARENT_GATE     BIT(1)
> +/* propagate rate change up one level */
> +#define ZYNQMP_CLK_SET_RATE_PARENT     BIT(2)
> +/* do not gate even if unused */
> +#define ZYNQMP_CLK_IGNORE_UNUSED       BIT(3)
> +/* do not use the cached clk rate */
> +#define ZYNQMP_CLK_GET_RATE_NOCACHE    BIT(6)
> +/* don't re-parent on rate change */
> +#define ZYNQMP_CLK_SET_RATE_NO_REPARENT        BIT(7)
> +/* do not use the cached clk accuracy */
> +#define ZYNQMP_CLK_GET_ACCURACY_NOCACHE        BIT(8)
> +/* recalc rates after notifications */
> +#define ZYNQMP_CLK_RECALC_NEW_RATES    BIT(9)
> +/* clock needs to run to set rate */
> +#define ZYNQMP_CLK_SET_RATE_UNGATE     BIT(10)
> +/* do not gate, ever */
> +#define ZYNQMP_CLK_IS_CRITICAL         BIT(11)
> +
>  enum topology_type {
>         TYPE_INVALID,
>         TYPE_MUX,
> diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> index db8d0d7..8663587 100644
> --- a/drivers/clk/zynqmp/clkc.c
> +++ b/drivers/clk/zynqmp/clkc.c
> @@ -385,14 +385,35 @@ static int __zynqmp_clock_get_topology(struct clock_topology *topology,
>  {
>         int i;
>         u32 type;
> +       u32 flag;
> 
>         for (i = 0; i < ARRAY_SIZE(response->topology); i++) {
>                 type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]);
>                 if (type == TYPE_INVALID)
>                         return END_OF_TOPOLOGY_NODE;
>                 topology[*nnodes].type = type;
> -               topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS,
> -                                                  response->topology[i]);
> +               flag = FIELD_GET(CLK_TOPOLOGY_FLAGS, response->topology[i]);
> +               topology[*nnodes].flag = 0;
> +               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_SET_RATE_GATE) ?
> +                                          CLK_SET_RATE_GATE : 0;
> +               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_SET_RATE_PARENT) ?
> +                                          CLK_SET_RATE_PARENT : 0;
> +               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_IGNORE_UNUSED) ?
> +                                          CLK_IGNORE_UNUSED : 0;
> +               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_GET_RATE_NOCACHE) ?
> +                                          CLK_GET_RATE_NOCACHE : 0;
> +               topology[*nnodes].flag |= (flag &
> +                                          ZYNQMP_CLK_SET_RATE_NO_REPARENT) ?
> +                                          CLK_SET_RATE_NO_REPARENT : 0;
> +               topology[*nnodes].flag |= (flag &
> +                                          ZYNQMP_CLK_GET_ACCURACY_NOCACHE) ?
> +                                          CLK_GET_ACCURACY_NOCACHE : 0;
> +               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_RECALC_NEW_RATES) ?
> +                                          CLK_RECALC_NEW_RATES : 0;
> +               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_SET_RATE_UNGATE) ?
> +                                          CLK_SET_RATE_UNGATE : 0;
> +               topology[*nnodes].flag |= (flag & ZYNQMP_CLK_IS_CRITICAL) ?
> +                                          CLK_IS_CRITICAL : 0;

I don't think that this is the right location for converting the ZYNQMP_CLK_*
flags to CLK_* flags. Here we are writing the flags to the struct
clock_topology, which is still ZynqMP specific. The conversion should rather
happen in the zynqmp_clk_register_*() functions, because these functions write
the flags to struct clk_init_data, which is part of the common clock
framework.

Maybe you could also add a helper function for converting the flags to make
this more readable.

Michael

>                 topology[*nnodes].type_flag =
>                                 FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
>                                           response->topology[i]);
> --
> 2.7.4
> 
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> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

[PATCH 2/3] clk: zynqmp: Use firmware specific divider clock flags

[Amit Sunil Dhamne]

From: Rajan Vaja <rajan.vaja@xilinx.com>

Use ZynqMP specific divider clock flags instead of using CCF flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
---
 drivers/clk/zynqmp/clk-zynqmp.h |  9 +++++++++
 drivers/clk/zynqmp/divider.c    | 16 +++++++++++++++-
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index d8e580b..ade5e9e 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -32,6 +32,15 @@
 /* do not gate, ever */
 #define ZYNQMP_CLK_IS_CRITICAL         BIT(11)

+/* Type Flags for divider clock */
+#define ZYNQMP_CLK_DIVIDER_ONE_BASED           BIT(0)
+#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO                BIT(1)
+#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO          BIT(2)
+#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK         BIT(3)
+#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST       BIT(4)
+#define ZYNQMP_CLK_DIVIDER_READ_ONLY           BIT(5)
+#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO         BIT(6)
+
 enum topology_type {
        TYPE_INVALID,
        TYPE_MUX,
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 66da02b..f15d6b7 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -319,7 +319,21 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
        /* struct clk_divider assignments */
        div->is_frac = !!((nodes->flag & CLK_FRAC) |
                          (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
-       div->flags = nodes->type_flag;
+       div->flags = 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ?
+                     CLK_DIVIDER_ONE_BASED : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
+                     CLK_DIVIDER_POWER_OF_TWO : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ?
+                     CLK_DIVIDER_ALLOW_ZERO : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
+                     CLK_DIVIDER_HIWORD_MASK : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ?
+                     CLK_DIVIDER_ROUND_CLOSEST : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ?
+                     CLK_DIVIDER_READ_ONLY : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ?
+                     CLK_DIVIDER_MAX_AT_ZERO : 0;
        div->hw.init = &init;
        div->clk_id = clk_id;
        div->div_type = nodes->type;
--
2.7.4

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[PATCH 3/3] clk: zynqmp: Use firmware specific mux clock flags

[Amit Sunil Dhamne]

From: Rajan Vaja <rajan.vaja@xilinx.com>

Use ZynqMP specific mux clock flags instead of using CCF flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
---
 drivers/clk/zynqmp/clk-mux-zynqmp.c | 14 +++++++++++++-
 drivers/clk/zynqmp/clk-zynqmp.h     |  8 ++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
index 0619414..9e365e7 100644
--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
@@ -123,7 +123,19 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
        init.flags = nodes->flag;
        init.parent_names = parents;
        init.num_parents = num_parents;
-       mux->flags = nodes->type_flag;
+       mux->flags = 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) ?
+                     CLK_MUX_INDEX_ONE : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) ?
+                     CLK_MUX_INDEX_BIT : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) ?
+                     CLK_MUX_HIWORD_MASK : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_READ_ONLY) ?
+                     CLK_MUX_READ_ONLY : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) ?
+                     CLK_MUX_ROUND_CLOSEST : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) ?
+                     CLK_MUX_BIG_ENDIAN : 0;
        mux->hw.init = &init;
        mux->clk_id = clk_id;

diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index ade5e9e..a29ab43 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -41,6 +41,14 @@
 #define ZYNQMP_CLK_DIVIDER_READ_ONLY           BIT(5)
 #define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO         BIT(6)

+/* Type Flags for mux clock */
+#define ZYNQMP_CLK_MUX_INDEX_ONE               BIT(0)
+#define ZYNQMP_CLK_MUX_INDEX_BIT               BIT(1)
+#define ZYNQMP_CLK_MUX_HIWORD_MASK             BIT(2)
+#define ZYNQMP_CLK_MUX_READ_ONLY               BIT(3)
+#define ZYNQMP_CLK_MUX_ROUND_CLOSEST           BIT(4)
+#define ZYNQMP_CLK_MUX_BIG_ENDIAN              BIT(5)
+
 enum topology_type {
        TYPE_INVALID,
        TYPE_MUX,
--
2.7.4

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