From: Stephen Boyd <sboyd@kernel.org>
To: Loic Poulain <loic.poulain@linaro.org>, bjorn.andersson@linaro.org
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
amit.kucheria@linaro.org, Ilia Lin <ilialin@codeaurora.org>
Subject: Re: [PATCH v5 3/5] dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
Date: Fri, 10 Jul 2020 17:13:24 -0700 [thread overview]
Message-ID: <159442640418.1987609.16468106693473840191@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1593766185-16346-4-git-send-email-loic.poulain@linaro.org>
Quoting Loic Poulain (2020-07-03 01:49:43)
> From: Ilia Lin <ilialin@codeaurora.org>
>
> Each of the CPU clusters (Power and Perf) on msm8996 are
> clocked via 2 PLLs, a primary and alternate. There are also
> 2 Mux'es, a primary and secondary all connected together
> as shown below
>
> +-------+
> XO | |
> +------------------>0 |
> | |
> PLL/2 | SMUX +----+
> +------->1 | |
> | | | |
> | +-------+ | +-------+
> | +---->0 |
> | | |
> +---------------+ | +----------->1 | CPU clk
> |Primary PLL +----+ PLL_EARLY | | +------>
> | +------+-----------+ +------>2 PMUX |
> +---------------+ | | | |
> | +------+ | +-->3 |
> +--^+ ACD +-----+ | +-------+
> +---------------+ +------+ |
> |Alt PLL | |
> | +---------------------------+
> +---------------+ PLL_EARLY
>
> The primary PLL is what drives the CPU clk, except for times
> when we are reprogramming the PLL itself (for rate changes) when
> we temporarily switch to an alternate PLL. A subsequent patch adds
> support to switch between primary and alternate PLL during rate
> changes.
>
> The primary PLL operates on a single VCO range, between 600MHz
> and 3GHz. However the CPUs do support OPPs with frequencies
> between 300MHz and 600MHz. In order to support running the CPUs
> at those frequencies we end up having to lock the PLL at twice
> the rate and drive the CPU clk via the PLL/2 output and SMUX.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
Applied to clk-next
next prev parent reply other threads:[~2020-07-11 0:13 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 8:49 [PATCH v5 0/5] msm8996 CPU scaling support Loic Poulain
2020-07-03 8:49 ` [PATCH v5 1/5] soc: qcom: Separate kryo l2 accessors from PMU driver Loic Poulain
2020-07-11 0:08 ` Stephen Boyd
2020-07-11 0:12 ` Stephen Boyd
2020-07-03 8:49 ` [PATCH v5 2/5] clk: qcom: Add CPU clock driver for msm8996 Loic Poulain
2020-07-11 0:13 ` Stephen Boyd
2020-07-03 8:49 ` [PATCH v5 3/5] dt-bindings: clk: qcom: Add bindings for CPU clock " Loic Poulain
2020-07-11 0:13 ` Stephen Boyd [this message]
2020-07-13 15:21 ` Rob Herring
2020-07-16 0:53 ` Stephen Boyd
2020-07-03 8:49 ` [PATCH v5 4/5] arch: arm64: dts: msm8996: Rename speedbin node Loic Poulain
2020-07-03 8:49 ` [PATCH v5 5/5] arch: arm64: dts: msm8996: Add CPU opps and thermal Loic Poulain
2020-07-03 14:49 ` Amit Kucheria
2020-07-03 19:33 ` [PATCH v5 0/5] msm8996 CPU scaling support Bjorn Andersson
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