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* [v2 1/4] ACPI: APD: Change name from ST to FCH
       [not found] <20200728082857.10829-1-akshu.agrawal@amd.com>
@ 2020-07-28  8:28 ` Akshu Agrawal
       [not found]   ` <159598596077.1360974.483730969007254506@swboyd.mtv.corp.google.com>
  2020-07-28  8:28 ` [v2 2/4] clk: x86: " Akshu Agrawal
  2020-07-28  8:28 ` [v3 4/4] clk: x86: Support RV architecture Akshu Agrawal
  2 siblings, 1 reply; 9+ messages in thread
From: Akshu Agrawal @ 2020-07-28  8:28 UTC (permalink / raw)
  To: akshu.agrawal
  Cc: sboyd, rafael, Rafael J. Wysocki, Len Brown, Michael Turquette,
	open list:ACPI, open list, open list:COMMON CLK FRAMEWORK

AMD SoC general pupose clk is present in new platforms with
same MMIO mappings. We can reuse the same clk handler support
for other platforms. Hence, changing name from ST(SoC) to FCH(IP)

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
---
v2: pulled in clk changes so that patch compiles individually

 drivers/acpi/acpi_apd.c                            | 14 +++++++-------
 drivers/clk/x86/clk-st.c                           |  4 ++--
 .../linux/platform_data/{clk-st.h => clk-fch.h}    | 10 +++++-----
 3 files changed, 14 insertions(+), 14 deletions(-)
 rename include/linux/platform_data/{clk-st.h => clk-fch.h} (53%)

diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
index ba2612e9a0eb..2d99e46add1a 100644
--- a/drivers/acpi/acpi_apd.c
+++ b/drivers/acpi/acpi_apd.c
@@ -8,7 +8,7 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/platform_data/clk-st.h>
+#include <linux/platform_data/clk-fch.h>
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/clkdev.h>
@@ -79,11 +79,11 @@ static int misc_check_res(struct acpi_resource *ares, void *data)
 	return !acpi_dev_resource_memory(ares, &res);
 }
 
-static int st_misc_setup(struct apd_private_data *pdata)
+static int fch_misc_setup(struct apd_private_data *pdata)
 {
 	struct acpi_device *adev = pdata->adev;
 	struct platform_device *clkdev;
-	struct st_clk_data *clk_data;
+	struct fch_clk_data *clk_data;
 	struct resource_entry *rentry;
 	struct list_head resource_list;
 	int ret;
@@ -106,7 +106,7 @@ static int st_misc_setup(struct apd_private_data *pdata)
 
 	acpi_dev_free_resource_list(&resource_list);
 
-	clkdev = platform_device_register_data(&adev->dev, "clk-st",
+	clkdev = platform_device_register_data(&adev->dev, "clk-fch",
 					       PLATFORM_DEVID_NONE, clk_data,
 					       sizeof(*clk_data));
 	return PTR_ERR_OR_ZERO(clkdev);
@@ -135,8 +135,8 @@ static const struct apd_device_desc cz_uart_desc = {
 	.properties = uart_properties,
 };
 
-static const struct apd_device_desc st_misc_desc = {
-	.setup = st_misc_setup,
+static const struct apd_device_desc fch_misc_desc = {
+	.setup = fch_misc_setup,
 };
 #endif
 
@@ -239,7 +239,7 @@ static const struct acpi_device_id acpi_apd_device_ids[] = {
 	{ "AMD0020", APD_ADDR(cz_uart_desc) },
 	{ "AMDI0020", APD_ADDR(cz_uart_desc) },
 	{ "AMD0030", },
-	{ "AMD0040", APD_ADDR(st_misc_desc)},
+	{ "AMD0040", APD_ADDR(fch_misc_desc)},
 #endif
 #ifdef CONFIG_ARM64
 	{ "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-st.c
index 25d4b97aff9b..c2438874d9f2 100644
--- a/drivers/clk/x86/clk-st.c
+++ b/drivers/clk/x86/clk-st.c
@@ -8,7 +8,7 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
-#include <linux/platform_data/clk-st.h>
+#include <linux/platform_data/clk-fch.h>
 #include <linux/platform_device.h>
 
 /* Clock Driving Strength 2 register */
@@ -31,7 +31,7 @@ static struct clk_hw *hws[ST_MAX_CLKS];
 
 static int st_clk_probe(struct platform_device *pdev)
 {
-	struct st_clk_data *st_data;
+	struct fch_clk_data *st_data;
 
 	st_data = dev_get_platdata(&pdev->dev);
 	if (!st_data || !st_data->base)
diff --git a/include/linux/platform_data/clk-st.h b/include/linux/platform_data/clk-fch.h
similarity index 53%
rename from include/linux/platform_data/clk-st.h
rename to include/linux/platform_data/clk-fch.h
index 7cdb6a402b35..850ca776156d 100644
--- a/include/linux/platform_data/clk-st.h
+++ b/include/linux/platform_data/clk-fch.h
@@ -1,17 +1,17 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * clock framework for AMD Stoney based clock
+ * clock framework for AMD misc clocks
  *
  * Copyright 2018 Advanced Micro Devices, Inc.
  */
 
-#ifndef __CLK_ST_H
-#define __CLK_ST_H
+#ifndef __CLK_FCH_H
+#define __CLK_FCH_H
 
 #include <linux/compiler.h>
 
-struct st_clk_data {
+struct fch_clk_data {
 	void __iomem *base;
 };
 
-#endif /* __CLK_ST_H */
+#endif /* __CLK_FCH_H */
-- 
2.20.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [v2 2/4] clk: x86: Change name from ST to FCH
       [not found] <20200728082857.10829-1-akshu.agrawal@amd.com>
  2020-07-28  8:28 ` [v2 1/4] ACPI: APD: Change name from ST to FCH Akshu Agrawal
@ 2020-07-28  8:28 ` Akshu Agrawal
  2020-07-29  1:25   ` Stephen Boyd
  2020-07-28  8:28 ` [v3 4/4] clk: x86: Support RV architecture Akshu Agrawal
  2 siblings, 1 reply; 9+ messages in thread
From: Akshu Agrawal @ 2020-07-28  8:28 UTC (permalink / raw)
  To: akshu.agrawal
  Cc: sboyd, rafael, Michael Turquette, Rahul Tanwar,
	open list:COMMON CLK FRAMEWORK, open list

AMD SoC general pupose clk is present in new platforms with
minor differences. We can reuse the same clk driver for other
platforms. Hence, changing name from ST(SoC) to FCH(IP)

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
---
v2: Moved some changes to acp:apd patch so that individual patches
compile

 drivers/clk/x86/Makefile                |  2 +-
 drivers/clk/x86/{clk-st.c => clk-fch.c} | 24 ++++++++++++------------
 2 files changed, 13 insertions(+), 13 deletions(-)
 rename drivers/clk/x86/{clk-st.c => clk-fch.c} (75%)

diff --git a/drivers/clk/x86/Makefile b/drivers/clk/x86/Makefile
index 7c774ea7ddeb..18564efdc651 100644
--- a/drivers/clk/x86/Makefile
+++ b/drivers/clk/x86/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
-obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)	+= clk-st.o
+obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)	+= clk-fch.o
 clk-x86-lpss-objs		:= clk-lpt.o
 obj-$(CONFIG_X86_INTEL_LPSS)	+= clk-x86-lpss.o
 obj-$(CONFIG_CLK_LGM_CGU)	+= clk-cgu.o clk-cgu-pll.o clk-lgm.o
diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-fch.c
similarity index 75%
rename from drivers/clk/x86/clk-st.c
rename to drivers/clk/x86/clk-fch.c
index c2438874d9f2..b252f0cf0628 100644
--- a/drivers/clk/x86/clk-st.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -29,12 +29,12 @@
 static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
 static struct clk_hw *hws[ST_MAX_CLKS];
 
-static int st_clk_probe(struct platform_device *pdev)
+static int fch_clk_probe(struct platform_device *pdev)
 {
-	struct fch_clk_data *st_data;
+	struct fch_clk_data *fch_data;
 
-	st_data = dev_get_platdata(&pdev->dev);
-	if (!st_data || !st_data->base)
+	fch_data = dev_get_platdata(&pdev->dev);
+	if (!fch_data || !fch_data->base)
 		return -EINVAL;
 
 	hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
@@ -44,12 +44,12 @@ static int st_clk_probe(struct platform_device *pdev)
 
 	hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
 		clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
-		0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
+		0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
 
 	clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
 
 	hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
-		0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
+		0, fch_data->base + MISCCLKCNTL1, OSCCLKENB,
 		CLK_GATE_SET_TO_DISABLE, NULL);
 
 	devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], "oscout1",
@@ -58,7 +58,7 @@ static int st_clk_probe(struct platform_device *pdev)
 	return 0;
 }
 
-static int st_clk_remove(struct platform_device *pdev)
+static int fch_clk_remove(struct platform_device *pdev)
 {
 	int i;
 
@@ -67,12 +67,12 @@ static int st_clk_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static struct platform_driver st_clk_driver = {
+static struct platform_driver fch_clk_driver = {
 	.driver = {
-		.name = "clk-st",
+		.name = "clk-fch",
 		.suppress_bind_attrs = true,
 	},
-	.probe = st_clk_probe,
-	.remove = st_clk_remove,
+	.probe = fch_clk_probe,
+	.remove = fch_clk_remove,
 };
-builtin_platform_driver(st_clk_driver);
+builtin_platform_driver(fch_clk_driver);
-- 
2.20.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [v3 4/4] clk: x86: Support RV architecture
       [not found] <20200728082857.10829-1-akshu.agrawal@amd.com>
  2020-07-28  8:28 ` [v2 1/4] ACPI: APD: Change name from ST to FCH Akshu Agrawal
  2020-07-28  8:28 ` [v2 2/4] clk: x86: " Akshu Agrawal
@ 2020-07-28  8:28 ` Akshu Agrawal
  2020-07-29  1:26   ` Stephen Boyd
  2 siblings, 1 reply; 9+ messages in thread
From: Akshu Agrawal @ 2020-07-28  8:28 UTC (permalink / raw)
  To: akshu.agrawal
  Cc: sboyd, rafael, Michael Turquette, open list:COMMON CLK FRAMEWORK,
	open list

There is minor difference between previous family of SoC and
the current one. Which is the there is only 48Mh fixed clk.
There is no mux and no option to select another freq as there in previous.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
---
v2: Consolidated the loops in remove.
v3: Removed negation in condition to make it simple

 drivers/clk/x86/clk-fch.c | 53 ++++++++++++++++++++++++++++-----------
 1 file changed, 38 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
index b252f0cf0628..8f7c5142b0f0 100644
--- a/drivers/clk/x86/clk-fch.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -26,6 +26,10 @@
 #define ST_CLK_GATE	3
 #define ST_MAX_CLKS	4
 
+#define RV_CLK_48M	0
+#define RV_CLK_GATE	1
+#define RV_MAX_CLKS	2
+
 static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
 static struct clk_hw *hws[ST_MAX_CLKS];
 
@@ -37,33 +41,52 @@ static int fch_clk_probe(struct platform_device *pdev)
 	if (!fch_data || !fch_data->base)
 		return -EINVAL;
 
-	hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
-						     48000000);
-	hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
-						     25000000);
+	if (!fch_data->is_rv) {
+		hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
+			NULL, 0, 48000000);
+		hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
+			NULL, 0, 25000000);
+
+		hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
+			clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
+			0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0,
+			NULL);
 
-	hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
-		clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
-		0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
+		clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
 
-	clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
+		hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
+			"oscout1_mux", 0, fch_data->base + MISCCLKCNTL1,
+			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
 
-	hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
-		0, fch_data->base + MISCCLKCNTL1, OSCCLKENB,
-		CLK_GATE_SET_TO_DISABLE, NULL);
+		devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],
+			"oscout1", NULL);
+	} else {
+		hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
+			NULL, 0, 48000000);
 
-	devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], "oscout1",
-				    NULL);
+		hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
+			"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
+			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
+
+		devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE],
+			"oscout1", NULL);
+	}
 
 	return 0;
 }
 
 static int fch_clk_remove(struct platform_device *pdev)
 {
-	int i;
+	int i, clks;
+	struct fch_clk_data *fch_data;
 
-	for (i = 0; i < ST_MAX_CLKS; i++)
+	fch_data = dev_get_platdata(&pdev->dev);
+
+	clks = fch_data->is_rv ? RV_MAX_CLKS : ST_MAX_CLKS;
+
+	for (i = 0; i < clks; i++)
 		clk_hw_unregister(hws[i]);
+
 	return 0;
 }
 
-- 
2.20.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [v2 2/4] clk: x86: Change name from ST to FCH
  2020-07-28  8:28 ` [v2 2/4] clk: x86: " Akshu Agrawal
@ 2020-07-29  1:25   ` Stephen Boyd
  0 siblings, 0 replies; 9+ messages in thread
From: Stephen Boyd @ 2020-07-29  1:25 UTC (permalink / raw)
  To: akshu.agrawal
  Cc: rafael, Michael Turquette, Rahul Tanwar, linux-clk, linux-kernel

Quoting Akshu Agrawal (2020-07-28 01:28:54)
> AMD SoC general pupose clk is present in new platforms with
> minor differences. We can reuse the same clk driver for other
> platforms. Hence, changing name from ST(SoC) to FCH(IP)
> 
> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [v3 4/4] clk: x86: Support RV architecture
  2020-07-28  8:28 ` [v3 4/4] clk: x86: Support RV architecture Akshu Agrawal
@ 2020-07-29  1:26   ` Stephen Boyd
  0 siblings, 0 replies; 9+ messages in thread
From: Stephen Boyd @ 2020-07-29  1:26 UTC (permalink / raw)
  To: akshu.agrawal; +Cc: rafael, Michael Turquette, linux-clk, linux-kernel

Quoting Akshu Agrawal (2020-07-28 01:28:56)
> There is minor difference between previous family of SoC and
> the current one. Which is the there is only 48Mh fixed clk.
> There is no mux and no option to select another freq as there in previous.
> 
> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [v2 1/4] ACPI: APD: Change name from ST to FCH
       [not found]   ` <159598596077.1360974.483730969007254506@swboyd.mtv.corp.google.com>
@ 2020-07-31  0:44     ` Agrawal, Akshu
  2020-07-31 11:14       ` Rafael J. Wysocki
  0 siblings, 1 reply; 9+ messages in thread
From: Agrawal, Akshu @ 2020-07-31  0:44 UTC (permalink / raw)
  To: Stephen Boyd, akshu.agrawal
  Cc: rafael, Rafael J. Wysocki, Len Brown, Michael Turquette,
	linux-acpi, linux-kernel, linux-clk


On 7/29/2020 6:56 AM, Stephen Boyd wrote:
> Quoting Akshu Agrawal (2020-07-28 01:28:53)
>> AMD SoC general pupose clk is present in new platforms with
>> same MMIO mappings. We can reuse the same clk handler support
>> for other platforms. Hence, changing name from ST(SoC) to FCH(IP)
>>
>> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
>> ---
> Acked-by: Stephen Boyd <sboyd@kernel.org>

Hi Rafael,
I see the status of these patches as Not Applicable in patchwork, is 
there any pending action for me?
Thanks,
Akshu


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [v2 1/4] ACPI: APD: Change name from ST to FCH
  2020-07-31  0:44     ` Agrawal, Akshu
@ 2020-07-31 11:14       ` Rafael J. Wysocki
  2020-07-31 13:33         ` Agrawal, Akshu
  0 siblings, 1 reply; 9+ messages in thread
From: Rafael J. Wysocki @ 2020-07-31 11:14 UTC (permalink / raw)
  To: Agrawal, Akshu
  Cc: Stephen Boyd, Agrawal, Akshu, Rafael J. Wysocki,
	Rafael J. Wysocki, Len Brown, Michael Turquette,
	ACPI Devel Maling List, Linux Kernel Mailing List, linux-clk

On Fri, Jul 31, 2020 at 2:44 AM Agrawal, Akshu <aagrawal2@amd.com> wrote:
>
>
> On 7/29/2020 6:56 AM, Stephen Boyd wrote:
> > Quoting Akshu Agrawal (2020-07-28 01:28:53)
> >> AMD SoC general pupose clk is present in new platforms with
> >> same MMIO mappings. We can reuse the same clk handler support
> >> for other platforms. Hence, changing name from ST(SoC) to FCH(IP)
> >>
> >> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
> >> ---
> > Acked-by: Stephen Boyd <sboyd@kernel.org>
>
> Hi Rafael,
> I see the status of these patches as Not Applicable in patchwork, is
> there any pending action for me?

Yes, there is.

You need to let me know if you want me to apply them (and I mean the
whole series). :-)

Besides, I only can see 3 out of 4 patches, so if you want me to apply
them, can you please resend the whole series with CCs to linux-acpi?

Thanks!

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [v2 1/4] ACPI: APD: Change name from ST to FCH
  2020-07-31 11:14       ` Rafael J. Wysocki
@ 2020-07-31 13:33         ` Agrawal, Akshu
  0 siblings, 0 replies; 9+ messages in thread
From: Agrawal, Akshu @ 2020-07-31 13:33 UTC (permalink / raw)
  To: Rafael J. Wysocki
  Cc: Stephen Boyd, Agrawal, Akshu, Rafael J. Wysocki, Len Brown,
	Michael Turquette, ACPI Devel Maling List,
	Linux Kernel Mailing List, linux-clk


On 7/31/2020 4:44 PM, Rafael J. Wysocki wrote:
> On Fri, Jul 31, 2020 at 2:44 AM Agrawal, Akshu <aagrawal2@amd.com> wrote:
>>
>> On 7/29/2020 6:56 AM, Stephen Boyd wrote:
>>> Quoting Akshu Agrawal (2020-07-28 01:28:53)
>>>> AMD SoC general pupose clk is present in new platforms with
>>>> same MMIO mappings. We can reuse the same clk handler support
>>>> for other platforms. Hence, changing name from ST(SoC) to FCH(IP)
>>>>
>>>> Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
>>>> ---
>>> Acked-by: Stephen Boyd <sboyd@kernel.org>
>> Hi Rafael,
>> I see the status of these patches as Not Applicable in patchwork, is
>> there any pending action for me?
> Yes, there is.
>
> You need to let me know if you want me to apply them (and I mean the
> whole series). :-)
Yes, please apply the whole series.
>
> Besides, I only can see 3 out of 4 patches, so if you want me to apply
> them, can you please resend the whole series with CCs to linux-acpi?

Sending them again with cc to linux-acpi.

Thanks,

Akshu


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [v2 2/4] clk: x86: Change name from ST to FCH
  2020-07-31 13:36 [0/4] Extend AMD SoC general purpose clk for all versions Akshu Agrawal
@ 2020-07-31 13:36 ` Akshu Agrawal
  0 siblings, 0 replies; 9+ messages in thread
From: Akshu Agrawal @ 2020-07-31 13:36 UTC (permalink / raw)
  To: akshu.agrawal
  Cc: sboyd, rafael, rjw, lenb, mturquette, linux-acpi, linux-kernel,
	linux-clk, rahul.tanwar

AMD SoC general pupose clk is present in new platforms with
minor differences. We can reuse the same clk driver for other
platforms. Hence, changing name from ST(SoC) to FCH(IP)

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
---
v2: Moved some changes to acp:apd patch so that individual patches
compile

 drivers/clk/x86/Makefile                |  2 +-
 drivers/clk/x86/{clk-st.c => clk-fch.c} | 24 ++++++++++++------------
 2 files changed, 13 insertions(+), 13 deletions(-)
 rename drivers/clk/x86/{clk-st.c => clk-fch.c} (75%)

diff --git a/drivers/clk/x86/Makefile b/drivers/clk/x86/Makefile
index 7c774ea7ddeb..18564efdc651 100644
--- a/drivers/clk/x86/Makefile
+++ b/drivers/clk/x86/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
-obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)	+= clk-st.o
+obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)	+= clk-fch.o
 clk-x86-lpss-objs		:= clk-lpt.o
 obj-$(CONFIG_X86_INTEL_LPSS)	+= clk-x86-lpss.o
 obj-$(CONFIG_CLK_LGM_CGU)	+= clk-cgu.o clk-cgu-pll.o clk-lgm.o
diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-fch.c
similarity index 75%
rename from drivers/clk/x86/clk-st.c
rename to drivers/clk/x86/clk-fch.c
index c2438874d9f2..b252f0cf0628 100644
--- a/drivers/clk/x86/clk-st.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -29,12 +29,12 @@
 static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
 static struct clk_hw *hws[ST_MAX_CLKS];
 
-static int st_clk_probe(struct platform_device *pdev)
+static int fch_clk_probe(struct platform_device *pdev)
 {
-	struct fch_clk_data *st_data;
+	struct fch_clk_data *fch_data;
 
-	st_data = dev_get_platdata(&pdev->dev);
-	if (!st_data || !st_data->base)
+	fch_data = dev_get_platdata(&pdev->dev);
+	if (!fch_data || !fch_data->base)
 		return -EINVAL;
 
 	hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
@@ -44,12 +44,12 @@ static int st_clk_probe(struct platform_device *pdev)
 
 	hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
 		clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
-		0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
+		0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
 
 	clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
 
 	hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
-		0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
+		0, fch_data->base + MISCCLKCNTL1, OSCCLKENB,
 		CLK_GATE_SET_TO_DISABLE, NULL);
 
 	devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], "oscout1",
@@ -58,7 +58,7 @@ static int st_clk_probe(struct platform_device *pdev)
 	return 0;
 }
 
-static int st_clk_remove(struct platform_device *pdev)
+static int fch_clk_remove(struct platform_device *pdev)
 {
 	int i;
 
@@ -67,12 +67,12 @@ static int st_clk_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static struct platform_driver st_clk_driver = {
+static struct platform_driver fch_clk_driver = {
 	.driver = {
-		.name = "clk-st",
+		.name = "clk-fch",
 		.suppress_bind_attrs = true,
 	},
-	.probe = st_clk_probe,
-	.remove = st_clk_remove,
+	.probe = fch_clk_probe,
+	.remove = fch_clk_remove,
 };
-builtin_platform_driver(st_clk_driver);
+builtin_platform_driver(fch_clk_driver);
-- 
2.20.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

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Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <20200728082857.10829-1-akshu.agrawal@amd.com>
2020-07-28  8:28 ` [v2 1/4] ACPI: APD: Change name from ST to FCH Akshu Agrawal
     [not found]   ` <159598596077.1360974.483730969007254506@swboyd.mtv.corp.google.com>
2020-07-31  0:44     ` Agrawal, Akshu
2020-07-31 11:14       ` Rafael J. Wysocki
2020-07-31 13:33         ` Agrawal, Akshu
2020-07-28  8:28 ` [v2 2/4] clk: x86: " Akshu Agrawal
2020-07-29  1:25   ` Stephen Boyd
2020-07-28  8:28 ` [v3 4/4] clk: x86: Support RV architecture Akshu Agrawal
2020-07-29  1:26   ` Stephen Boyd
2020-07-31 13:36 [0/4] Extend AMD SoC general purpose clk for all versions Akshu Agrawal
2020-07-31 13:36 ` [v2 2/4] clk: x86: Change name from ST to FCH Akshu Agrawal

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