From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FC3FC433DF for ; Wed, 29 Jul 2020 08:04:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5514221744 for ; Wed, 29 Jul 2020 08:04:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726797AbgG2IEm (ORCPT ); Wed, 29 Jul 2020 04:04:42 -0400 Received: from inva020.nxp.com ([92.121.34.13]:34338 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726548AbgG2IEl (ORCPT ); Wed, 29 Jul 2020 04:04:41 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 885191A0F39; Wed, 29 Jul 2020 10:04:39 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C8FD31A0F3E; Wed, 29 Jul 2020 10:04:35 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id DB2BF402DF; Wed, 29 Jul 2020 10:04:30 +0200 (CEST) From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, mturquette@baylibre.com, shawnguo@kernel.org, fabio.estevam@nxp.com, linux-imx@nxp.com, kernel@pengutronix.de, Dong Aisheng Subject: [PATCH v7 00/11] clk: imx8: add new clock binding for better pm support Date: Wed, 29 Jul 2020 16:00:07 +0800 Message-Id: <1596009618-25516-1-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch series is a preparation for the MX8 Architecture improvement. As for IMX SCU based platforms like MX8QM and MX8QXP, they are comprised of a couple of SS(Subsystems) while most of them within the same SS can be shared. e.g. Clocks, Devices and etc. However, current clock binding is using SW IDs for device tree to use which can cause troubles in writing the common -ss-xx.dtsi file for different SoCs. This patch series aims to introduce a new binding which is more close to hardware and platform independent and can makes us write a more general drivers for different SCU based SoCs. Another important thing is that on MX8, each Clock resource is associated with a power domain. So we have to attach that clock device to the power domain in order to make it work properly. Further more, the clock state will be lost when its power domain is completely off during suspend/resume, so we also introduce the clock state save&restore mechanism. It's based on latest shanw/for-next branch. The top commit is: 3c1a41dab7b8 Merge branch 'imx/defconfig' into for-next ChangeLog: v6->v7: * addressed all comments from Stephen * rebased to latest shawn/for-next v5->v6: * add scu clk unregister if add provider failed v4->v5: * Address all comments from Stephen v3->v4: * use clk-indices for LPCG to fetch each clks offset from dt v2->v3: * change scu clk into two cells binding * add clk pm patches to ease the understand of the changes v1->v2: * SCU clock changed to one cell clock binding inspired by arm,scpi.txt Documentation/devicetree/bindings/arm/arm,scpi.txt * Add required power domain property * Dropped PATCH 3&4 first, will send the updated version accordingly after the binding is finally determined, Dong Aisheng (11): dt-bindings: firmware: imx-scu: new binding to parse clocks from device tree dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree clk: imx: scu: add two cells binding support clk: imx: scu: bypass cpu power domains clk: imx: scu: allow scu clk to take device pointer clk: imx: scu: add runtime pm support clk: imx: scu: add suspend/resume support clk: imx: imx8qxp-lpcg: add parsing clocks from device tree clk: imx: lpcg: allow lpcg clk to take device pointer clk: imx: clk-imx8qxp-lpcg: add runtime pm support clk: imx: lpcg: add suspend/resume support .../bindings/arm/freescale/fsl,scu.txt | 12 +- .../bindings/clock/imx8qxp-lpcg.yaml | 79 ++++-- drivers/clk/imx/clk-imx8qxp-lpcg.c | 139 +++++++++++ drivers/clk/imx/clk-imx8qxp.c | 136 +++++----- drivers/clk/imx/clk-lpcg-scu.c | 53 +++- drivers/clk/imx/clk-scu.c | 234 +++++++++++++++++- drivers/clk/imx/clk-scu.h | 56 ++++- include/dt-bindings/clock/imx8-lpcg.h | 14 ++ 8 files changed, 620 insertions(+), 103 deletions(-) create mode 100644 include/dt-bindings/clock/imx8-lpcg.h -- 2.23.0